drivers/clk/clk-axi-clkgen.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * AXI clkgen driver
   4  *
   5  * Copyright 2012-2013 Analog Devices Inc.
   6  *  Author: Lars-Peter Clausen <lars@metafoo.de>
   7  */
   8
   9 #include <linux/platform_device.h>
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/slab.h>
  13 #include <linux/io.h>
  14 #include <linux/of.h>
  15 #include <linux/module.h>
  16 #include <linux/err.h>
  17
  18 #define AXI_CLKGEN_V2_REG_RESET         0x40
  19 #define AXI_CLKGEN_V2_REG_CLKSEL        0x44
  20 #define AXI_CLKGEN_V2_REG_DRP_CNTRL     0x70
  21 #define AXI_CLKGEN_V2_REG_DRP_STATUS    0x74
  22
  23 #define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1)
  24 #define AXI_CLKGEN_V2_RESET_ENABLE      BIT(0)
  25
  26 #define AXI_CLKGEN_V2_DRP_CNTRL_SEL     BIT(29)
  27 #define AXI_CLKGEN_V2_DRP_CNTRL_READ    BIT(28)
  28
  29 #define AXI_CLKGEN_V2_DRP_STATUS_BUSY   BIT(16)
  30
  31 #define MMCM_REG_CLKOUT5_2      0x07
  32 #define MMCM_REG_CLKOUT0_1      0x08
  33 #define MMCM_REG_CLKOUT0_2      0x09
  34 #define MMCM_REG_CLKOUT6_2      0x13
  35 #define MMCM_REG_CLK_FB1        0x14
  36 #define MMCM_REG_CLK_FB2        0x15
  37 #define MMCM_REG_CLK_DIV        0x16
  38 #define MMCM_REG_LOCK1          0x18
  39 #define MMCM_REG_LOCK2          0x19
  40 #define MMCM_REG_LOCK3          0x1a
  41 #define MMCM_REG_POWER          0x28
  42 #define MMCM_REG_FILTER1        0x4e
  43 #define MMCM_REG_FILTER2        0x4f
  44
  45 #define MMCM_CLKOUT_NOCOUNT     BIT(6)
  46
  47 #define MMCM_CLK_DIV_DIVIDE     BIT(11)
  48 #define MMCM_CLK_DIV_NOCOUNT    BIT(12)
  49
  50 struct axi_clkgen_limits {
  51         unsigned int fpfd_min;
  52         unsigned int fpfd_max;
  53         unsigned int fvco_min;
  54         unsigned int fvco_max;
  55 };
  56
  57 struct axi_clkgen {
  58         void __iomem *base;
  59         struct clk_hw clk_hw;
  60         struct axi_clkgen_limits limits;
  61 };
  62
  63 static uint32_t axi_clkgen_lookup_filter(unsigned int m)
  64 {
  65         switch (m) {
  66         case 0:
  67                 return 0x01001990;
  68         case 1:
  69                 return 0x01001190;
  70         case 2:
  71                 return 0x01009890;
  72         case 3:
  73                 return 0x01001890;
  74         case 4:
  75                 return 0x01008890;
  76         case 5 ... 8:
  77                 return 0x01009090;
  78         case 9 ... 11:
  79                 return 0x01000890;
  80         case 12:
  81                 return 0x08009090;
  82         case 13 ... 22:
  83                 return 0x01001090;
  84         case 23 ... 36:
  85                 return 0x01008090;
  86         case 37 ... 46:
  87                 return 0x08001090;
  88         default:
  89                 return 0x08008090;
  90         }
  91 }
  92
  93 static const uint32_t axi_clkgen_lock_table[] = {
  94         0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
  95         0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
  96         0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
  97         0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
  98         0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
  99         0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
 100         0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
 101         0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
 102         0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
 103 };
 104
 105 static uint32_t axi_clkgen_lookup_lock(unsigned int m)
 106 {
 107         if (m < ARRAY_SIZE(axi_clkgen_lock_table))
 108                 return axi_clkgen_lock_table[m];
 109         return 0x1f1f00fa;
 110 }
 111
 112 static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = {
 113         .fpfd_min = 10000,
 114         .fpfd_max = 450000,
 115         .fvco_min = 800000,
 116         .fvco_max = 1600000,
 117 };
 118
 119 static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = {
 120         .fpfd_min = 10000,
 121         .fpfd_max = 300000,
 122         .fvco_min = 600000,
 123         .fvco_max = 1200000,
 124 };
 125
 126 static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits,
 127         unsigned long fin, unsigned long fout,
 128         unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
 129 {
 130         unsigned long d, d_min, d_max, _d_min, _d_max;
 131         unsigned long m, m_min, m_max;
 132         unsigned long f, dout, best_f, fvco;
 133         unsigned long fract_shift = 0;
 134         unsigned long fvco_min_fract, fvco_max_fract;
 135
 136         fin /= 1000;
 137         fout /= 1000;
 138
 139         best_f = ULONG_MAX;
 140         *best_d = 0;
 141         *best_m = 0;
 142         *best_dout = 0;
 143
 144         d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1);
 145         d_max = min_t(unsigned long, fin / limits->fpfd_min, 80);
 146
 147 again:
 148         fvco_min_fract = limits->fvco_min << fract_shift;
 149         fvco_max_fract = limits->fvco_max << fract_shift;
 150
 151         m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1);
 152         m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift);
 153
 154         for (m = m_min; m <= m_max; m++) {
 155                 _d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max_fract));
 156                 _d_max = min(d_max, fin * m / fvco_min_fract);
 157
 158                 for (d = _d_min; d <= _d_max; d++) {
 159                         fvco = fin * m / d;
 160
 161                         dout = DIV_ROUND_CLOSEST(fvco, fout);
 162                         dout = clamp_t(unsigned long, dout, 1, 128 << fract_shift);
 163                         f = fvco / dout;
 164                         if (abs(f - fout) < abs(best_f - fout)) {
 165                                 best_f = f;
 166                                 *best_d = d;
 167                                 *best_m = m << (3 - fract_shift);
 168                                 *best_dout = dout << (3 - fract_shift);
 169                                 if (best_f == fout)
 170                                         return;
 171                         }
 172                 }
 173         }
 174
 175         /* Lets see if we find a better setting in fractional mode */
 176         if (fract_shift == 0) {
 177                 fract_shift = 3;
 178                 goto again;
 179         }
 180 }
 181
 182 struct axi_clkgen_div_params {
 183         unsigned int low;
 184         unsigned int high;
 185         unsigned int edge;
 186         unsigned int nocount;
 187         unsigned int frac_en;
 188         unsigned int frac;
 189         unsigned int frac_wf_f;
 190         unsigned int frac_wf_r;
 191         unsigned int frac_phase;
 192 };
 193
 194 static void axi_clkgen_calc_clk_params(unsigned int divider,
 195         unsigned int frac_divider, struct axi_clkgen_div_params *params)
 196 {
 197
 198         memset(params, 0x0, sizeof(*params));
 199
 200         if (divider == 1) {
 201                 params->nocount = 1;
 202                 return;
 203         }
 204
 205         if (frac_divider == 0) {
 206                 params->high = divider / 2;
 207                 params->edge = divider % 2;
 208                 params->low = divider - params->high;
 209         } else {
 210                 params->frac_en = 1;
 211                 params->frac = frac_divider;
 212
 213                 params->high = divider / 2;
 214                 params->edge = divider % 2;
 215                 params->low = params->high;
 216
 217                 if (params->edge == 0) {
 218                         params->high--;
 219                         params->frac_wf_r = 1;
 220                 }
 221
 222                 if (params->edge == 0 || frac_divider == 1)
 223                         params->low--;
 224                 if (((params->edge == 0) ^ (frac_divider == 1)) ||
 225                         (divider == 2 && frac_divider == 1))
 226                         params->frac_wf_f = 1;
 227
 228                 params->frac_phase = params->edge * 4 + frac_divider / 2;
 229         }
 230 }
 231
 232 static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
 233         unsigned int reg, unsigned int val)
 234 {
 235         writel(val, axi_clkgen->base + reg);
 236 }
 237
 238 static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
 239         unsigned int reg, unsigned int *val)
 240 {
 241         *val = readl(axi_clkgen->base + reg);
 242 }
 243
 244 static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
 245 {
 246         unsigned int timeout = 10000;
 247         unsigned int val;
 248
 249         do {
 250                 axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
 251         } while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
 252
 253         if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
 254                 return -EIO;
 255
 256         return val & 0xffff;
 257 }
 258
 259 static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
 260         unsigned int reg, unsigned int *val)
 261 {
 262         unsigned int reg_val;
 263         int ret;
 264
 265         ret = axi_clkgen_wait_non_busy(axi_clkgen);
 266         if (ret < 0)
 267                 return ret;
 268
 269         reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;
 270         reg_val |= (reg << 16);
 271
 272         axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
 273
 274         ret = axi_clkgen_wait_non_busy(axi_clkgen);
 275         if (ret < 0)
 276                 return ret;
 277
 278         *val = ret;
 279
 280         return 0;
 281 }
 282
 283 static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
 284         unsigned int reg, unsigned int val, unsigned int mask)
 285 {
 286         unsigned int reg_val = 0;
 287         int ret;
 288
 289         ret = axi_clkgen_wait_non_busy(axi_clkgen);
 290         if (ret < 0)
 291                 return ret;
 292
 293         if (mask != 0xffff) {
 294                 axi_clkgen_mmcm_read(axi_clkgen, reg, &reg_val);
 295                 reg_val &= ~mask;
 296         }
 297
 298         reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);
 299
 300         axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
 301
 302         return 0;
 303 }
 304
 305 static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
 306         bool enable)
 307 {
 308         unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
 309
 310         if (enable)
 311                 val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;
 312
 313         axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
 314 }
 315
 316 static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
 317 {
 318         return container_of(clk_hw, struct axi_clkgen, clk_hw);
 319 }
 320
 321 static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen,
 322         unsigned int reg1, unsigned int reg2, unsigned int reg3,
 323         struct axi_clkgen_div_params *params)
 324 {
 325         axi_clkgen_mmcm_write(axi_clkgen, reg1,
 326                 (params->high << 6) | params->low, 0xefff);
 327         axi_clkgen_mmcm_write(axi_clkgen, reg2,
 328                 (params->frac << 12) | (params->frac_en << 11) |
 329                 (params->frac_wf_r << 10) | (params->edge << 7) |
 330                 (params->nocount << 6), 0x7fff);
 331         if (reg3 != 0) {
 332                 axi_clkgen_mmcm_write(axi_clkgen, reg3,
 333                         (params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00);
 334         }
 335 }
 336
 337 static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
 338         unsigned long rate, unsigned long parent_rate)
 339 {
 340         struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
 341         const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
 342         unsigned int d, m, dout;
 343         struct axi_clkgen_div_params params;
 344         uint32_t power = 0;
 345         uint32_t filter;
 346         uint32_t lock;
 347
 348         if (parent_rate == 0 || rate == 0)
 349                 return -EINVAL;
 350
 351         axi_clkgen_calc_params(limits, parent_rate, rate, &d, &m, &dout);
 352
 353         if (d == 0 || dout == 0 || m == 0)
 354                 return -EINVAL;
 355
 356         if ((dout & 0x7) != 0 || (m & 0x7) != 0)
 357                 power |= 0x9800;
 358
 359         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800);
 360
 361         filter = axi_clkgen_lookup_filter(m - 1);
 362         lock = axi_clkgen_lookup_lock(m - 1);
 363
 364         axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, &params);
 365         axi_clkgen_set_div(axi_clkgen,  MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2,
 366                 MMCM_REG_CLKOUT5_2, &params);
 367
 368         axi_clkgen_calc_clk_params(d, 0, &params);
 369         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
 370                 (params.edge << 13) | (params.nocount << 12) |
 371                 (params.high << 6) | params.low, 0x3fff);
 372
 373         axi_clkgen_calc_clk_params(m >> 3, m & 0x7, &params);
 374         axi_clkgen_set_div(axi_clkgen,  MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2,
 375                 MMCM_REG_CLKOUT6_2, &params);
 376
 377         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
 378         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
 379                 (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
 380         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
 381                 (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
 382         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
 383         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
 384
 385         return 0;
 386 }
 387
 388 static int axi_clkgen_determine_rate(struct clk_hw *hw,
 389                                      struct clk_rate_request *req)
 390 {
 391         struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(hw);
 392         const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
 393         unsigned int d, m, dout;
 394         unsigned long long tmp;
 395
 396         axi_clkgen_calc_params(limits, req->best_parent_rate, req->rate,
 397                                &d, &m, &dout);
 398
 399         if (d == 0 || dout == 0 || m == 0)
 400                 return -EINVAL;
 401
 402         tmp = (unsigned long long)req->best_parent_rate * m;
 403         tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
 404
 405         req->rate = min_t(unsigned long long, tmp, LONG_MAX);
 406         return 0;
 407 }
 408
 409 static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
 410         unsigned int reg1, unsigned int reg2)
 411 {
 412         unsigned int val1, val2;
 413         unsigned int div;
 414
 415         axi_clkgen_mmcm_read(axi_clkgen, reg2, &val2);
 416         if (val2 & MMCM_CLKOUT_NOCOUNT)
 417                 return 8;
 418
 419         axi_clkgen_mmcm_read(axi_clkgen, reg1, &val1);
 420
 421         div = (val1 & 0x3f) + ((val1 >> 6) & 0x3f);
 422         div <<= 3;
 423
 424         if (val2 & MMCM_CLK_DIV_DIVIDE) {
 425                 if ((val2 & BIT(7)) && (val2 & 0x7000) != 0x1000)
 426                         div += 8;
 427                 else
 428                         div += 16;
 429
 430                 div += (val2 >> 12) & 0x7;
 431         }
 432
 433         return div;
 434 }
 435
 436 static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
 437         unsigned long parent_rate)
 438 {
 439         struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
 440         unsigned int d, m, dout;
 441         unsigned long long tmp;
 442         unsigned int val;
 443
 444         dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1,
 445                 MMCM_REG_CLKOUT0_2);
 446         m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1,
 447                 MMCM_REG_CLK_FB2);
 448
 449         axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val);
 450         if (val & MMCM_CLK_DIV_NOCOUNT)
 451                 d = 1;
 452         else
 453                 d = (val & 0x3f) + ((val >> 6) & 0x3f);
 454
 455         if (d == 0 || dout == 0)
 456                 return 0;
 457
 458         tmp = (unsigned long long)parent_rate * m;
 459         tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
 460
 461         return min_t(unsigned long long, tmp, ULONG_MAX);
 462 }
 463
 464 static int axi_clkgen_enable(struct clk_hw *clk_hw)
 465 {
 466         struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
 467
 468         axi_clkgen_mmcm_enable(axi_clkgen, true);
 469
 470         return 0;
 471 }
 472
 473 static void axi_clkgen_disable(struct clk_hw *clk_hw)
 474 {
 475         struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
 476
 477         axi_clkgen_mmcm_enable(axi_clkgen, false);
 478 }
 479
 480 static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
 481 {
 482         struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
 483
 484         axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index);
 485
 486         return 0;
 487 }
 488
 489 static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
 490 {
 491         struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
 492         unsigned int parent;
 493
 494         axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent);
 495
 496         return parent;
 497 }
 498
 499 static const struct clk_ops axi_clkgen_ops = {
 500         .recalc_rate = axi_clkgen_recalc_rate,
 501         .determine_rate = axi_clkgen_determine_rate,
 502         .set_rate = axi_clkgen_set_rate,
 503         .enable = axi_clkgen_enable,
 504         .disable = axi_clkgen_disable,
 505         .set_parent = axi_clkgen_set_parent,
 506         .get_parent = axi_clkgen_get_parent,
 507 };
 508
 509 static int axi_clkgen_probe(struct platform_device *pdev)
 510 {
 511         const struct axi_clkgen_limits *dflt_limits;
 512         struct axi_clkgen *axi_clkgen;
 513         struct clk_init_data init;
 514         const char *parent_names[2];
 515         const char *clk_name;
 516         struct clk *axi_clk;
 517         unsigned int i;
 518         int ret;
 519
 520         dflt_limits = device_get_match_data(&pdev->dev);
 521         if (!dflt_limits)
 522                 return -ENODEV;
 523
 524         axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
 525         if (!axi_clkgen)
 526                 return -ENOMEM;
 527
 528         axi_clkgen->base = devm_platform_ioremap_resource(pdev, 0);
 529         if (IS_ERR(axi_clkgen->base))
 530                 return PTR_ERR(axi_clkgen->base);
 531
 532         init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
 533
 534         axi_clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
 535         if (!IS_ERR(axi_clk)) {
 536                 if (init.num_parents < 2 || init.num_parents > 3)
 537                         return -EINVAL;
 538
 539                 init.num_parents -= 1;
 540         } else {
 541                 /*
 542                  * Legacy... So that old DTs which do not have clock-names still
 543                  * work. In this case we don't explicitly enable the AXI bus
 544                  * clock.
 545                  */
 546                 if (PTR_ERR(axi_clk) != -ENOENT)
 547                         return PTR_ERR(axi_clk);
 548                 if (init.num_parents < 1 || init.num_parents > 2)
 549                         return -EINVAL;
 550         }
 551
 552         for (i = 0; i < init.num_parents; i++) {
 553                 parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
 554                 if (!parent_names[i])
 555                         return -EINVAL;
 556         }
 557
 558         memcpy(&axi_clkgen->limits, dflt_limits, sizeof(axi_clkgen->limits));
 559
 560         clk_name = pdev->dev.of_node->name;
 561         of_property_read_string(pdev->dev.of_node, "clock-output-names",
 562                 &clk_name);
 563
 564         init.name = clk_name;
 565         init.ops = &axi_clkgen_ops;
 566         init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
 567         init.parent_names = parent_names;
 568
 569         axi_clkgen_mmcm_enable(axi_clkgen, false);
 570
 571         axi_clkgen->clk_hw.init = &init;
 572         ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
 573         if (ret)
 574                 return ret;
 575
 576         return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,
 577                                            &axi_clkgen->clk_hw);
 578 }
 579
 580 static const struct of_device_id axi_clkgen_ids[] = {
 581         {
 582                 .compatible = "adi,zynqmp-axi-clkgen-2.00.a",
 583                 .data = &axi_clkgen_zynqmp_default_limits,
 584         },
 585         {
 586                 .compatible = "adi,axi-clkgen-2.00.a",
 587                 .data = &axi_clkgen_zynq_default_limits,
 588         },
 589         { }
 590 };
 591 MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
 592
 593 static struct platform_driver axi_clkgen_driver = {
 594         .driver = {
 595                 .name = "adi-axi-clkgen",
 596                 .of_match_table = axi_clkgen_ids,
 597         },
 598         .probe = axi_clkgen_probe,
 599 };
 600 module_platform_driver(axi_clkgen_driver);
 601
 602 MODULE_LICENSE("GPL v2");
 603 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 604 MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");