| blob | e9e2bfdaaedf8945b08e5a62831f18afadbd67ce |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * clk-si5351.h: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator
4 *
5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 * Rabeeh Khoury <rabeeh@solid-run.com>
7 */
9 #ifndef _CLK_SI5351_H_
10 #define _CLK_SI5351_H_
12 #define SI5351_BUS_BASE_ADDR 0x60
14 #define SI5351_PLL_VCO_MIN 600000000
15 #define SI5351_PLL_VCO_MAX 900000000
16 #define SI5351_MULTISYNTH_MIN_FREQ 1000000
17 #define SI5351_MULTISYNTH_DIVBY4_FREQ 150000000
18 #define SI5351_MULTISYNTH_MAX_FREQ 160000000
19 #define SI5351_MULTISYNTH67_MAX_FREQ SI5351_MULTISYNTH_DIVBY4_FREQ
20 #define SI5351_CLKOUT_MIN_FREQ 8000
21 #define SI5351_CLKOUT_MAX_FREQ SI5351_MULTISYNTH_MAX_FREQ
22 #define SI5351_CLKOUT67_MAX_FREQ SI5351_MULTISYNTH67_MAX_FREQ
24 #define SI5351_PLL_A_MIN 15
25 #define SI5351_PLL_A_MAX 90
26 #define SI5351_PLL_B_MAX (SI5351_PLL_C_MAX-1)
27 #define SI5351_PLL_C_MAX 1048575
28 #define SI5351_MULTISYNTH_A_MIN 6
29 #define SI5351_MULTISYNTH_A_MAX 1800
30 #define SI5351_MULTISYNTH67_A_MAX 254
31 #define SI5351_MULTISYNTH_B_MAX (SI5351_MULTISYNTH_C_MAX-1)
32 #define SI5351_MULTISYNTH_C_MAX 1048575
33 #define SI5351_MULTISYNTH_P1_MAX ((1<<18)-1)
34 #define SI5351_MULTISYNTH_P2_MAX ((1<<20)-1)
35 #define SI5351_MULTISYNTH_P3_MAX ((1<<20)-1)
37 #define SI5351_DEVICE_STATUS 0
38 #define SI5351_INTERRUPT_STATUS 1
39 #define SI5351_INTERRUPT_MASK 2
40 #define SI5351_STATUS_SYS_INIT (1<<7)
41 #define SI5351_STATUS_LOL_B (1<<6)
42 #define SI5351_STATUS_LOL_A (1<<5)
43 #define SI5351_STATUS_LOS (1<<4)
44 #define SI5351_OUTPUT_ENABLE_CTRL 3
45 #define SI5351_OEB_PIN_ENABLE_CTRL 9
46 #define SI5351_PLL_INPUT_SOURCE 15
47 #define SI5351_CLKIN_DIV_MASK (3<<6)
48 #define SI5351_CLKIN_DIV_1 (0<<6)
49 #define SI5351_CLKIN_DIV_2 (1<<6)
50 #define SI5351_CLKIN_DIV_4 (2<<6)
51 #define SI5351_CLKIN_DIV_8 (3<<6)
52 #define SI5351_PLLB_SOURCE (1<<3)
53 #define SI5351_PLLA_SOURCE (1<<2)
55 #define SI5351_CLK0_CTRL 16
56 #define SI5351_CLK1_CTRL 17
57 #define SI5351_CLK2_CTRL 18
58 #define SI5351_CLK3_CTRL 19
59 #define SI5351_CLK4_CTRL 20
60 #define SI5351_CLK5_CTRL 21
61 #define SI5351_CLK6_CTRL 22
62 #define SI5351_CLK7_CTRL 23
63 #define SI5351_CLK_POWERDOWN (1<<7)
64 #define SI5351_CLK_INTEGER_MODE (1<<6)
65 #define SI5351_CLK_PLL_SELECT (1<<5)
66 #define SI5351_CLK_INVERT (1<<4)
67 #define SI5351_CLK_INPUT_MASK (3<<2)
68 #define SI5351_CLK_INPUT_XTAL (0<<2)
69 #define SI5351_CLK_INPUT_CLKIN (1<<2)
70 #define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2<<2)
71 #define SI5351_CLK_INPUT_MULTISYNTH_N (3<<2)
72 #define SI5351_CLK_DRIVE_STRENGTH_MASK (3<<0)
73 #define SI5351_CLK_DRIVE_STRENGTH_2MA (0<<0)
74 #define SI5351_CLK_DRIVE_STRENGTH_4MA (1<<0)
75 #define SI5351_CLK_DRIVE_STRENGTH_6MA (2<<0)
76 #define SI5351_CLK_DRIVE_STRENGTH_8MA (3<<0)
78 #define SI5351_CLK3_0_DISABLE_STATE 24
79 #define SI5351_CLK7_4_DISABLE_STATE 25
80 #define SI5351_CLK_DISABLE_STATE_MASK 3
81 #define SI5351_CLK_DISABLE_STATE_LOW 0
82 #define SI5351_CLK_DISABLE_STATE_HIGH 1
83 #define SI5351_CLK_DISABLE_STATE_FLOAT 2
84 #define SI5351_CLK_DISABLE_STATE_NEVER 3
86 #define SI5351_PARAMETERS_LENGTH 8
87 #define SI5351_PLLA_PARAMETERS 26
88 #define SI5351_PLLB_PARAMETERS 34
89 #define SI5351_CLK0_PARAMETERS 42
90 #define SI5351_CLK1_PARAMETERS 50
91 #define SI5351_CLK2_PARAMETERS 58
92 #define SI5351_CLK3_PARAMETERS 66
93 #define SI5351_CLK4_PARAMETERS 74
94 #define SI5351_CLK5_PARAMETERS 82
95 #define SI5351_CLK6_PARAMETERS 90
96 #define SI5351_CLK7_PARAMETERS 91
97 #define SI5351_CLK6_7_OUTPUT_DIVIDER 92
98 #define SI5351_OUTPUT_CLK_DIV_MASK (7 << 4)
99 #define SI5351_OUTPUT_CLK6_DIV_MASK (7 << 0)
100 #define SI5351_OUTPUT_CLK_DIV_SHIFT 4
101 #define SI5351_OUTPUT_CLK_DIV6_SHIFT 0
102 #define SI5351_OUTPUT_CLK_DIV_1 0
103 #define SI5351_OUTPUT_CLK_DIV_2 1
104 #define SI5351_OUTPUT_CLK_DIV_4 2
105 #define SI5351_OUTPUT_CLK_DIV_8 3
106 #define SI5351_OUTPUT_CLK_DIV_16 4
107 #define SI5351_OUTPUT_CLK_DIV_32 5
108 #define SI5351_OUTPUT_CLK_DIV_64 6
109 #define SI5351_OUTPUT_CLK_DIV_128 7
110 #define SI5351_OUTPUT_CLK_DIVBY4 (3<<2)
112 #define SI5351_SSC_PARAM0 149
113 #define SI5351_SSC_PARAM1 150
114 #define SI5351_SSC_PARAM2 151
115 #define SI5351_SSC_PARAM3 152
116 #define SI5351_SSC_PARAM4 153
117 #define SI5351_SSC_PARAM5 154
118 #define SI5351_SSC_PARAM6 155
119 #define SI5351_SSC_PARAM7 156
120 #define SI5351_SSC_PARAM8 157
121 #define SI5351_SSC_PARAM9 158
122 #define SI5351_SSC_PARAM10 159
123 #define SI5351_SSC_PARAM11 160
124 #define SI5351_SSC_PARAM12 161
126 #define SI5351_VXCO_PARAMETERS_LOW 162
127 #define SI5351_VXCO_PARAMETERS_MID 163
128 #define SI5351_VXCO_PARAMETERS_HIGH 164
130 #define SI5351_CLK0_PHASE_OFFSET 165
131 #define SI5351_CLK1_PHASE_OFFSET 166
132 #define SI5351_CLK2_PHASE_OFFSET 167
133 #define SI5351_CLK3_PHASE_OFFSET 168
134 #define SI5351_CLK4_PHASE_OFFSET 169
135 #define SI5351_CLK5_PHASE_OFFSET 170
137 #define SI5351_PLL_RESET 177
138 #define SI5351_PLL_RESET_B (1<<7)
139 #define SI5351_PLL_RESET_A (1<<5)
141 #define SI5351_CRYSTAL_LOAD 183
142 #define SI5351_CRYSTAL_LOAD_MASK (3<<6)
143 #define SI5351_CRYSTAL_LOAD_6PF (1<<6)
144 #define SI5351_CRYSTAL_LOAD_8PF (2<<6)
145 #define SI5351_CRYSTAL_LOAD_10PF (3<<6)
147 #define SI5351_FANOUT_ENABLE 187
148 #define SI5351_CLKIN_ENABLE (1<<7)
149 #define SI5351_XTAL_ENABLE (1<<6)
150 #define SI5351_MULTISYNTH_ENABLE (1<<4)
152 /**
153 * enum si5351_variant - SiLabs Si5351 chip variant
154 * @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input)
155 * @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input)
156 * @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input)
157 * @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input)
158 */
164 };
166 #endif