| blob | 27df99c4565aed5036be1fb106ee096a0a1127b5 |
1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2 /*
3 * Copyright (c) 2016 Amlogic, Inc.
4 * Author: Michael Turquette <mturquette@baylibre.com>
5 *
6 * Copyright (c) 2018 Amlogic, inc.
7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
8 * Author: Jian Hu <jian.hu@amlogic.com>
9 *
10 */
11 #ifndef __G12A_H
12 #define __G12A_H
14 /*
15 * Clock controller register offsets
16 *
17 * Register offsets from the data sheet must be multiplied by 4 before
18 * adding them to the base address to get the right value.
19 */
20 #define HHI_MIPI_CNTL0 0x000
21 #define HHI_MIPI_CNTL1 0x004
22 #define HHI_MIPI_CNTL2 0x008
23 #define HHI_MIPI_STS 0x00C
24 #define HHI_GP0_PLL_CNTL0 0x040
25 #define HHI_GP0_PLL_CNTL1 0x044
26 #define HHI_GP0_PLL_CNTL2 0x048
27 #define HHI_GP0_PLL_CNTL3 0x04C
28 #define HHI_GP0_PLL_CNTL4 0x050
29 #define HHI_GP0_PLL_CNTL5 0x054
30 #define HHI_GP0_PLL_CNTL6 0x058
31 #define HHI_GP0_PLL_STS 0x05C
32 #define HHI_GP1_PLL_CNTL0 0x060
33 #define HHI_GP1_PLL_CNTL1 0x064
34 #define HHI_GP1_PLL_CNTL2 0x068
35 #define HHI_GP1_PLL_CNTL3 0x06C
36 #define HHI_GP1_PLL_CNTL4 0x070
37 #define HHI_GP1_PLL_CNTL5 0x074
38 #define HHI_GP1_PLL_CNTL6 0x078
39 #define HHI_GP1_PLL_STS 0x07C
40 #define HHI_PCIE_PLL_CNTL0 0x098
41 #define HHI_PCIE_PLL_CNTL1 0x09C
42 #define HHI_PCIE_PLL_CNTL2 0x0A0
43 #define HHI_PCIE_PLL_CNTL3 0x0A4
44 #define HHI_PCIE_PLL_CNTL4 0x0A8
45 #define HHI_PCIE_PLL_CNTL5 0x0AC
46 #define HHI_PCIE_PLL_STS 0x0B8
47 #define HHI_HIFI_PLL_CNTL0 0x0D8
48 #define HHI_HIFI_PLL_CNTL1 0x0DC
49 #define HHI_HIFI_PLL_CNTL2 0x0E0
50 #define HHI_HIFI_PLL_CNTL3 0x0E4
51 #define HHI_HIFI_PLL_CNTL4 0x0E8
52 #define HHI_HIFI_PLL_CNTL5 0x0EC
53 #define HHI_HIFI_PLL_CNTL6 0x0F0
54 #define HHI_VIID_CLK_DIV 0x128
55 #define HHI_VIID_CLK_CNTL 0x12C
56 #define HHI_GCLK_MPEG0 0x140
57 #define HHI_GCLK_MPEG1 0x144
58 #define HHI_GCLK_MPEG2 0x148
59 #define HHI_GCLK_OTHER 0x150
60 #define HHI_GCLK_OTHER2 0x154
61 #define HHI_SYS_CPU_CLK_CNTL1 0x15c
62 #define HHI_VID_CLK_DIV 0x164
63 #define HHI_MPEG_CLK_CNTL 0x174
64 #define HHI_AUD_CLK_CNTL 0x178
65 #define HHI_VID_CLK_CNTL 0x17c
66 #define HHI_TS_CLK_CNTL 0x190
67 #define HHI_VID_CLK_CNTL2 0x194
68 #define HHI_SYS_CPU_CLK_CNTL0 0x19c
69 #define HHI_VID_PLL_CLK_DIV 0x1A0
70 #define HHI_MALI_CLK_CNTL 0x1b0
71 #define HHI_VPU_CLKC_CNTL 0x1b4
72 #define HHI_VPU_CLK_CNTL 0x1bC
73 #define HHI_ISP_CLK_CNTL 0x1C0
74 #define HHI_NNA_CLK_CNTL 0x1C8
75 #define HHI_HDMI_CLK_CNTL 0x1CC
76 #define HHI_VDEC_CLK_CNTL 0x1E0
77 #define HHI_VDEC2_CLK_CNTL 0x1E4
78 #define HHI_VDEC3_CLK_CNTL 0x1E8
79 #define HHI_VDEC4_CLK_CNTL 0x1EC
80 #define HHI_HDCP22_CLK_CNTL 0x1F0
81 #define HHI_VAPBCLK_CNTL 0x1F4
82 #define HHI_SYS_CPUB_CLK_CNTL1 0x200
83 #define HHI_SYS_CPUB_CLK_CNTL 0x208
84 #define HHI_VPU_CLKB_CNTL 0x20C
85 #define HHI_SYS_CPU_CLK_CNTL2 0x210
86 #define HHI_SYS_CPU_CLK_CNTL3 0x214
87 #define HHI_SYS_CPU_CLK_CNTL4 0x218
88 #define HHI_SYS_CPU_CLK_CNTL5 0x21c
89 #define HHI_SYS_CPU_CLK_CNTL6 0x220
90 #define HHI_GEN_CLK_CNTL 0x228
91 #define HHI_VDIN_MEAS_CLK_CNTL 0x250
92 #define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
93 #define HHI_NAND_CLK_CNTL 0x25C
94 #define HHI_SD_EMMC_CLK_CNTL 0x264
95 #define HHI_MPLL_CNTL0 0x278
96 #define HHI_MPLL_CNTL1 0x27C
97 #define HHI_MPLL_CNTL2 0x280
98 #define HHI_MPLL_CNTL3 0x284
99 #define HHI_MPLL_CNTL4 0x288
100 #define HHI_MPLL_CNTL5 0x28c
101 #define HHI_MPLL_CNTL6 0x290
102 #define HHI_MPLL_CNTL7 0x294
103 #define HHI_MPLL_CNTL8 0x298
104 #define HHI_FIX_PLL_CNTL0 0x2A0
105 #define HHI_FIX_PLL_CNTL1 0x2A4
106 #define HHI_FIX_PLL_CNTL3 0x2AC
107 #define HHI_SYS_PLL_CNTL0 0x2f4
108 #define HHI_SYS_PLL_CNTL1 0x2f8
109 #define HHI_SYS_PLL_CNTL2 0x2fc
110 #define HHI_SYS_PLL_CNTL3 0x300
111 #define HHI_SYS_PLL_CNTL4 0x304
112 #define HHI_SYS_PLL_CNTL5 0x308
113 #define HHI_SYS_PLL_CNTL6 0x30c
114 #define HHI_HDMI_PLL_CNTL0 0x320
115 #define HHI_HDMI_PLL_CNTL1 0x324
116 #define HHI_HDMI_PLL_CNTL2 0x328
117 #define HHI_HDMI_PLL_CNTL3 0x32c
118 #define HHI_HDMI_PLL_CNTL4 0x330
119 #define HHI_HDMI_PLL_CNTL5 0x334
120 #define HHI_HDMI_PLL_CNTL6 0x338
121 #define HHI_SPICC_CLK_CNTL 0x3dc
122 #define HHI_SYS1_PLL_CNTL0 0x380
123 #define HHI_SYS1_PLL_CNTL1 0x384
124 #define HHI_SYS1_PLL_CNTL2 0x388
125 #define HHI_SYS1_PLL_CNTL3 0x38c
126 #define HHI_SYS1_PLL_CNTL4 0x390
127 #define HHI_SYS1_PLL_CNTL5 0x394
128 #define HHI_SYS1_PLL_CNTL6 0x398