drivers/hwtracing/coresight/ultrasoc-smb.h

   1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
   2 /*
   3  * Siemens System Memory Buffer driver.
   4  * Copyright(c) 2022, HiSilicon Limited.
   5  */
   6
   7 #ifndef _ULTRASOC_SMB_H
   8 #define _ULTRASOC_SMB_H
   9
  10 #include <linux/miscdevice.h>
  11 #include <linux/spinlock.h>
  12
  13 /* Offset of SMB global registers */
  14 #define SMB_GLB_CFG_REG         0x00
  15 #define SMB_GLB_EN_REG          0x04
  16 #define SMB_GLB_INT_REG         0x08
  17
  18 /* Offset of SMB logical buffer registers */
  19 #define SMB_LB_CFG_LO_REG       0x40
  20 #define SMB_LB_CFG_HI_REG       0x44
  21 #define SMB_LB_INT_CTRL_REG     0x48
  22 #define SMB_LB_INT_STS_REG      0x4c
  23 #define SMB_LB_RD_ADDR_REG      0x5c
  24 #define SMB_LB_WR_ADDR_REG      0x60
  25 #define SMB_LB_PURGE_REG        0x64
  26
  27 /* Set global config register */
  28 #define SMB_GLB_CFG_BURST_LEN_MSK       GENMASK(11, 4)
  29 #define SMB_GLB_CFG_IDLE_PRD_MSK        GENMASK(15, 12)
  30 #define SMB_GLB_CFG_MEM_WR_MSK          GENMASK(21, 16)
  31 #define SMB_GLB_CFG_MEM_RD_MSK          GENMASK(27, 22)
  32 #define SMB_GLB_CFG_DEFAULT     (FIELD_PREP(SMB_GLB_CFG_BURST_LEN_MSK, 0xf) | \
  33                                  FIELD_PREP(SMB_GLB_CFG_IDLE_PRD_MSK, 0xf) | \
  34                                  FIELD_PREP(SMB_GLB_CFG_MEM_WR_MSK, 0x3) | \
  35                                  FIELD_PREP(SMB_GLB_CFG_MEM_RD_MSK, 0x1b))
  36
  37 #define SMB_GLB_EN_HW_ENABLE    BIT(0)
  38
  39 /* Set global interrupt control register */
  40 #define SMB_GLB_INT_EN          BIT(0)
  41 #define SMB_GLB_INT_PULSE       BIT(1) /* Interrupt type: 1 - Pulse */
  42 #define SMB_GLB_INT_ACT_H       BIT(2) /* Interrupt polarity: 1 - Active high */
  43 #define SMB_GLB_INT_CFG         (SMB_GLB_INT_EN | SMB_GLB_INT_PULSE | \
  44                                  SMB_GLB_INT_ACT_H)
  45
  46 /* Set logical buffer config register lower 32 bits */
  47 #define SMB_LB_CFG_LO_EN                BIT(0)
  48 #define SMB_LB_CFG_LO_SINGLE_END        BIT(1)
  49 #define SMB_LB_CFG_LO_INIT              BIT(8)
  50 #define SMB_LB_CFG_LO_CONT              BIT(11)
  51 #define SMB_LB_CFG_LO_FLOW_MSK          GENMASK(19, 16)
  52 #define SMB_LB_CFG_LO_DEFAULT   (SMB_LB_CFG_LO_EN | SMB_LB_CFG_LO_SINGLE_END | \
  53                                  SMB_LB_CFG_LO_INIT | SMB_LB_CFG_LO_CONT | \
  54                                  FIELD_PREP(SMB_LB_CFG_LO_FLOW_MSK, 0xf))
  55
  56 /* Set logical buffer config register upper 32 bits */
  57 #define SMB_LB_CFG_HI_RANGE_UP_MSK      GENMASK(15, 8)
  58 #define SMB_LB_CFG_HI_DEFAULT   FIELD_PREP(SMB_LB_CFG_HI_RANGE_UP_MSK, 0xff)
  59
  60 /*
  61  * Set logical buffer interrupt control register.
  62  * The register control the validity of both real-time events and
  63  * interrupts. When logical buffer status changes causes to issue
  64  * an interrupt at the same time as it issues a real-time event.
  65  * Real-time events are used in SMB driver, which needs to get the buffer
  66  * status. Interrupts are used in debugger mode.
  67  * SMB_LB_INT_CTRL_BUF_NOTE_MASK control which events flags or interrupts
  68  * are valid.
  69  */
  70 #define SMB_LB_INT_CTRL_EN              BIT(0)
  71 #define SMB_LB_INT_CTRL_BUF_NOTE_MSK    GENMASK(11, 8)
  72 #define SMB_LB_INT_CTRL_CFG     (SMB_LB_INT_CTRL_EN | \
  73                                  FIELD_PREP(SMB_LB_INT_CTRL_BUF_NOTE_MSK, 0xf))
  74
  75 /* Set logical buffer interrupt status register */
  76 #define SMB_LB_INT_STS_NOT_EMPTY_MSK    BIT(0)
  77 #define SMB_LB_INT_STS_BUF_RESET_MSK    GENMASK(3, 0)
  78 #define SMB_LB_INT_STS_RESET    FIELD_PREP(SMB_LB_INT_STS_BUF_RESET_MSK, 0xf)
  79
  80 #define SMB_LB_PURGE_PURGED     BIT(0)
  81
  82 #define SMB_REG_ADDR_RES        0
  83 #define SMB_BUF_ADDR_RES        1
  84 #define SMB_BUF_ADDR_LO_MSK     GENMASK(31, 0)
  85
  86 /**
  87  * struct smb_data_buffer - Details of the buffer used by SMB
  88  * @buf_base:   Memory mapped base address of SMB.
  89  * @buf_hw_base:        SMB buffer start Physical base address, only used 32bits.
  90  * @buf_size:   Size of the buffer.
  91  * @data_size:  Size of the available trace data for SMB.
  92  * @buf_rdptr:  Current read position (index) within the buffer.
  93  */
  94 struct smb_data_buffer {
  95         void *buf_base;
  96         u32 buf_hw_base;
  97         unsigned long buf_size;
  98         unsigned long data_size;
  99         unsigned long buf_rdptr;
 100 };
 101
 102 /**
 103  * struct smb_drv_data - specifics associated to an SMB component
 104  * @base:       Memory mapped base address for SMB component.
 105  * @csdev:      Component vitals needed by the framework.
 106  * @sdb:        Data buffer for SMB.
 107  * @miscdev:    Specifics to handle "/dev/xyz.smb" entry.
 108  * @spinlock:   Control data access to one at a time.
 109  * @reading:    Synchronise user space access to SMB buffer.
 110  * @pid:        Process ID of the process being monitored by the
 111  *              session that is using this component.
 112  */
 113 struct smb_drv_data {
 114         void __iomem *base;
 115         struct coresight_device *csdev;
 116         struct smb_data_buffer sdb;
 117         struct miscdevice miscdev;
 118         spinlock_t spinlock;
 119         bool reading;
 120         pid_t pid;
 121 };
 122
 123 #endif