drivers/iio/accel/bma400.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Register constants and other forward declarations needed by the bma400
   4  * sources.
   5  *
   6  * Copyright 2019 Dan Robertson <dan@dlrobertson.com>
   7  */
   8
   9 #ifndef _BMA400_H_
  10 #define _BMA400_H_
  11
  12 #include <linux/bits.h>
  13 #include <linux/regmap.h>
  14
  15 /*
  16  * Read-Only Registers
  17  */
  18
  19 /* Status and ID registers */
  20 #define BMA400_CHIP_ID_REG          0x00
  21 #define BMA400_ERR_REG              0x02
  22 #define BMA400_STATUS_REG           0x03
  23
  24 /* Acceleration registers */
  25 #define BMA400_X_AXIS_LSB_REG       0x04
  26 #define BMA400_X_AXIS_MSB_REG       0x05
  27 #define BMA400_Y_AXIS_LSB_REG       0x06
  28 #define BMA400_Y_AXIS_MSB_REG       0x07
  29 #define BMA400_Z_AXIS_LSB_REG       0x08
  30 #define BMA400_Z_AXIS_MSB_REG       0x09
  31
  32 /* Sensor time registers */
  33 #define BMA400_SENSOR_TIME0         0x0a
  34 #define BMA400_SENSOR_TIME1         0x0b
  35 #define BMA400_SENSOR_TIME2         0x0c
  36
  37 /* Event and interrupt registers */
  38 #define BMA400_EVENT_REG            0x0d
  39 #define BMA400_INT_STAT0_REG        0x0e
  40 #define BMA400_INT_STAT1_REG        0x0f
  41 #define BMA400_INT_STAT2_REG        0x10
  42 #define BMA400_INT12_MAP_REG        0x23
  43 #define BMA400_INT_ENG_OVRUN_MSK    BIT(4)
  44
  45 /* Temperature register */
  46 #define BMA400_TEMP_DATA_REG        0x11
  47
  48 /* FIFO length and data registers */
  49 #define BMA400_FIFO_LENGTH0_REG     0x12
  50 #define BMA400_FIFO_LENGTH1_REG     0x13
  51 #define BMA400_FIFO_DATA_REG        0x14
  52
  53 /* Step count registers */
  54 #define BMA400_STEP_CNT0_REG        0x15
  55 #define BMA400_STEP_CNT1_REG        0x16
  56 #define BMA400_STEP_CNT3_REG        0x17
  57 #define BMA400_STEP_STAT_REG        0x18
  58 #define BMA400_STEP_INT_MSK         BIT(0)
  59 #define BMA400_STEP_RAW_LEN         0x03
  60 #define BMA400_STEP_STAT_MASK       GENMASK(9, 8)
  61
  62 /*
  63  * Read-write configuration registers
  64  */
  65 #define BMA400_ACC_CONFIG0_REG      0x19
  66 #define BMA400_ACC_CONFIG1_REG      0x1a
  67 #define BMA400_ACC_CONFIG2_REG      0x1b
  68 #define BMA400_CMD_REG              0x7e
  69
  70 /* Interrupt registers */
  71 #define BMA400_INT_CONFIG0_REG      0x1f
  72 #define BMA400_INT_CONFIG1_REG      0x20
  73 #define BMA400_INT1_MAP_REG         0x21
  74 #define BMA400_INT_IO_CTRL_REG      0x24
  75 #define BMA400_INT_DRDY_MSK         BIT(7)
  76
  77 /* Chip ID of BMA 400 devices found in the chip ID register. */
  78 #define BMA400_ID_REG_VAL           0x90
  79
  80 #define BMA400_LP_OSR_SHIFT         5
  81 #define BMA400_NP_OSR_SHIFT         4
  82 #define BMA400_SCALE_SHIFT          6
  83
  84 #define BMA400_TWO_BITS_MASK        GENMASK(1, 0)
  85 #define BMA400_LP_OSR_MASK          GENMASK(6, 5)
  86 #define BMA400_NP_OSR_MASK          GENMASK(5, 4)
  87 #define BMA400_ACC_ODR_MASK         GENMASK(3, 0)
  88 #define BMA400_ACC_SCALE_MASK       GENMASK(7, 6)
  89
  90 #define BMA400_ACC_ODR_MIN_RAW      0x05
  91 #define BMA400_ACC_ODR_LP_RAW       0x06
  92 #define BMA400_ACC_ODR_MAX_RAW      0x0b
  93
  94 #define BMA400_ACC_ODR_MAX_HZ       800
  95 #define BMA400_ACC_ODR_MIN_WHOLE_HZ 25
  96 #define BMA400_ACC_ODR_MIN_HZ       12
  97
  98 /* Generic interrupts register */
  99 #define BMA400_GEN1INT_CONFIG0      0x3f
 100 #define BMA400_GEN2INT_CONFIG0      0x4A
 101 #define BMA400_GEN_CONFIG1_OFF      0x01
 102 #define BMA400_GEN_CONFIG2_OFF      0x02
 103 #define BMA400_GEN_CONFIG3_OFF      0x03
 104 #define BMA400_GEN_CONFIG31_OFF     0x04
 105 #define BMA400_INT_GEN1_MSK         BIT(2)
 106 #define BMA400_INT_GEN2_MSK         BIT(3)
 107 #define BMA400_GEN_HYST_MSK         GENMASK(1, 0)
 108
 109 /* TAP config registers */
 110 #define BMA400_TAP_CONFIG           0x57
 111 #define BMA400_TAP_CONFIG1          0x58
 112 #define BMA400_S_TAP_MSK            BIT(2)
 113 #define BMA400_D_TAP_MSK            BIT(3)
 114 #define BMA400_INT_S_TAP_MSK        BIT(10)
 115 #define BMA400_INT_D_TAP_MSK        BIT(11)
 116 #define BMA400_TAP_SEN_MSK          GENMASK(2, 0)
 117 #define BMA400_TAP_TICSTH_MSK       GENMASK(1, 0)
 118 #define BMA400_TAP_QUIET_MSK        GENMASK(3, 2)
 119 #define BMA400_TAP_QUIETDT_MSK      GENMASK(5, 4)
 120 #define BMA400_TAP_TIM_LIST_LEN     4
 121
 122 /*
 123  * BMA400_SCALE_MIN macro value represents m/s^2 for 1 LSB before
 124  * converting to micro values for +-2g range.
 125  *
 126  * For +-2g - 1 LSB = 0.976562 milli g = 0.009576 m/s^2
 127  * For +-4g - 1 LSB = 1.953125 milli g = 0.019153 m/s^2
 128  * For +-16g - 1 LSB = 7.8125 milli g = 0.076614 m/s^2
 129  *
 130  * The raw value which is used to select the different ranges is determined
 131  * by the first bit set position from the scale value, so BMA400_SCALE_MIN
 132  * should be odd.
 133  *
 134  * Scale values for +-2g, +-4g, +-8g and +-16g are populated into bma400_scales
 135  * array by left shifting BMA400_SCALE_MIN.
 136  * e.g.:
 137  * To select +-2g = 9577 << 0 = raw value to write is 0.
 138  * To select +-8g = 9577 << 2 = raw value to write is 2.
 139  * To select +-16g = 9577 << 3 = raw value to write is 3.
 140  */
 141 #define BMA400_SCALE_MIN            9577
 142 #define BMA400_SCALE_MAX            76617
 143
 144 extern const struct regmap_config bma400_regmap_config;
 145
 146 int bma400_probe(struct device *dev, struct regmap *regmap, int irq,
 147                  const char *name);
 148
 149 #endif