drivers/iio/accel/mma7455_core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * IIO accel core driver for Freescale MMA7455L 3-axis 10-bit accelerometer
   4  * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
   5  *
   6  * UNSUPPORTED hardware features:
   7  *  - 8-bit mode with different scales
   8  *  - INT1/INT2 interrupts
   9  *  - Offset calibration
  10  *  - Events
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/iio/iio.h>
  15 #include <linux/iio/sysfs.h>
  16 #include <linux/iio/buffer.h>
  17 #include <linux/iio/trigger.h>
  18 #include <linux/iio/trigger_consumer.h>
  19 #include <linux/iio/triggered_buffer.h>
  20 #include <linux/module.h>
  21 #include <linux/regmap.h>
  22 #include <linux/types.h>
  23
  24 #include "mma7455.h"
  25
  26 #define MMA7455_REG_XOUTL               0x00
  27 #define MMA7455_REG_XOUTH               0x01
  28 #define MMA7455_REG_YOUTL               0x02
  29 #define MMA7455_REG_YOUTH               0x03
  30 #define MMA7455_REG_ZOUTL               0x04
  31 #define MMA7455_REG_ZOUTH               0x05
  32 #define MMA7455_REG_STATUS              0x09
  33 #define  MMA7455_STATUS_DRDY            BIT(0)
  34 #define MMA7455_REG_WHOAMI              0x0f
  35 #define  MMA7455_WHOAMI_ID              0x55
  36 #define MMA7455_REG_MCTL                0x16
  37 #define  MMA7455_MCTL_MODE_STANDBY      0x00
  38 #define  MMA7455_MCTL_MODE_MEASURE      0x01
  39 #define MMA7455_REG_CTL1                0x18
  40 #define  MMA7455_CTL1_DFBW_MASK         BIT(7)
  41 #define  MMA7455_CTL1_DFBW_125HZ        BIT(7)
  42 #define  MMA7455_CTL1_DFBW_62_5HZ       0
  43 #define MMA7455_REG_TW                  0x1e
  44
  45 /*
  46  * When MMA7455 is used in 10-bit it has a fullscale of -8g
  47  * corresponding to raw value -512. The userspace interface
  48  * uses m/s^2 and we declare micro units.
  49  * So scale factor is given by:
  50  *       g * 8 * 1e6 / 512 = 153228.90625, with g = 9.80665
  51  */
  52 #define MMA7455_10BIT_SCALE     153229
  53
  54 struct mma7455_data {
  55         struct regmap *regmap;
  56         /*
  57          * Used to reorganize data.  Will ensure correct alignment of
  58          * the timestamp if present
  59          */
  60         struct {
  61                 __le16 channels[3];
  62                 aligned_s64 ts;
  63         } scan;
  64 };
  65
  66 static int mma7455_drdy(struct mma7455_data *mma7455)
  67 {
  68         struct device *dev = regmap_get_device(mma7455->regmap);
  69         unsigned int reg;
  70         int tries = 3;
  71         int ret;
  72
  73         while (tries-- > 0) {
  74                 ret = regmap_read(mma7455->regmap, MMA7455_REG_STATUS, &reg);
  75                 if (ret)
  76                         return ret;
  77
  78                 if (reg & MMA7455_STATUS_DRDY)
  79                         return 0;
  80
  81                 msleep(20);
  82         }
  83
  84         dev_warn(dev, "data not ready\n");
  85
  86         return -EIO;
  87 }
  88
  89 static irqreturn_t mma7455_trigger_handler(int irq, void *p)
  90 {
  91         struct iio_poll_func *pf = p;
  92         struct iio_dev *indio_dev = pf->indio_dev;
  93         struct mma7455_data *mma7455 = iio_priv(indio_dev);
  94         int ret;
  95
  96         ret = mma7455_drdy(mma7455);
  97         if (ret)
  98                 goto done;
  99
 100         ret = regmap_bulk_read(mma7455->regmap, MMA7455_REG_XOUTL,
 101                                mma7455->scan.channels,
 102                                sizeof(mma7455->scan.channels));
 103         if (ret)
 104                 goto done;
 105
 106         iio_push_to_buffers_with_timestamp(indio_dev, &mma7455->scan,
 107                                            iio_get_time_ns(indio_dev));
 108
 109 done:
 110         iio_trigger_notify_done(indio_dev->trig);
 111
 112         return IRQ_HANDLED;
 113 }
 114
 115 static int mma7455_read_raw(struct iio_dev *indio_dev,
 116                             struct iio_chan_spec const *chan,
 117                             int *val, int *val2, long mask)
 118 {
 119         struct mma7455_data *mma7455 = iio_priv(indio_dev);
 120         unsigned int reg;
 121         __le16 data;
 122         int ret;
 123
 124         switch (mask) {
 125         case IIO_CHAN_INFO_RAW:
 126                 if (iio_buffer_enabled(indio_dev))
 127                         return -EBUSY;
 128
 129                 ret = mma7455_drdy(mma7455);
 130                 if (ret)
 131                         return ret;
 132
 133                 ret = regmap_bulk_read(mma7455->regmap, chan->address, &data,
 134                                        sizeof(data));
 135                 if (ret)
 136                         return ret;
 137
 138                 *val = sign_extend32(le16_to_cpu(data),
 139                                      chan->scan_type.realbits - 1);
 140
 141                 return IIO_VAL_INT;
 142
 143         case IIO_CHAN_INFO_SCALE:
 144                 *val = 0;
 145                 *val2 = MMA7455_10BIT_SCALE;
 146
 147                 return IIO_VAL_INT_PLUS_MICRO;
 148
 149         case IIO_CHAN_INFO_SAMP_FREQ:
 150                 ret = regmap_read(mma7455->regmap, MMA7455_REG_CTL1, &reg);
 151                 if (ret)
 152                         return ret;
 153
 154                 if (reg & MMA7455_CTL1_DFBW_MASK)
 155                         *val = 250;
 156                 else
 157                         *val = 125;
 158
 159                 return IIO_VAL_INT;
 160         }
 161
 162         return -EINVAL;
 163 }
 164
 165 static int mma7455_write_raw(struct iio_dev *indio_dev,
 166                              struct iio_chan_spec const *chan,
 167                              int val, int val2, long mask)
 168 {
 169         struct mma7455_data *mma7455 = iio_priv(indio_dev);
 170         int i;
 171
 172         switch (mask) {
 173         case IIO_CHAN_INFO_SAMP_FREQ:
 174                 if (val == 250 && val2 == 0)
 175                         i = MMA7455_CTL1_DFBW_125HZ;
 176                 else if (val == 125 && val2 == 0)
 177                         i = MMA7455_CTL1_DFBW_62_5HZ;
 178                 else
 179                         return -EINVAL;
 180
 181                 return regmap_update_bits(mma7455->regmap, MMA7455_REG_CTL1,
 182                                           MMA7455_CTL1_DFBW_MASK, i);
 183
 184         case IIO_CHAN_INFO_SCALE:
 185                 /* In 10-bit mode there is only one scale available */
 186                 if (val == 0 && val2 == MMA7455_10BIT_SCALE)
 187                         return 0;
 188                 break;
 189         }
 190
 191         return -EINVAL;
 192 }
 193
 194 static IIO_CONST_ATTR(sampling_frequency_available, "125 250");
 195
 196 static struct attribute *mma7455_attributes[] = {
 197         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 198         NULL
 199 };
 200
 201 static const struct attribute_group mma7455_group = {
 202         .attrs = mma7455_attributes,
 203 };
 204
 205 static const struct iio_info mma7455_info = {
 206         .attrs = &mma7455_group,
 207         .read_raw = mma7455_read_raw,
 208         .write_raw = mma7455_write_raw,
 209 };
 210
 211 #define MMA7455_CHANNEL(axis, idx) { \
 212         .type = IIO_ACCEL, \
 213         .modified = 1, \
 214         .address = MMA7455_REG_##axis##OUTL,\
 215         .channel2 = IIO_MOD_##axis, \
 216         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
 217         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
 218                                     BIT(IIO_CHAN_INFO_SCALE), \
 219         .scan_index = idx, \
 220         .scan_type = { \
 221                 .sign = 's', \
 222                 .realbits = 10, \
 223                 .storagebits = 16, \
 224                 .endianness = IIO_LE, \
 225         }, \
 226 }
 227
 228 static const struct iio_chan_spec mma7455_channels[] = {
 229         MMA7455_CHANNEL(X, 0),
 230         MMA7455_CHANNEL(Y, 1),
 231         MMA7455_CHANNEL(Z, 2),
 232         IIO_CHAN_SOFT_TIMESTAMP(3),
 233 };
 234
 235 static const unsigned long mma7455_scan_masks[] = {0x7, 0};
 236
 237 const struct regmap_config mma7455_core_regmap = {
 238         .reg_bits = 8,
 239         .val_bits = 8,
 240         .max_register = MMA7455_REG_TW,
 241 };
 242 EXPORT_SYMBOL_NS_GPL(mma7455_core_regmap, "IIO_MMA7455");
 243
 244 int mma7455_core_probe(struct device *dev, struct regmap *regmap,
 245                        const char *name)
 246 {
 247         struct mma7455_data *mma7455;
 248         struct iio_dev *indio_dev;
 249         unsigned int reg;
 250         int ret;
 251
 252         ret = regmap_read(regmap, MMA7455_REG_WHOAMI, &reg);
 253         if (ret) {
 254                 dev_err(dev, "unable to read reg\n");
 255                 return ret;
 256         }
 257
 258         if (reg != MMA7455_WHOAMI_ID) {
 259                 dev_err(dev, "device id mismatch\n");
 260                 return -ENODEV;
 261         }
 262
 263         indio_dev = devm_iio_device_alloc(dev, sizeof(*mma7455));
 264         if (!indio_dev)
 265                 return -ENOMEM;
 266
 267         dev_set_drvdata(dev, indio_dev);
 268         mma7455 = iio_priv(indio_dev);
 269         mma7455->regmap = regmap;
 270
 271         indio_dev->info = &mma7455_info;
 272         indio_dev->name = name;
 273         indio_dev->modes = INDIO_DIRECT_MODE;
 274         indio_dev->channels = mma7455_channels;
 275         indio_dev->num_channels = ARRAY_SIZE(mma7455_channels);
 276         indio_dev->available_scan_masks = mma7455_scan_masks;
 277
 278         regmap_write(mma7455->regmap, MMA7455_REG_MCTL,
 279                      MMA7455_MCTL_MODE_MEASURE);
 280
 281         ret = iio_triggered_buffer_setup(indio_dev, NULL,
 282                                          mma7455_trigger_handler, NULL);
 283         if (ret) {
 284                 dev_err(dev, "unable to setup triggered buffer\n");
 285                 return ret;
 286         }
 287
 288         ret = iio_device_register(indio_dev);
 289         if (ret) {
 290                 dev_err(dev, "unable to register device\n");
 291                 iio_triggered_buffer_cleanup(indio_dev);
 292                 return ret;
 293         }
 294
 295         return 0;
 296 }
 297 EXPORT_SYMBOL_NS_GPL(mma7455_core_probe, "IIO_MMA7455");
 298
 299 void mma7455_core_remove(struct device *dev)
 300 {
 301         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 302         struct mma7455_data *mma7455 = iio_priv(indio_dev);
 303
 304         iio_device_unregister(indio_dev);
 305         iio_triggered_buffer_cleanup(indio_dev);
 306
 307         regmap_write(mma7455->regmap, MMA7455_REG_MCTL,
 308                      MMA7455_MCTL_MODE_STANDBY);
 309 }
 310 EXPORT_SYMBOL_NS_GPL(mma7455_core_remove, "IIO_MMA7455");
 311
 312 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
 313 MODULE_DESCRIPTION("Freescale MMA7455L core accelerometer driver");
 314 MODULE_LICENSE("GPL v2");