1 // SPDX-License-Identifier: GPL-2.0-only
3 * Analog Devices AD9467 SPI ADC driver
5 * Copyright 2012-2020 Analog Devices Inc.
8 #include <linux/bitmap.h>
9 #include <linux/bitops.h>
10 #include <linux/cleanup.h>
11 #include <linux/debugfs.h>
12 #include <linux/module.h>
13 #include <linux/mutex.h>
14 #include <linux/device.h>
15 #include <linux/kernel.h>
16 #include <linux/slab.h>
17 #include <linux/spi/spi.h>
18 #include <linux/seq_file.h>
19 #include <linux/err.h>
20 #include <linux/delay.h>
21 #include <linux/gpio/consumer.h>
25 #include <linux/iio/backend.h>
26 #include <linux/iio/iio.h>
27 #include <linux/iio/sysfs.h>
29 #include <linux/clk.h>
32 * ADI High-Speed ADC common spi interface registers
33 * See Application-Note AN-877:
34 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
37 #define AN877_ADC_REG_CHIP_PORT_CONF 0x00
38 #define AN877_ADC_REG_CHIP_ID 0x01
39 #define AN877_ADC_REG_CHIP_GRADE 0x02
40 #define AN877_ADC_REG_CHAN_INDEX 0x05
41 #define AN877_ADC_REG_TRANSFER 0xFF
42 #define AN877_ADC_REG_MODES 0x08
43 #define AN877_ADC_REG_TEST_IO 0x0D
44 #define AN877_ADC_REG_ADC_INPUT 0x0F
45 #define AN877_ADC_REG_OFFSET 0x10
46 #define AN877_ADC_REG_OUTPUT_MODE 0x14
47 #define AN877_ADC_REG_OUTPUT_ADJUST 0x15
48 #define AN877_ADC_REG_OUTPUT_PHASE 0x16
49 #define AN877_ADC_REG_OUTPUT_DELAY 0x17
50 #define AN877_ADC_REG_VREF 0x18
51 #define AN877_ADC_REG_ANALOG_INPUT 0x2C
53 /* AN877_ADC_REG_TEST_IO */
54 #define AN877_ADC_TESTMODE_OFF 0x0
55 #define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1
56 #define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2
57 #define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3
58 #define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4
59 #define AN877_ADC_TESTMODE_PN23_SEQ 0x5
60 #define AN877_ADC_TESTMODE_PN9_SEQ 0x6
61 #define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7
62 #define AN877_ADC_TESTMODE_USER 0x8
63 #define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9
64 #define AN877_ADC_TESTMODE_SYNC 0xA
65 #define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB
66 #define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC
67 #define AN877_ADC_TESTMODE_RAMP 0xF
69 /* AN877_ADC_REG_TRANSFER */
70 #define AN877_ADC_TRANSFER_SYNC 0x1
72 /* AN877_ADC_REG_OUTPUT_MODE */
73 #define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0
74 #define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1
75 #define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2
77 /* AN877_ADC_REG_OUTPUT_PHASE */
78 #define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20
79 #define AN877_ADC_INVERT_DCO_CLK 0x80
81 /* AN877_ADC_REG_OUTPUT_DELAY */
82 #define AN877_ADC_DCO_DELAY_ENABLE 0x80
85 * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC
88 #define CHIPID_AD9265 0x64
89 #define AD9265_DEF_OUTPUT_MODE 0x40
90 #define AD9265_REG_VREF_MASK 0xC0
93 * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC
96 #define CHIPID_AD9434 0x6A
97 #define AD9434_DEF_OUTPUT_MODE 0x00
98 #define AD9434_REG_VREF_MASK 0xC0
101 * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC
104 #define CHIPID_AD9467 0x50
105 #define AD9467_DEF_OUTPUT_MODE 0x08
106 #define AD9467_REG_VREF_MASK 0x0F
109 * Analog Devices AD9643 14-Bit, 170/210/250 MSPS ADC
112 #define CHIPID_AD9643 0x82
113 #define AD9643_REG_VREF_MASK 0x1F
116 * Analog Devices AD9652 16-bit 310 MSPS ADC
119 #define CHIPID_AD9652 0xC1
120 #define AD9652_REG_VREF_MASK 0xC0
123 * Analog Devices AD9649 14-bit 20/40/65/80 MSPS ADC
126 #define CHIPID_AD9649 0x6F
127 #define AD9649_TEST_POINTS 8
129 #define AD9647_MAX_TEST_POINTS 32
130 #define AD9467_CAN_INVERT(st) \
131 (!(st)->info->has_dco || (st)->info->has_dco_invert)
133 struct ad9467_chip_info
{
136 const struct iio_chan_spec
*channels
;
137 unsigned int num_channels
;
138 const unsigned int (*scale_table
)[2];
140 unsigned long test_mask
;
141 unsigned int test_mask_len
;
142 unsigned long max_rate
;
143 unsigned int default_output_mode
;
144 unsigned int vref_mask
;
145 unsigned int num_lanes
;
147 unsigned int test_points
;
148 /* data clock output */
153 struct ad9467_chan_test_mode
{
154 struct ad9467_state
*st
;
159 struct ad9467_state
{
160 const struct ad9467_chip_info
*info
;
161 struct iio_backend
*back
;
162 struct spi_device
*spi
;
164 /* used for debugfs */
165 struct ad9467_chan_test_mode
*chan_test
;
166 unsigned int output_mode
;
167 unsigned int (*scales
)[2];
169 * Times 2 because we may also invert the signal polarity and run the
170 * calibration again. For some reference on the test points (ad9265) see:
171 * https://www.analog.com/media/en/technical-documentation/data-sheets/ad9265.pdf
172 * at page 38 for the dco output delay. On devices as ad9467, the
173 * calibration is done at the backend level. For the ADI axi-adc:
174 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
175 * at the io delay control section.
177 DECLARE_BITMAP(calib_map
, AD9647_MAX_TEST_POINTS
* 2);
178 /* number of bits of the map */
179 unsigned int calib_map_size
;
180 struct gpio_desc
*pwrdown_gpio
;
181 /* ensure consistent state obtained on multiple related accesses */
183 u8 buf
[3] __aligned(IIO_DMA_MINALIGN
);
186 static int ad9467_spi_read(struct ad9467_state
*st
, unsigned int reg
)
188 unsigned char tbuf
[2], rbuf
[1];
191 tbuf
[0] = 0x80 | (reg
>> 8);
192 tbuf
[1] = reg
& 0xFF;
194 ret
= spi_write_then_read(st
->spi
,
195 tbuf
, ARRAY_SIZE(tbuf
),
196 rbuf
, ARRAY_SIZE(rbuf
));
204 static int ad9467_spi_write(struct ad9467_state
*st
, unsigned int reg
,
207 st
->buf
[0] = reg
>> 8;
208 st
->buf
[1] = reg
& 0xFF;
211 return spi_write(st
->spi
, st
->buf
, ARRAY_SIZE(st
->buf
));
214 static int ad9467_reg_access(struct iio_dev
*indio_dev
, unsigned int reg
,
215 unsigned int writeval
, unsigned int *readval
)
217 struct ad9467_state
*st
= iio_priv(indio_dev
);
221 guard(mutex
)(&st
->lock
);
222 ret
= ad9467_spi_write(st
, reg
, writeval
);
225 return ad9467_spi_write(st
, AN877_ADC_REG_TRANSFER
,
226 AN877_ADC_TRANSFER_SYNC
);
229 ret
= ad9467_spi_read(st
, reg
);
237 static const unsigned int ad9265_scale_table
[][2] = {
238 {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0},
241 static const unsigned int ad9434_scale_table
[][2] = {
242 {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00},
243 {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05},
244 {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A},
245 {1200, 0x0B}, {1180, 0x0C},
248 static const unsigned int ad9467_scale_table
[][2] = {
249 {2000, 0}, {2100, 6}, {2200, 7},
250 {2300, 8}, {2400, 9}, {2500, 10},
253 static const unsigned int ad9643_scale_table
[][2] = {
254 {2087, 0x0F}, {2065, 0x0E}, {2042, 0x0D}, {2020, 0x0C}, {1997, 0x0B},
255 {1975, 0x0A}, {1952, 0x09}, {1930, 0x08}, {1907, 0x07}, {1885, 0x06},
256 {1862, 0x05}, {1840, 0x04}, {1817, 0x03}, {1795, 0x02}, {1772, 0x01},
257 {1750, 0x00}, {1727, 0x1F}, {1704, 0x1E}, {1681, 0x1D}, {1658, 0x1C},
258 {1635, 0x1B}, {1612, 0x1A}, {1589, 0x19}, {1567, 0x18}, {1544, 0x17},
259 {1521, 0x16}, {1498, 0x15}, {1475, 0x14}, {1452, 0x13}, {1429, 0x12},
260 {1406, 0x11}, {1383, 0x10},
263 static const unsigned int ad9649_scale_table
[][2] = {
267 static const unsigned int ad9652_scale_table
[][2] = {
268 {1250, 0}, {1125, 1}, {1200, 2}, {1250, 3}, {1000, 5},
271 static void __ad9467_get_scale(struct ad9467_state
*st
, int index
,
272 unsigned int *val
, unsigned int *val2
)
274 const struct ad9467_chip_info
*info
= st
->info
;
275 const struct iio_chan_spec
*chan
= &info
->channels
[0];
278 tmp
= (info
->scale_table
[index
][0] * 1000000ULL) >>
279 chan
->scan_type
.realbits
;
280 *val
= tmp
/ 1000000;
281 *val2
= tmp
% 1000000;
284 #define AD9467_CHAN(_chan, avai_mask, _si, _bits, _sign) \
286 .type = IIO_VOLTAGE, \
289 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
290 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
291 .info_mask_shared_by_type_available = avai_mask, \
300 static const struct iio_chan_spec ad9434_channels
[] = {
301 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE
), 0, 12, 's'),
304 static const struct iio_chan_spec ad9467_channels
[] = {
305 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE
), 0, 16, 's'),
308 static const struct iio_chan_spec ad9643_channels
[] = {
309 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE
), 0, 14, 's'),
310 AD9467_CHAN(1, BIT(IIO_CHAN_INFO_SCALE
), 1, 14, 's'),
313 static const struct iio_chan_spec ad9649_channels
[] = {
314 AD9467_CHAN(0, 0, 0, 14, 's'),
317 static const struct iio_chan_spec ad9652_channels
[] = {
318 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE
), 0, 16, 's'),
319 AD9467_CHAN(1, BIT(IIO_CHAN_INFO_SCALE
), 1, 16, 's'),
322 static const char * const ad9467_test_modes
[] = {
323 [AN877_ADC_TESTMODE_OFF
] = "off",
324 [AN877_ADC_TESTMODE_MIDSCALE_SHORT
] = "midscale_short",
325 [AN877_ADC_TESTMODE_POS_FULLSCALE
] = "pos_fullscale",
326 [AN877_ADC_TESTMODE_NEG_FULLSCALE
] = "neg_fullscale",
327 [AN877_ADC_TESTMODE_ALT_CHECKERBOARD
] = "checkerboard",
328 [AN877_ADC_TESTMODE_PN23_SEQ
] = "prbs23",
329 [AN877_ADC_TESTMODE_PN9_SEQ
] = "prbs9",
330 [AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE
] = "one_zero_toggle",
331 [AN877_ADC_TESTMODE_USER
] = "user",
332 [AN877_ADC_TESTMODE_BIT_TOGGLE
] = "bit_toggle",
333 [AN877_ADC_TESTMODE_SYNC
] = "sync",
334 [AN877_ADC_TESTMODE_ONE_BIT_HIGH
] = "one_bit_high",
335 [AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY
] = "mixed_bit_frequency",
336 [AN877_ADC_TESTMODE_RAMP
] = "ramp",
339 static const struct ad9467_chip_info ad9467_chip_tbl
= {
342 .max_rate
= 250000000UL,
343 .scale_table
= ad9467_scale_table
,
344 .num_scales
= ARRAY_SIZE(ad9467_scale_table
),
345 .channels
= ad9467_channels
,
346 .num_channels
= ARRAY_SIZE(ad9467_channels
),
347 .test_points
= AD9647_MAX_TEST_POINTS
,
348 .test_mask
= GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE
,
349 AN877_ADC_TESTMODE_OFF
),
350 .test_mask_len
= AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE
+ 1,
351 .default_output_mode
= AD9467_DEF_OUTPUT_MODE
,
352 .vref_mask
= AD9467_REG_VREF_MASK
,
356 static const struct ad9467_chip_info ad9434_chip_tbl
= {
359 .max_rate
= 500000000UL,
360 .scale_table
= ad9434_scale_table
,
361 .num_scales
= ARRAY_SIZE(ad9434_scale_table
),
362 .channels
= ad9434_channels
,
363 .num_channels
= ARRAY_SIZE(ad9434_channels
),
364 .test_points
= AD9647_MAX_TEST_POINTS
,
365 .test_mask
= GENMASK(AN877_ADC_TESTMODE_USER
, AN877_ADC_TESTMODE_OFF
),
366 .test_mask_len
= AN877_ADC_TESTMODE_USER
+ 1,
367 .default_output_mode
= AD9434_DEF_OUTPUT_MODE
,
368 .vref_mask
= AD9434_REG_VREF_MASK
,
372 static const struct ad9467_chip_info ad9265_chip_tbl
= {
375 .max_rate
= 125000000UL,
376 .scale_table
= ad9265_scale_table
,
377 .num_scales
= ARRAY_SIZE(ad9265_scale_table
),
378 .channels
= ad9467_channels
,
379 .num_channels
= ARRAY_SIZE(ad9467_channels
),
380 .test_points
= AD9647_MAX_TEST_POINTS
,
381 .test_mask
= GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE
,
382 AN877_ADC_TESTMODE_OFF
),
383 .test_mask_len
= AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE
+ 1,
384 .default_output_mode
= AD9265_DEF_OUTPUT_MODE
,
385 .vref_mask
= AD9265_REG_VREF_MASK
,
387 .has_dco_invert
= true,
390 static const struct ad9467_chip_info ad9643_chip_tbl
= {
393 .max_rate
= 250000000UL,
394 .scale_table
= ad9643_scale_table
,
395 .num_scales
= ARRAY_SIZE(ad9643_scale_table
),
396 .channels
= ad9643_channels
,
397 .num_channels
= ARRAY_SIZE(ad9643_channels
),
398 .test_points
= AD9647_MAX_TEST_POINTS
,
399 .test_mask
= BIT(AN877_ADC_TESTMODE_RAMP
) |
400 GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY
, AN877_ADC_TESTMODE_OFF
),
401 .test_mask_len
= AN877_ADC_TESTMODE_RAMP
+ 1,
402 .vref_mask
= AD9643_REG_VREF_MASK
,
404 .has_dco_invert
= true,
405 .dco_en
= AN877_ADC_DCO_DELAY_ENABLE
,
408 static const struct ad9467_chip_info ad9649_chip_tbl
= {
411 .max_rate
= 80000000UL,
412 .scale_table
= ad9649_scale_table
,
413 .num_scales
= ARRAY_SIZE(ad9649_scale_table
),
414 .channels
= ad9649_channels
,
415 .num_channels
= ARRAY_SIZE(ad9649_channels
),
416 .test_points
= AD9649_TEST_POINTS
,
417 .test_mask
= GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY
,
418 AN877_ADC_TESTMODE_OFF
),
419 .test_mask_len
= AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY
+ 1,
421 .has_dco_invert
= true,
422 .dco_en
= AN877_ADC_DCO_DELAY_ENABLE
,
425 static const struct ad9467_chip_info ad9652_chip_tbl
= {
428 .max_rate
= 310000000UL,
429 .scale_table
= ad9652_scale_table
,
430 .num_scales
= ARRAY_SIZE(ad9652_scale_table
),
431 .channels
= ad9652_channels
,
432 .num_channels
= ARRAY_SIZE(ad9652_channels
),
433 .test_points
= AD9647_MAX_TEST_POINTS
,
434 .test_mask
= GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE
,
435 AN877_ADC_TESTMODE_OFF
),
436 .test_mask_len
= AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE
+ 1,
437 .vref_mask
= AD9652_REG_VREF_MASK
,
441 static int ad9467_get_scale(struct ad9467_state
*st
, int *val
, int *val2
)
443 const struct ad9467_chip_info
*info
= st
->info
;
444 unsigned int vref_val
;
448 /* nothing to read if we only have one possible scale */
449 if (info
->num_scales
== 1)
452 ret
= ad9467_spi_read(st
, AN877_ADC_REG_VREF
);
456 vref_val
= ret
& info
->vref_mask
;
458 for (i
= 0; i
< info
->num_scales
; i
++) {
459 if (vref_val
== info
->scale_table
[i
][1])
463 if (i
== info
->num_scales
)
467 __ad9467_get_scale(st
, i
, val
, val2
);
469 return IIO_VAL_INT_PLUS_MICRO
;
472 static int ad9467_set_scale(struct ad9467_state
*st
, int val
, int val2
)
474 const struct ad9467_chip_info
*info
= st
->info
;
475 unsigned int scale_val
[2];
481 if (info
->num_scales
== 1)
484 for (i
= 0; i
< info
->num_scales
; i
++) {
485 __ad9467_get_scale(st
, i
, &scale_val
[0], &scale_val
[1]);
486 if (scale_val
[0] != val
|| scale_val
[1] != val2
)
489 guard(mutex
)(&st
->lock
);
490 ret
= ad9467_spi_write(st
, AN877_ADC_REG_VREF
,
491 info
->scale_table
[i
][1]);
495 return ad9467_spi_write(st
, AN877_ADC_REG_TRANSFER
,
496 AN877_ADC_TRANSFER_SYNC
);
502 static int ad9467_outputmode_set(struct ad9467_state
*st
, unsigned int mode
)
506 ret
= ad9467_spi_write(st
, AN877_ADC_REG_OUTPUT_MODE
, mode
);
510 return ad9467_spi_write(st
, AN877_ADC_REG_TRANSFER
,
511 AN877_ADC_TRANSFER_SYNC
);
514 static int ad9467_testmode_set(struct ad9467_state
*st
, unsigned int chan
,
515 unsigned int test_mode
)
519 if (st
->info
->num_channels
> 1) {
520 /* so that the test mode is only applied to one channel */
521 ret
= ad9467_spi_write(st
, AN877_ADC_REG_CHAN_INDEX
, BIT(chan
));
526 ret
= ad9467_spi_write(st
, AN877_ADC_REG_TEST_IO
, test_mode
);
530 if (st
->info
->num_channels
> 1) {
531 /* go to default state where all channels get write commands */
532 ret
= ad9467_spi_write(st
, AN877_ADC_REG_CHAN_INDEX
,
533 GENMASK(st
->info
->num_channels
- 1, 0));
538 return ad9467_spi_write(st
, AN877_ADC_REG_TRANSFER
,
539 AN877_ADC_TRANSFER_SYNC
);
542 static int ad9467_backend_testmode_on(struct ad9467_state
*st
,
544 enum iio_backend_test_pattern pattern
)
546 struct iio_backend_data_fmt data
= {
551 ret
= iio_backend_data_format_set(st
->back
, chan
, &data
);
555 ret
= iio_backend_test_pattern_set(st
->back
, chan
, pattern
);
559 return iio_backend_chan_enable(st
->back
, chan
);
562 static int ad9467_backend_testmode_off(struct ad9467_state
*st
,
565 struct iio_backend_data_fmt data
= {
571 ret
= iio_backend_chan_disable(st
->back
, chan
);
575 ret
= iio_backend_test_pattern_set(st
->back
, chan
,
576 IIO_BACKEND_NO_TEST_PATTERN
);
580 return iio_backend_data_format_set(st
->back
, chan
, &data
);
583 static int ad9647_calibrate_prepare(struct ad9467_state
*st
)
588 ret
= ad9467_outputmode_set(st
, st
->info
->default_output_mode
);
592 for (c
= 0; c
< st
->info
->num_channels
; c
++) {
593 ret
= ad9467_testmode_set(st
, c
, AN877_ADC_TESTMODE_PN9_SEQ
);
597 ret
= ad9467_backend_testmode_on(st
, c
,
598 IIO_BACKEND_ADI_PRBS_9A
);
606 static int ad9647_calibrate_polarity_set(struct ad9467_state
*st
,
609 enum iio_backend_sample_trigger trigger
;
611 if (st
->info
->has_dco
) {
612 unsigned int phase
= AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN
;
615 phase
|= AN877_ADC_INVERT_DCO_CLK
;
617 return ad9467_spi_write(st
, AN877_ADC_REG_OUTPUT_PHASE
,
622 trigger
= IIO_BACKEND_SAMPLE_TRIGGER_EDGE_FALLING
;
624 trigger
= IIO_BACKEND_SAMPLE_TRIGGER_EDGE_RISING
;
626 return iio_backend_data_sample_trigger(st
->back
, trigger
);
630 * The idea is pretty simple. Find the max number of successful points in a row
631 * and get the one in the middle.
633 static unsigned int ad9467_find_optimal_point(const unsigned long *calib_map
,
638 unsigned int bit
= start
, end
, start_cnt
, cnt
= 0;
640 for_each_clear_bitrange_from(bit
, end
, calib_map
, nbits
+ start
) {
641 if (end
- bit
> cnt
) {
648 *val
= start_cnt
+ cnt
/ 2;
653 static int ad9467_calibrate_apply(struct ad9467_state
*st
, unsigned int val
)
658 if (st
->info
->has_dco
) {
659 ret
= ad9467_spi_write(st
, AN877_ADC_REG_OUTPUT_DELAY
,
660 val
| st
->info
->dco_en
);
664 return ad9467_spi_write(st
, AN877_ADC_REG_TRANSFER
,
665 AN877_ADC_TRANSFER_SYNC
);
668 for (lane
= 0; lane
< st
->info
->num_lanes
; lane
++) {
669 ret
= iio_backend_iodelay_set(st
->back
, lane
, val
);
677 static int ad9647_calibrate_stop(struct ad9467_state
*st
)
679 unsigned int c
, mode
;
682 for (c
= 0; c
< st
->info
->num_channels
; c
++) {
683 ret
= ad9467_backend_testmode_off(st
, c
);
687 ret
= ad9467_testmode_set(st
, c
, AN877_ADC_TESTMODE_OFF
);
692 mode
= st
->info
->default_output_mode
| AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT
;
693 return ad9467_outputmode_set(st
, mode
);
696 static int ad9467_calibrate(struct ad9467_state
*st
)
698 unsigned int point
, val
, inv_val
, cnt
, inv_cnt
= 0, c
;
700 * Half of the bitmap is for the inverted signal. The number of test
701 * points is the same though...
703 unsigned int test_points
= st
->info
->test_points
;
704 unsigned long sample_rate
= clk_get_rate(st
->clk
);
705 struct device
*dev
= &st
->spi
->dev
;
706 bool invert
= false, stat
;
709 /* all points invalid */
710 bitmap_fill(st
->calib_map
, st
->calib_map_size
);
712 ret
= ad9647_calibrate_prepare(st
);
716 ret
= ad9647_calibrate_polarity_set(st
, invert
);
720 for (point
= 0; point
< st
->info
->test_points
; point
++) {
721 ret
= ad9467_calibrate_apply(st
, point
);
725 for (c
= 0; c
< st
->info
->num_channels
; c
++) {
726 ret
= iio_backend_chan_status(st
->back
, c
, &stat
);
731 * A point is considered valid if all channels report no
732 * error. If one reports an error, then we consider the
733 * point as invalid and we can break the loop right away.
736 dev_dbg(dev
, "Invalid point(%u, inv:%u) for CH:%u\n",
741 if (c
== st
->info
->num_channels
- 1)
742 __clear_bit(point
+ invert
* test_points
,
748 cnt
= ad9467_find_optimal_point(st
->calib_map
, 0, test_points
,
751 * We're happy if we find, at least, three good test points in
755 if (AD9467_CAN_INVERT(st
)) {
764 inv_cnt
= ad9467_find_optimal_point(st
->calib_map
, test_points
,
765 test_points
, &inv_val
);
766 if (!inv_cnt
&& !cnt
)
771 ret
= ad9647_calibrate_polarity_set(st
, false);
776 * polarity inverted is the last test to run. Hence, there's no
777 * need to re-do any configuration. We just need to "normalize"
778 * the selected value.
780 val
= inv_val
- test_points
;
783 if (st
->info
->has_dco
)
784 dev_dbg(dev
, "%sDCO 0x%X CLK %lu Hz\n", inv_cnt
>= cnt
? "INVERT " : "",
787 dev_dbg(dev
, "%sIDELAY 0x%x\n", inv_cnt
>= cnt
? "INVERT " : "",
790 ret
= ad9467_calibrate_apply(st
, val
);
794 /* finally apply the optimal value */
795 return ad9647_calibrate_stop(st
);
798 static int ad9467_read_raw(struct iio_dev
*indio_dev
,
799 struct iio_chan_spec
const *chan
,
800 int *val
, int *val2
, long m
)
802 struct ad9467_state
*st
= iio_priv(indio_dev
);
805 case IIO_CHAN_INFO_SCALE
:
806 return ad9467_get_scale(st
, val
, val2
);
807 case IIO_CHAN_INFO_SAMP_FREQ
:
808 *val
= clk_get_rate(st
->clk
);
816 static int ad9467_write_raw(struct iio_dev
*indio_dev
,
817 struct iio_chan_spec
const *chan
,
818 int val
, int val2
, long mask
)
820 struct ad9467_state
*st
= iio_priv(indio_dev
);
821 const struct ad9467_chip_info
*info
= st
->info
;
822 unsigned long sample_rate
;
827 case IIO_CHAN_INFO_SCALE
:
828 return ad9467_set_scale(st
, val
, val2
);
829 case IIO_CHAN_INFO_SAMP_FREQ
:
830 r_clk
= clk_round_rate(st
->clk
, val
);
831 if (r_clk
< 0 || r_clk
> info
->max_rate
) {
832 dev_warn(&st
->spi
->dev
,
833 "Error setting ADC sample rate %ld", r_clk
);
837 sample_rate
= clk_get_rate(st
->clk
);
839 * clk_set_rate() would also do this but since we would still
840 * need it for avoiding an unnecessary calibration, do it now.
842 if (sample_rate
== r_clk
)
845 iio_device_claim_direct_scoped(return -EBUSY
, indio_dev
) {
846 ret
= clk_set_rate(st
->clk
, r_clk
);
850 guard(mutex
)(&st
->lock
);
851 ret
= ad9467_calibrate(st
);
859 static int ad9467_read_avail(struct iio_dev
*indio_dev
,
860 struct iio_chan_spec
const *chan
,
861 const int **vals
, int *type
, int *length
,
864 struct ad9467_state
*st
= iio_priv(indio_dev
);
865 const struct ad9467_chip_info
*info
= st
->info
;
868 case IIO_CHAN_INFO_SCALE
:
869 *vals
= (const int *)st
->scales
;
870 *type
= IIO_VAL_INT_PLUS_MICRO
;
871 /* Values are stored in a 2D matrix */
872 *length
= info
->num_scales
* 2;
873 return IIO_AVAIL_LIST
;
879 static int ad9467_update_scan_mode(struct iio_dev
*indio_dev
,
880 const unsigned long *scan_mask
)
882 struct ad9467_state
*st
= iio_priv(indio_dev
);
886 for (c
= 0; c
< st
->info
->num_channels
; c
++) {
887 if (test_bit(c
, scan_mask
))
888 ret
= iio_backend_chan_enable(st
->back
, c
);
890 ret
= iio_backend_chan_disable(st
->back
, c
);
898 static struct iio_info ad9467_info
= {
899 .read_raw
= ad9467_read_raw
,
900 .write_raw
= ad9467_write_raw
,
901 .update_scan_mode
= ad9467_update_scan_mode
,
902 .debugfs_reg_access
= ad9467_reg_access
,
903 .read_avail
= ad9467_read_avail
,
906 static int ad9467_scale_fill(struct ad9467_state
*st
)
908 const struct ad9467_chip_info
*info
= st
->info
;
909 unsigned int i
, val1
, val2
;
911 st
->scales
= devm_kmalloc_array(&st
->spi
->dev
, info
->num_scales
,
912 sizeof(*st
->scales
), GFP_KERNEL
);
916 for (i
= 0; i
< info
->num_scales
; i
++) {
917 __ad9467_get_scale(st
, i
, &val1
, &val2
);
918 st
->scales
[i
][0] = val1
;
919 st
->scales
[i
][1] = val2
;
925 static int ad9467_reset(struct device
*dev
)
927 struct gpio_desc
*gpio
;
929 gpio
= devm_gpiod_get_optional(dev
, "reset", GPIOD_OUT_HIGH
);
930 if (IS_ERR_OR_NULL(gpio
))
931 return PTR_ERR_OR_ZERO(gpio
);
934 gpiod_set_value_cansleep(gpio
, 0);
935 fsleep(10 * USEC_PER_MSEC
);
940 static int ad9467_iio_backend_get(struct ad9467_state
*st
)
942 struct device
*dev
= &st
->spi
->dev
;
943 struct device_node
*__back
;
945 st
->back
= devm_iio_backend_get(dev
, NULL
);
946 if (!IS_ERR(st
->back
))
948 /* If not found, don't error out as we might have legacy DT property */
949 if (PTR_ERR(st
->back
) != -ENOENT
)
950 return PTR_ERR(st
->back
);
953 * if we don't get the backend using the normal API's, use the legacy
954 * 'adi,adc-dev' property. So we get all nodes with that property, and
955 * look for the one pointing at us. Then we directly lookup that fwnode
956 * on the backend list of registered devices. This is done so we don't
957 * make io-backends mandatory which would break DT ABI.
959 for_each_node_with_property(__back
, "adi,adc-dev") {
960 struct device_node
*__me
;
962 __me
= of_parse_phandle(__back
, "adi,adc-dev", 0);
966 if (!device_match_of_node(dev
, __me
)) {
972 st
->back
= __devm_iio_backend_get_from_fwnode_lookup(dev
,
973 of_fwnode_handle(__back
));
975 return PTR_ERR_OR_ZERO(st
->back
);
981 static int ad9467_test_mode_available_show(struct seq_file
*s
, void *ignored
)
983 struct ad9467_state
*st
= s
->private;
986 for_each_set_bit(bit
, &st
->info
->test_mask
, st
->info
->test_mask_len
)
987 seq_printf(s
, "%s\n", ad9467_test_modes
[bit
]);
991 DEFINE_SHOW_ATTRIBUTE(ad9467_test_mode_available
);
993 static ssize_t
ad9467_chan_test_mode_read(struct file
*file
,
994 char __user
*userbuf
, size_t count
,
997 struct ad9467_chan_test_mode
*chan
= file
->private_data
;
998 struct ad9467_state
*st
= chan
->st
;
1003 if (chan
->mode
== AN877_ADC_TESTMODE_PN9_SEQ
||
1004 chan
->mode
== AN877_ADC_TESTMODE_PN23_SEQ
) {
1005 len
= scnprintf(buf
, sizeof(buf
), "Running \"%s\" Test:\n\t",
1006 ad9467_test_modes
[chan
->mode
]);
1008 ret
= iio_backend_debugfs_print_chan_status(st
->back
, chan
->idx
,
1014 } else if (chan
->mode
== AN877_ADC_TESTMODE_OFF
) {
1015 len
= scnprintf(buf
, sizeof(buf
), "No test Running...\n");
1017 len
= scnprintf(buf
, sizeof(buf
), "Running \"%s\" Test on CH:%u\n",
1018 ad9467_test_modes
[chan
->mode
], chan
->idx
);
1021 return simple_read_from_buffer(userbuf
, count
, ppos
, buf
, len
);
1024 static ssize_t
ad9467_chan_test_mode_write(struct file
*file
,
1025 const char __user
*userbuf
,
1026 size_t count
, loff_t
*ppos
)
1028 struct ad9467_chan_test_mode
*chan
= file
->private_data
;
1029 struct ad9467_state
*st
= chan
->st
;
1030 char test_mode
[32] = {0};
1034 ret
= simple_write_to_buffer(test_mode
, sizeof(test_mode
) - 1, ppos
,
1039 for_each_set_bit(mode
, &st
->info
->test_mask
, st
->info
->test_mask_len
) {
1040 if (sysfs_streq(test_mode
, ad9467_test_modes
[mode
]))
1044 if (mode
== st
->info
->test_mask_len
)
1047 guard(mutex
)(&st
->lock
);
1049 if (mode
== AN877_ADC_TESTMODE_OFF
) {
1050 unsigned int out_mode
;
1052 if (chan
->mode
== AN877_ADC_TESTMODE_PN9_SEQ
||
1053 chan
->mode
== AN877_ADC_TESTMODE_PN23_SEQ
) {
1054 ret
= ad9467_backend_testmode_off(st
, chan
->idx
);
1059 ret
= ad9467_testmode_set(st
, chan
->idx
, mode
);
1063 out_mode
= st
->info
->default_output_mode
| AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT
;
1064 ret
= ad9467_outputmode_set(st
, out_mode
);
1068 ret
= ad9467_outputmode_set(st
, st
->info
->default_output_mode
);
1072 ret
= ad9467_testmode_set(st
, chan
->idx
, mode
);
1076 /* some patterns have a backend matching monitoring block */
1077 if (mode
== AN877_ADC_TESTMODE_PN9_SEQ
) {
1078 ret
= ad9467_backend_testmode_on(st
, chan
->idx
,
1079 IIO_BACKEND_ADI_PRBS_9A
);
1082 } else if (mode
== AN877_ADC_TESTMODE_PN23_SEQ
) {
1083 ret
= ad9467_backend_testmode_on(st
, chan
->idx
,
1084 IIO_BACKEND_ADI_PRBS_23A
);
1095 static const struct file_operations ad9467_chan_test_mode_fops
= {
1096 .open
= simple_open
,
1097 .read
= ad9467_chan_test_mode_read
,
1098 .write
= ad9467_chan_test_mode_write
,
1099 .llseek
= default_llseek
,
1100 .owner
= THIS_MODULE
,
1103 static ssize_t
ad9467_dump_calib_table(struct file
*file
,
1104 char __user
*userbuf
,
1105 size_t count
, loff_t
*ppos
)
1107 struct ad9467_state
*st
= file
->private_data
;
1109 /* +2 for the newline and +1 for the string termination */
1110 unsigned char map
[AD9647_MAX_TEST_POINTS
* 2 + 3];
1113 guard(mutex
)(&st
->lock
);
1117 for (bit
= 0; bit
< st
->calib_map_size
; bit
++) {
1118 if (AD9467_CAN_INVERT(st
) && bit
== st
->calib_map_size
/ 2)
1119 len
+= scnprintf(map
+ len
, sizeof(map
) - len
, "\n");
1121 len
+= scnprintf(map
+ len
, sizeof(map
) - len
, "%c",
1122 test_bit(bit
, st
->calib_map
) ? 'x' : 'o');
1125 len
+= scnprintf(map
+ len
, sizeof(map
) - len
, "\n");
1127 return simple_read_from_buffer(userbuf
, count
, ppos
, map
, len
);
1130 static const struct file_operations ad9467_calib_table_fops
= {
1131 .open
= simple_open
,
1132 .read
= ad9467_dump_calib_table
,
1133 .llseek
= default_llseek
,
1134 .owner
= THIS_MODULE
,
1137 static void ad9467_debugfs_init(struct iio_dev
*indio_dev
)
1139 struct dentry
*d
= iio_get_debugfs_dentry(indio_dev
);
1140 struct ad9467_state
*st
= iio_priv(indio_dev
);
1144 if (!IS_ENABLED(CONFIG_DEBUG_FS
))
1147 st
->chan_test
= devm_kcalloc(&st
->spi
->dev
, st
->info
->num_channels
,
1148 sizeof(*st
->chan_test
), GFP_KERNEL
);
1152 debugfs_create_file("calibration_table_dump", 0400, d
, st
,
1153 &ad9467_calib_table_fops
);
1155 for (chan
= 0; chan
< st
->info
->num_channels
; chan
++) {
1156 snprintf(attr_name
, sizeof(attr_name
), "in_voltage%u_test_mode",
1158 st
->chan_test
[chan
].idx
= chan
;
1159 st
->chan_test
[chan
].st
= st
;
1160 debugfs_create_file(attr_name
, 0600, d
, &st
->chan_test
[chan
],
1161 &ad9467_chan_test_mode_fops
);
1164 debugfs_create_file("in_voltage_test_mode_available", 0400, d
, st
,
1165 &ad9467_test_mode_available_fops
);
1167 iio_backend_debugfs_add(st
->back
, indio_dev
);
1170 static int ad9467_probe(struct spi_device
*spi
)
1172 struct iio_dev
*indio_dev
;
1173 struct ad9467_state
*st
;
1177 indio_dev
= devm_iio_device_alloc(&spi
->dev
, sizeof(*st
));
1181 st
= iio_priv(indio_dev
);
1184 st
->info
= spi_get_device_match_data(spi
);
1188 st
->calib_map_size
= st
->info
->test_points
;
1189 if (AD9467_CAN_INVERT(st
))
1190 st
->calib_map_size
*= 2;
1192 st
->clk
= devm_clk_get_enabled(&spi
->dev
, "adc-clk");
1193 if (IS_ERR(st
->clk
))
1194 return PTR_ERR(st
->clk
);
1196 st
->pwrdown_gpio
= devm_gpiod_get_optional(&spi
->dev
, "powerdown",
1198 if (IS_ERR(st
->pwrdown_gpio
))
1199 return PTR_ERR(st
->pwrdown_gpio
);
1201 ret
= ad9467_reset(&spi
->dev
);
1205 ret
= ad9467_scale_fill(st
);
1209 id
= ad9467_spi_read(st
, AN877_ADC_REG_CHIP_ID
);
1210 if (id
!= st
->info
->id
) {
1211 dev_err(&spi
->dev
, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n",
1216 if (st
->info
->num_scales
> 1)
1217 ad9467_info
.read_avail
= ad9467_read_avail
;
1218 indio_dev
->name
= st
->info
->name
;
1219 indio_dev
->channels
= st
->info
->channels
;
1220 indio_dev
->num_channels
= st
->info
->num_channels
;
1221 indio_dev
->info
= &ad9467_info
;
1223 ret
= ad9467_iio_backend_get(st
);
1227 ret
= devm_iio_backend_request_buffer(&spi
->dev
, st
->back
, indio_dev
);
1231 ret
= devm_iio_backend_enable(&spi
->dev
, st
->back
);
1235 ret
= ad9467_calibrate(st
);
1239 ret
= devm_iio_device_register(&spi
->dev
, indio_dev
);
1243 ad9467_debugfs_init(indio_dev
);
1248 static const struct of_device_id ad9467_of_match
[] = {
1249 { .compatible
= "adi,ad9265", .data
= &ad9265_chip_tbl
, },
1250 { .compatible
= "adi,ad9434", .data
= &ad9434_chip_tbl
, },
1251 { .compatible
= "adi,ad9467", .data
= &ad9467_chip_tbl
, },
1252 { .compatible
= "adi,ad9643", .data
= &ad9643_chip_tbl
, },
1253 { .compatible
= "adi,ad9649", .data
= &ad9649_chip_tbl
, },
1254 { .compatible
= "adi,ad9652", .data
= &ad9652_chip_tbl
, },
1257 MODULE_DEVICE_TABLE(of
, ad9467_of_match
);
1259 static const struct spi_device_id ad9467_ids
[] = {
1260 { "ad9265", (kernel_ulong_t
)&ad9265_chip_tbl
},
1261 { "ad9434", (kernel_ulong_t
)&ad9434_chip_tbl
},
1262 { "ad9467", (kernel_ulong_t
)&ad9467_chip_tbl
},
1263 { "ad9643", (kernel_ulong_t
)&ad9643_chip_tbl
},
1264 { "ad9649", (kernel_ulong_t
)&ad9649_chip_tbl
, },
1265 { "ad9652", (kernel_ulong_t
)&ad9652_chip_tbl
, },
1268 MODULE_DEVICE_TABLE(spi
, ad9467_ids
);
1270 static struct spi_driver ad9467_driver
= {
1273 .of_match_table
= ad9467_of_match
,
1275 .probe
= ad9467_probe
,
1276 .id_table
= ad9467_ids
,
1278 module_spi_driver(ad9467_driver
);
1280 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1281 MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver");
1282 MODULE_LICENSE("GPL v2");
1283 MODULE_IMPORT_NS("IIO_BACKEND");