drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3 * Copyright (C) 2012 Invensense, Inc.
   4 */
   5
   6 #ifndef INV_MPU_IIO_H_
   7 #define INV_MPU_IIO_H_
   8
   9 #include <linux/i2c.h>
  10 #include <linux/i2c-mux.h>
  11 #include <linux/mutex.h>
  12 #include <linux/platform_data/invensense_mpu6050.h>
  13 #include <linux/regmap.h>
  14
  15 #include <linux/iio/buffer.h>
  16 #include <linux/iio/common/inv_sensors_timestamp.h>
  17 #include <linux/iio/iio.h>
  18 #include <linux/iio/kfifo_buf.h>
  19 #include <linux/iio/trigger.h>
  20 #include <linux/iio/triggered_buffer.h>
  21 #include <linux/iio/trigger_consumer.h>
  22 #include <linux/iio/sysfs.h>
  23
  24 /**
  25  *  struct inv_mpu6050_reg_map - Notable registers.
  26  *  @sample_rate_div:   Divider applied to gyro output rate.
  27  *  @lpf:               Configures internal low pass filter.
  28  *  @accel_lpf:         Configures accelerometer low pass filter.
  29  *  @user_ctrl:         Enables/resets the FIFO.
  30  *  @fifo_en:           Determines which data will appear in FIFO.
  31  *  @gyro_config:       gyro config register.
  32  *  @accl_config:       accel config register
  33  *  @fifo_count_h:      Upper byte of FIFO count.
  34  *  @fifo_r_w:          FIFO register.
  35  *  @raw_gyro:          Address of first gyro register.
  36  *  @raw_accl:          Address of first accel register.
  37  *  @temperature:       temperature register
  38  *  @int_enable:        Interrupt enable register.
  39  *  @int_status:        Interrupt status register.
  40  *  @pwr_mgmt_1:        Controls chip's power state and clock source.
  41  *  @pwr_mgmt_2:        Controls power state of individual sensors.
  42  *  @int_pin_cfg;       Controls interrupt pin configuration.
  43  *  @accl_offset:       Controls the accelerometer calibration offset.
  44  *  @gyro_offset:       Controls the gyroscope calibration offset.
  45  *  @i2c_if:            Controls the i2c interface
  46  */
  47 struct inv_mpu6050_reg_map {
  48         u8 sample_rate_div;
  49         u8 lpf;
  50         u8 accel_lpf;
  51         u8 user_ctrl;
  52         u8 fifo_en;
  53         u8 gyro_config;
  54         u8 accl_config;
  55         u8 fifo_count_h;
  56         u8 fifo_r_w;
  57         u8 raw_gyro;
  58         u8 raw_accl;
  59         u8 temperature;
  60         u8 int_enable;
  61         u8 int_status;
  62         u8 pwr_mgmt_1;
  63         u8 pwr_mgmt_2;
  64         u8 int_pin_cfg;
  65         u8 accl_offset;
  66         u8 gyro_offset;
  67         u8 i2c_if;
  68 };
  69
  70 /*device enum */
  71 enum inv_devices {
  72         INV_MPU6050,
  73         INV_MPU6500,
  74         INV_MPU6515,
  75         INV_MPU6880,
  76         INV_MPU6000,
  77         INV_MPU9150,
  78         INV_MPU9250,
  79         INV_MPU9255,
  80         INV_ICM20608,
  81         INV_ICM20608D,
  82         INV_ICM20609,
  83         INV_ICM20689,
  84         INV_ICM20600,
  85         INV_ICM20602,
  86         INV_ICM20690,
  87         INV_IAM20680,
  88         INV_IAM20680HP,
  89         INV_IAM20680HT,
  90         INV_NUM_PARTS
  91 };
  92
  93 /* chip sensors mask: accelerometer, gyroscope, temperature, magnetometer, WoM */
  94 #define INV_MPU6050_SENSOR_ACCL         BIT(0)
  95 #define INV_MPU6050_SENSOR_GYRO         BIT(1)
  96 #define INV_MPU6050_SENSOR_TEMP         BIT(2)
  97 #define INV_MPU6050_SENSOR_MAGN         BIT(3)
  98 #define INV_MPU6050_SENSOR_WOM          BIT(4)
  99
 100 /**
 101  *  struct inv_mpu6050_chip_config - Cached chip configuration data.
 102  *  @clk:               selected chip clock
 103  *  @fsr:               Full scale range.
 104  *  @lpf:               Digital low pass filter frequency.
 105  *  @accl_fs:           accel full scale range.
 106  *  @accl_en:           accel engine enabled
 107  *  @gyro_en:           gyro engine enabled
 108  *  @temp_en:           temperature sensor enabled
 109  *  @magn_en:           magn engine (i2c master) enabled
 110  *  @wom_en:            Wake-on-Motion enabled
 111  *  @accl_fifo_enable:  enable accel data output
 112  *  @gyro_fifo_enable:  enable gyro data output
 113  *  @temp_fifo_enable:  enable temp data output
 114  *  @magn_fifo_enable:  enable magn data output
 115  *  @divider:           chip sample rate divider (sample rate divider - 1)
 116  *  @roc_threshold:     save ROC threshold (WoM) set value
 117  */
 118 struct inv_mpu6050_chip_config {
 119         unsigned int clk:3;
 120         unsigned int fsr:2;
 121         unsigned int lpf:3;
 122         unsigned int accl_fs:2;
 123         unsigned int accl_en:1;
 124         unsigned int gyro_en:1;
 125         unsigned int temp_en:1;
 126         unsigned int magn_en:1;
 127         unsigned int wom_en:1;
 128         unsigned int accl_fifo_enable:1;
 129         unsigned int gyro_fifo_enable:1;
 130         unsigned int temp_fifo_enable:1;
 131         unsigned int magn_fifo_enable:1;
 132         u8 divider;
 133         u8 user_ctrl;
 134         u64 roc_threshold;
 135 };
 136
 137 /*
 138  * Maximum of 6 + 6 + 2 + 7 (for MPU9x50) = 21 round up to 24 and plus 8.
 139  * May be less if fewer channels are enabled, as long as the timestamp
 140  * remains 8 byte aligned
 141  */
 142 #define INV_MPU6050_OUTPUT_DATA_SIZE         32
 143
 144 /**
 145  *  struct inv_mpu6050_hw - Other important hardware information.
 146  *  @whoami:    Self identification byte from WHO_AM_I register
 147  *  @name:      name of the chip.
 148  *  @reg:   register map of the chip.
 149  *  @config:    configuration of the chip.
 150  *  @fifo_size: size of the FIFO in bytes.
 151  *  @temp:      offset and scale to apply to raw temperature.
 152  */
 153 struct inv_mpu6050_hw {
 154         u8 whoami;
 155         u8 *name;
 156         const struct inv_mpu6050_reg_map *reg;
 157         const struct inv_mpu6050_chip_config *config;
 158         size_t fifo_size;
 159         struct {
 160                 int offset;
 161                 int scale;
 162         } temp;
 163         struct {
 164                 unsigned int accel;
 165                 unsigned int gyro;
 166         } startup_time;
 167 };
 168
 169 /*
 170  *  struct inv_mpu6050_state - Driver state variables.
 171  *  @lock:              Chip access lock.
 172  *  @trig:              IIO trigger.
 173  *  @chip_config:       Cached attribute information.
 174  *  @reg:               Map of important registers.
 175  *  @hw:                Other hardware-specific information.
 176  *  @chip_type:         chip type.
 177  *  @plat_data:         platform data (deprecated in favor of @orientation).
 178  *  @orientation:       sensor chip orientation relative to main hardware.
 179  *  @map                regmap pointer.
 180  *  @irq                interrupt number.
 181  *  @irq_mask           the int_pin_cfg mask to configure interrupt type.
 182  *  @timestamp:         timestamping module
 183  *  @vdd_supply:        VDD voltage regulator for the chip.
 184  *  @vddio_supply       I/O voltage regulator for the chip.
 185  *  @magn_disabled:     magnetometer disabled for backward compatibility reason.
 186  *  @magn_raw_to_gauss: coefficient to convert mag raw value to Gauss.
 187  *  @magn_orient:       magnetometer sensor chip orientation if available.
 188  *  @suspended_sensors: sensors mask of sensors turned off for suspend
 189  *  @data:              read buffer used for bulk reads.
 190  *  @it_timestamp:      interrupt timestamp.
 191  */
 192 struct inv_mpu6050_state {
 193         struct mutex lock;
 194         struct iio_trigger  *trig;
 195         struct inv_mpu6050_chip_config chip_config;
 196         const struct inv_mpu6050_reg_map *reg;
 197         const struct inv_mpu6050_hw *hw;
 198         enum   inv_devices chip_type;
 199         struct i2c_mux_core *muxc;
 200         struct i2c_client *mux_client;
 201         struct inv_mpu6050_platform_data plat_data;
 202         struct iio_mount_matrix orientation;
 203         struct regmap *map;
 204         int irq;
 205         u8 irq_mask;
 206         unsigned skip_samples;
 207         struct inv_sensors_timestamp timestamp;
 208         struct regulator *vdd_supply;
 209         struct regulator *vddio_supply;
 210         bool magn_disabled;
 211         s32 magn_raw_to_gauss[3];
 212         struct iio_mount_matrix magn_orient;
 213         unsigned int suspended_sensors;
 214         bool level_shifter;
 215         u8 *data;
 216         s64 it_timestamp;
 217 };
 218
 219 /*register and associated bit definition*/
 220 #define INV_MPU6050_REG_ACCEL_OFFSET        0x06
 221 #define INV_MPU6050_REG_GYRO_OFFSET         0x13
 222
 223 #define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
 224 #define INV_MPU6050_REG_CONFIG              0x1A
 225 #define INV_MPU6050_REG_GYRO_CONFIG         0x1B
 226 #define INV_MPU6050_REG_ACCEL_CONFIG        0x1C
 227
 228 #define INV_MPU6050_REG_FIFO_EN             0x23
 229 #define INV_MPU6050_BIT_SLAVE_0             0x01
 230 #define INV_MPU6050_BIT_SLAVE_1             0x02
 231 #define INV_MPU6050_BIT_SLAVE_2             0x04
 232 #define INV_MPU6050_BIT_ACCEL_OUT           0x08
 233 #define INV_MPU6050_BITS_GYRO_OUT           0x70
 234 #define INV_MPU6050_BIT_TEMP_OUT            0x80
 235
 236 #define INV_MPU6050_REG_I2C_MST_CTRL        0x24
 237 #define INV_MPU6050_BITS_I2C_MST_CLK_400KHZ 0x0D
 238 #define INV_MPU6050_BIT_I2C_MST_P_NSR       0x10
 239 #define INV_MPU6050_BIT_SLV3_FIFO_EN        0x20
 240 #define INV_MPU6050_BIT_WAIT_FOR_ES         0x40
 241 #define INV_MPU6050_BIT_MULT_MST_EN         0x80
 242
 243 /* control I2C slaves from 0 to 3 */
 244 #define INV_MPU6050_REG_I2C_SLV_ADDR(_x)    (0x25 + 3 * (_x))
 245 #define INV_MPU6050_BIT_I2C_SLV_RNW         0x80
 246
 247 #define INV_MPU6050_REG_I2C_SLV_REG(_x)     (0x26 + 3 * (_x))
 248
 249 #define INV_MPU6050_REG_I2C_SLV_CTRL(_x)    (0x27 + 3 * (_x))
 250 #define INV_MPU6050_BIT_SLV_GRP             0x10
 251 #define INV_MPU6050_BIT_SLV_REG_DIS         0x20
 252 #define INV_MPU6050_BIT_SLV_BYTE_SW         0x40
 253 #define INV_MPU6050_BIT_SLV_EN              0x80
 254
 255 /* I2C master delay register */
 256 #define INV_MPU6050_REG_I2C_SLV4_CTRL       0x34
 257 #define INV_MPU6050_BITS_I2C_MST_DLY(_x)    ((_x) & 0x1F)
 258
 259 #define INV_MPU6050_REG_I2C_MST_STATUS      0x36
 260 #define INV_MPU6050_BIT_I2C_SLV0_NACK       0x01
 261 #define INV_MPU6050_BIT_I2C_SLV1_NACK       0x02
 262 #define INV_MPU6050_BIT_I2C_SLV2_NACK       0x04
 263 #define INV_MPU6050_BIT_I2C_SLV3_NACK       0x08
 264
 265 #define INV_MPU6050_REG_INT_ENABLE          0x38
 266 #define INV_MPU6050_BIT_DATA_RDY_EN         0x01
 267 #define INV_MPU6050_BIT_DMP_INT_EN          0x02
 268 #define INV_MPU6500_BIT_WOM_INT_EN          BIT(6)
 269 #define INV_ICM20608_BIT_WOM_INT_EN         GENMASK(7, 5)
 270
 271 #define INV_MPU6050_REG_RAW_ACCEL           0x3B
 272 #define INV_MPU6050_REG_TEMPERATURE         0x41
 273 #define INV_MPU6050_REG_RAW_GYRO            0x43
 274
 275 #define INV_MPU6050_REG_INT_STATUS          0x3A
 276 #define INV_MPU6500_BIT_WOM_INT             BIT(6)
 277 #define INV_ICM20608_BIT_WOM_INT            GENMASK(7, 5)
 278 #define INV_MPU6050_BIT_FIFO_OVERFLOW_INT   0x10
 279 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT    0x01
 280
 281 #define INV_MPU6050_REG_EXT_SENS_DATA       0x49
 282
 283 /* I2C slaves data output from 0 to 3 */
 284 #define INV_MPU6050_REG_I2C_SLV_DO(_x)      (0x63 + (_x))
 285
 286 #define INV_MPU6050_REG_I2C_MST_DELAY_CTRL  0x67
 287 #define INV_MPU6050_BIT_I2C_SLV0_DLY_EN     0x01
 288 #define INV_MPU6050_BIT_I2C_SLV1_DLY_EN     0x02
 289 #define INV_MPU6050_BIT_I2C_SLV2_DLY_EN     0x04
 290 #define INV_MPU6050_BIT_I2C_SLV3_DLY_EN     0x08
 291 #define INV_MPU6050_BIT_DELAY_ES_SHADOW     0x80
 292
 293 #define INV_MPU6050_REG_SIGNAL_PATH_RESET   0x68
 294 #define INV_MPU6050_BIT_TEMP_RST            BIT(0)
 295 #define INV_MPU6050_BIT_ACCEL_RST           BIT(1)
 296 #define INV_MPU6050_BIT_GYRO_RST            BIT(2)
 297
 298 #define INV_MPU6050_REG_USER_CTRL           0x6A
 299 #define INV_MPU6050_BIT_SIG_COND_RST        0x01
 300 #define INV_MPU6050_BIT_FIFO_RST            0x04
 301 #define INV_MPU6050_BIT_DMP_RST             0x08
 302 #define INV_MPU6050_BIT_I2C_MST_EN          0x20
 303 #define INV_MPU6050_BIT_FIFO_EN             0x40
 304 #define INV_MPU6050_BIT_DMP_EN              0x80
 305 #define INV_MPU6050_BIT_I2C_IF_DIS          0x10
 306
 307 #define INV_MPU6050_REG_PWR_MGMT_1          0x6B
 308 #define INV_MPU6050_BIT_H_RESET             0x80
 309 #define INV_MPU6050_BIT_SLEEP               0x40
 310 #define INV_MPU6050_BIT_CYCLE               0x20
 311 #define INV_MPU6050_BIT_TEMP_DIS            0x08
 312 #define INV_MPU6050_BIT_CLK_MASK            0x7
 313
 314 #define INV_MPU6050_REG_PWR_MGMT_2          0x6C
 315 #define INV_MPU6050_BIT_PWR_ACCL_STBY       0x38
 316 #define INV_MPU6050_BIT_PWR_GYRO_STBY       0x07
 317
 318 /* ICM20609 registers */
 319 #define INV_ICM20609_REG_ACCEL_WOM_X_THR    0x20
 320 #define INV_ICM20609_REG_ACCEL_WOM_Y_THR    0x21
 321 #define INV_ICM20609_REG_ACCEL_WOM_Z_THR    0x22
 322
 323 /* ICM20602 register */
 324 #define INV_ICM20602_REG_I2C_IF             0x70
 325 #define INV_ICM20602_BIT_I2C_IF_DIS         0x40
 326
 327 #define INV_MPU6050_REG_FIFO_COUNT_H        0x72
 328 #define INV_MPU6050_REG_FIFO_R_W            0x74
 329
 330 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
 331 #define INV_MPU6050_FIFO_COUNT_BYTE          2
 332
 333 /* MPU9X50 9-axis magnetometer */
 334 #define INV_MPU9X50_BYTES_MAGN               7
 335
 336 /* FIFO temperature sample size */
 337 #define INV_MPU6050_BYTES_PER_TEMP_SENSOR   2
 338
 339 /* mpu6500 registers */
 340 #define INV_MPU6500_REG_ACCEL_CONFIG_2      0x1D
 341 #define INV_ICM20689_BITS_FIFO_SIZE_MAX     0xC0
 342 #define INV_MPU6500_REG_LP_ODR              0x1E
 343 #define INV_MPU6500_REG_WOM_THRESHOLD       0x1F
 344 #define INV_MPU6500_REG_ACCEL_INTEL_CTRL    0x69
 345 #define INV_MPU6500_BIT_ACCEL_INTEL_EN      BIT(7)
 346 #define INV_MPU6500_BIT_ACCEL_INTEL_MODE    BIT(6)
 347 #define INV_MPU6500_REG_ACCEL_OFFSET        0x77
 348
 349 /* delay time in milliseconds */
 350 #define INV_MPU6050_POWER_UP_TIME            100
 351 #define INV_MPU6050_TEMP_UP_TIME             100
 352 #define INV_MPU6050_ACCEL_STARTUP_TIME       20
 353 #define INV_MPU6050_GYRO_STARTUP_TIME        60
 354 #define INV_MPU6050_GYRO_DOWN_TIME           150
 355 #define INV_MPU6050_SUSPEND_DELAY_MS         2000
 356
 357 #define INV_MPU6500_GYRO_STARTUP_TIME        70
 358 #define INV_MPU6500_ACCEL_STARTUP_TIME       30
 359
 360 #define INV_ICM20602_GYRO_STARTUP_TIME       100
 361 #define INV_ICM20602_ACCEL_STARTUP_TIME      20
 362
 363 #define INV_ICM20690_GYRO_STARTUP_TIME       80
 364 #define INV_ICM20690_ACCEL_STARTUP_TIME      10
 365
 366
 367 /* delay time in microseconds */
 368 #define INV_MPU6050_REG_UP_TIME_MIN          5000
 369 #define INV_MPU6050_REG_UP_TIME_MAX          10000
 370
 371 #define INV_MPU6050_TEMP_OFFSET              12420
 372 #define INV_MPU6050_TEMP_SCALE               2941176
 373 #define INV_MPU6050_MAX_GYRO_FS_PARAM        3
 374 #define INV_MPU6050_MAX_ACCL_FS_PARAM        3
 375 #define INV_MPU6050_THREE_AXIS               3
 376 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
 377 #define INV_ICM20690_GYRO_CONFIG_FSR_SHIFT   2
 378 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3
 379
 380 #define INV_MPU6500_TEMP_OFFSET              7011
 381 #define INV_MPU6500_TEMP_SCALE               2995178
 382
 383 #define INV_ICM20608_TEMP_OFFSET             8170
 384 #define INV_ICM20608_TEMP_SCALE              3059976
 385
 386 #define INV_MPU6050_REG_INT_PIN_CFG     0x37
 387 #define INV_MPU6050_ACTIVE_HIGH         0x00
 388 #define INV_MPU6050_ACTIVE_LOW          0x80
 389 /* enable level triggering */
 390 #define INV_MPU6050_LATCH_INT_EN        0x20
 391 #define INV_MPU6050_BIT_BYPASS_EN       0x2
 392
 393 /* Allowed timestamp period jitter in percent */
 394 #define INV_MPU6050_TS_PERIOD_JITTER    4
 395
 396 /* init parameters */
 397 #define INV_MPU6050_MAX_FIFO_RATE            1000
 398 #define INV_MPU6050_MIN_FIFO_RATE            4
 399
 400 /* chip internal frequency: 1KHz */
 401 #define INV_MPU6050_INTERNAL_FREQ_HZ            1000
 402 /* return the frequency divider (chip sample rate divider + 1) */
 403 #define INV_MPU6050_FREQ_DIVIDER(st)                                    \
 404         ((st)->chip_config.divider + 1)
 405 /* chip sample rate divider to fifo rate */
 406 #define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate)                     \
 407         ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)
 408 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider)                       \
 409         (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))
 410
 411 #define INV_MPU6050_REG_WHOAMI                  117
 412
 413 #define INV_MPU6000_WHOAMI_VALUE                0x68
 414 #define INV_MPU6050_WHOAMI_VALUE                0x68
 415 #define INV_MPU6500_WHOAMI_VALUE                0x70
 416 #define INV_MPU6880_WHOAMI_VALUE                0x78
 417 #define INV_MPU9150_WHOAMI_VALUE                0x68
 418 #define INV_MPU9250_WHOAMI_VALUE                0x71
 419 #define INV_MPU9255_WHOAMI_VALUE                0x73
 420 #define INV_MPU6515_WHOAMI_VALUE                0x74
 421 #define INV_ICM20608_WHOAMI_VALUE               0xAF
 422 #define INV_ICM20608D_WHOAMI_VALUE              0xAE
 423 #define INV_ICM20609_WHOAMI_VALUE               0xA6
 424 #define INV_ICM20689_WHOAMI_VALUE               0x98
 425 #define INV_ICM20600_WHOAMI_VALUE               0x11
 426 #define INV_ICM20602_WHOAMI_VALUE               0x12
 427 #define INV_ICM20690_WHOAMI_VALUE               0x20
 428 #define INV_IAM20680_WHOAMI_VALUE               0xA9
 429 #define INV_IAM20680HP_WHOAMI_VALUE             0xF8
 430 #define INV_IAM20680HT_WHOAMI_VALUE             0xFA
 431
 432 /* scan element definition for generic MPU6xxx devices */
 433 enum inv_mpu6050_scan {
 434         INV_MPU6050_SCAN_ACCL_X,
 435         INV_MPU6050_SCAN_ACCL_Y,
 436         INV_MPU6050_SCAN_ACCL_Z,
 437         INV_MPU6050_SCAN_TEMP,
 438         INV_MPU6050_SCAN_GYRO_X,
 439         INV_MPU6050_SCAN_GYRO_Y,
 440         INV_MPU6050_SCAN_GYRO_Z,
 441         INV_MPU6050_SCAN_TIMESTAMP,
 442
 443         INV_MPU9X50_SCAN_MAGN_X = INV_MPU6050_SCAN_GYRO_Z + 1,
 444         INV_MPU9X50_SCAN_MAGN_Y,
 445         INV_MPU9X50_SCAN_MAGN_Z,
 446         INV_MPU9X50_SCAN_TIMESTAMP,
 447 };
 448
 449 enum inv_mpu6050_filter_e {
 450         INV_MPU6050_FILTER_NOLPF2 = 0,
 451         INV_MPU6050_FILTER_200HZ,
 452         INV_MPU6050_FILTER_100HZ,
 453         INV_MPU6050_FILTER_45HZ,
 454         INV_MPU6050_FILTER_20HZ,
 455         INV_MPU6050_FILTER_10HZ,
 456         INV_MPU6050_FILTER_5HZ,
 457         INV_MPU6050_FILTER_NOLPF,
 458         NUM_MPU6050_FILTER
 459 };
 460
 461 enum inv_mpu6050_lposc_e {
 462         INV_MPU6050_LPOSC_4HZ = 4,
 463         INV_MPU6050_LPOSC_8HZ,
 464         INV_MPU6050_LPOSC_16HZ,
 465         INV_MPU6050_LPOSC_31HZ,
 466         INV_MPU6050_LPOSC_62HZ,
 467         INV_MPU6050_LPOSC_125HZ,
 468         INV_MPU6050_LPOSC_250HZ,
 469         INV_MPU6050_LPOSC_500HZ,
 470         NUM_MPU6050_LPOSC,
 471 };
 472
 473 /* IIO attribute address */
 474 enum INV_MPU6050_IIO_ATTR_ADDR {
 475         ATTR_GYRO_MATRIX,
 476         ATTR_ACCL_MATRIX,
 477 };
 478
 479 enum inv_mpu6050_accl_fs_e {
 480         INV_MPU6050_FS_02G = 0,
 481         INV_MPU6050_FS_04G,
 482         INV_MPU6050_FS_08G,
 483         INV_MPU6050_FS_16G,
 484         NUM_ACCL_FSR
 485 };
 486
 487 enum inv_mpu6050_fsr_e {
 488         INV_MPU6050_FSR_250DPS = 0,
 489         INV_MPU6050_FSR_500DPS,
 490         INV_MPU6050_FSR_1000DPS,
 491         INV_MPU6050_FSR_2000DPS,
 492         NUM_MPU6050_FSR
 493 };
 494
 495 enum inv_mpu6050_clock_sel_e {
 496         INV_CLK_INTERNAL = 0,
 497         INV_CLK_PLL,
 498         NUM_CLK
 499 };
 500
 501 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
 502 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
 503 int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable);
 504 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en,
 505                               unsigned int mask);
 506 int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
 507 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
 508 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
 509                 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
 510 extern const struct dev_pm_ops inv_mpu_pmops;
 511
 512 #endif