drivers/interconnect/qcom/qcs615.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
   4  *
   5  */
   6
   7 #include <linux/device.h>
   8 #include <linux/interconnect.h>
   9 #include <linux/interconnect-provider.h>
  10 #include <linux/module.h>
  11 #include <linux/of_platform.h>
  12 #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
  13
  14 #include "bcm-voter.h"
  15 #include "icc-rpmh.h"
  16 #include "qcs615.h"
  17
  18 static struct qcom_icc_node qhm_a1noc_cfg = {
  19         .name = "qhm_a1noc_cfg",
  20         .id = QCS615_MASTER_A1NOC_CFG,
  21         .channels = 1,
  22         .buswidth = 4,
  23         .num_links = 1,
  24         .links = { QCS615_SLAVE_SERVICE_A2NOC },
  25 };
  26
  27 static struct qcom_icc_node qhm_qdss_bam = {
  28         .name = "qhm_qdss_bam",
  29         .id = QCS615_MASTER_QDSS_BAM,
  30         .channels = 1,
  31         .buswidth = 4,
  32         .num_links = 1,
  33         .links = { QCS615_SLAVE_A1NOC_SNOC },
  34 };
  35
  36 static struct qcom_icc_node qhm_qspi = {
  37         .name = "qhm_qspi",
  38         .id = QCS615_MASTER_QSPI,
  39         .channels = 1,
  40         .buswidth = 4,
  41         .num_links = 1,
  42         .links = { QCS615_SLAVE_A1NOC_SNOC },
  43 };
  44
  45 static struct qcom_icc_node qhm_qup0 = {
  46         .name = "qhm_qup0",
  47         .id = QCS615_MASTER_QUP_0,
  48         .channels = 1,
  49         .buswidth = 4,
  50         .num_links = 1,
  51         .links = { QCS615_SLAVE_A1NOC_SNOC },
  52 };
  53
  54 static struct qcom_icc_node qhm_qup1 = {
  55         .name = "qhm_qup1",
  56         .id = QCS615_MASTER_BLSP_1,
  57         .channels = 1,
  58         .buswidth = 4,
  59         .num_links = 1,
  60         .links = { QCS615_SLAVE_A1NOC_SNOC },
  61 };
  62
  63 static struct qcom_icc_node qnm_cnoc = {
  64         .name = "qnm_cnoc",
  65         .id = QCS615_MASTER_CNOC_A2NOC,
  66         .channels = 1,
  67         .buswidth = 8,
  68         .num_links = 1,
  69         .links = { QCS615_SLAVE_A1NOC_SNOC },
  70 };
  71
  72 static struct qcom_icc_node qxm_crypto = {
  73         .name = "qxm_crypto",
  74         .id = QCS615_MASTER_CRYPTO,
  75         .channels = 1,
  76         .buswidth = 8,
  77         .num_links = 1,
  78         .links = { QCS615_SLAVE_A1NOC_SNOC },
  79 };
  80
  81 static struct qcom_icc_node qxm_ipa = {
  82         .name = "qxm_ipa",
  83         .id = QCS615_MASTER_IPA,
  84         .channels = 1,
  85         .buswidth = 8,
  86         .num_links = 1,
  87         .links = { QCS615_SLAVE_LPASS_SNOC },
  88 };
  89
  90 static struct qcom_icc_node xm_emac_avb = {
  91         .name = "xm_emac_avb",
  92         .id = QCS615_MASTER_EMAC_EVB,
  93         .channels = 1,
  94         .buswidth = 8,
  95         .num_links = 1,
  96         .links = { QCS615_SLAVE_A1NOC_SNOC },
  97 };
  98
  99 static struct qcom_icc_node xm_pcie = {
 100         .name = "xm_pcie",
 101         .id = QCS615_MASTER_PCIE,
 102         .channels = 1,
 103         .buswidth = 8,
 104         .num_links = 1,
 105         .links = { QCS615_SLAVE_ANOC_PCIE_SNOC },
 106 };
 107
 108 static struct qcom_icc_node xm_qdss_etr = {
 109         .name = "xm_qdss_etr",
 110         .id = QCS615_MASTER_QDSS_ETR,
 111         .channels = 1,
 112         .buswidth = 8,
 113         .num_links = 1,
 114         .links = { QCS615_SLAVE_A1NOC_SNOC },
 115 };
 116
 117 static struct qcom_icc_node xm_sdc1 = {
 118         .name = "xm_sdc1",
 119         .id = QCS615_MASTER_SDCC_1,
 120         .channels = 1,
 121         .buswidth = 8,
 122         .num_links = 1,
 123         .links = { QCS615_SLAVE_A1NOC_SNOC },
 124 };
 125
 126 static struct qcom_icc_node xm_sdc2 = {
 127         .name = "xm_sdc2",
 128         .id = QCS615_MASTER_SDCC_2,
 129         .channels = 1,
 130         .buswidth = 8,
 131         .num_links = 1,
 132         .links = { QCS615_SLAVE_A1NOC_SNOC },
 133 };
 134
 135 static struct qcom_icc_node xm_ufs_mem = {
 136         .name = "xm_ufs_mem",
 137         .id = QCS615_MASTER_UFS_MEM,
 138         .channels = 1,
 139         .buswidth = 8,
 140         .num_links = 1,
 141         .links = { QCS615_SLAVE_A1NOC_SNOC },
 142 };
 143
 144 static struct qcom_icc_node xm_usb2 = {
 145         .name = "xm_usb2",
 146         .id = QCS615_MASTER_USB2,
 147         .channels = 1,
 148         .buswidth = 8,
 149         .num_links = 1,
 150         .links = { QCS615_SLAVE_A1NOC_SNOC },
 151 };
 152
 153 static struct qcom_icc_node xm_usb3_0 = {
 154         .name = "xm_usb3_0",
 155         .id = QCS615_MASTER_USB3_0,
 156         .channels = 1,
 157         .buswidth = 8,
 158         .num_links = 1,
 159         .links = { QCS615_SLAVE_A1NOC_SNOC },
 160 };
 161
 162 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
 163         .name = "qxm_camnoc_hf0_uncomp",
 164         .id = QCS615_MASTER_CAMNOC_HF0_UNCOMP,
 165         .channels = 1,
 166         .buswidth = 32,
 167         .num_links = 1,
 168         .links = { QCS615_SLAVE_CAMNOC_UNCOMP },
 169 };
 170
 171 static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
 172         .name = "qxm_camnoc_hf1_uncomp",
 173         .id = QCS615_MASTER_CAMNOC_HF1_UNCOMP,
 174         .channels = 1,
 175         .buswidth = 32,
 176         .num_links = 1,
 177         .links = { QCS615_SLAVE_CAMNOC_UNCOMP },
 178 };
 179
 180 static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
 181         .name = "qxm_camnoc_sf_uncomp",
 182         .id = QCS615_MASTER_CAMNOC_SF_UNCOMP,
 183         .channels = 1,
 184         .buswidth = 32,
 185         .num_links = 1,
 186         .links = { QCS615_SLAVE_CAMNOC_UNCOMP },
 187 };
 188
 189 static struct qcom_icc_node qhm_spdm = {
 190         .name = "qhm_spdm",
 191         .id = QCS615_MASTER_SPDM,
 192         .channels = 1,
 193         .buswidth = 4,
 194         .num_links = 1,
 195         .links = { QCS615_SLAVE_CNOC_A2NOC },
 196 };
 197
 198 static struct qcom_icc_node qnm_snoc = {
 199         .name = "qnm_snoc",
 200         .id = QCS615_MASTER_SNOC_CNOC,
 201         .channels = 1,
 202         .buswidth = 8,
 203         .num_links = 39,
 204         .links = { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST,
 205                    QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP,
 206                    QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG,
 207                    QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG,
 208                    QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG,
 209                    QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG,
 210                    QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM,
 211                    QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG,
 212                    QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG,
 213                    QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG,
 214                    QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG,
 215                    QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0,
 216                    QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1,
 217                    QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG,
 218                    QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR,
 219                    QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH,
 220                    QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG,
 221                    QCS615_SLAVE_USB2, QCS615_SLAVE_USB3,
 222                    QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG,
 223                    QCS615_SLAVE_SERVICE_CNOC },
 224 };
 225
 226 static struct qcom_icc_node xm_qdss_dap = {
 227         .name = "xm_qdss_dap",
 228         .id = QCS615_MASTER_QDSS_DAP,
 229         .channels = 1,
 230         .buswidth = 8,
 231         .num_links = 40,
 232         .links = { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST,
 233                    QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP,
 234                    QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG,
 235                    QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG,
 236                    QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG,
 237                    QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG,
 238                    QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM,
 239                    QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG,
 240                    QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG,
 241                    QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG,
 242                    QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG,
 243                    QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0,
 244                    QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1,
 245                    QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG,
 246                    QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR,
 247                    QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH,
 248                    QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG,
 249                    QCS615_SLAVE_USB2, QCS615_SLAVE_USB3,
 250                    QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG,
 251                    QCS615_SLAVE_CNOC_A2NOC, QCS615_SLAVE_SERVICE_CNOC },
 252 };
 253
 254 static struct qcom_icc_node qhm_cnoc = {
 255         .name = "qhm_cnoc",
 256         .id = QCS615_MASTER_CNOC_DC_NOC,
 257         .channels = 1,
 258         .buswidth = 4,
 259         .num_links = 2,
 260         .links = { QCS615_SLAVE_DC_NOC_GEMNOC, QCS615_SLAVE_LLCC_CFG },
 261 };
 262
 263 static struct qcom_icc_node acm_apps = {
 264         .name = "acm_apps",
 265         .id = QCS615_MASTER_APPSS_PROC,
 266         .channels = 1,
 267         .buswidth = 16,
 268         .num_links = 3,
 269         .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC,
 270                    QCS615_SLAVE_MEM_NOC_PCIE_SNOC },
 271 };
 272
 273 static struct qcom_icc_node acm_gpu_tcu = {
 274         .name = "acm_gpu_tcu",
 275         .id = QCS615_MASTER_GPU_TCU,
 276         .channels = 1,
 277         .buswidth = 8,
 278         .num_links = 2,
 279         .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC },
 280 };
 281
 282 static struct qcom_icc_node acm_sys_tcu = {
 283         .name = "acm_sys_tcu",
 284         .id = QCS615_MASTER_SYS_TCU,
 285         .channels = 1,
 286         .buswidth = 8,
 287         .num_links = 2,
 288         .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC },
 289 };
 290
 291 static struct qcom_icc_node qhm_gemnoc_cfg = {
 292         .name = "qhm_gemnoc_cfg",
 293         .id = QCS615_MASTER_GEM_NOC_CFG,
 294         .channels = 1,
 295         .buswidth = 4,
 296         .num_links = 2,
 297         .links = { QCS615_SLAVE_MSS_PROC_MS_MPU_CFG, QCS615_SLAVE_SERVICE_GEM_NOC },
 298 };
 299
 300 static struct qcom_icc_node qnm_gpu = {
 301         .name = "qnm_gpu",
 302         .id = QCS615_MASTER_GFX3D,
 303         .channels = 2,
 304         .buswidth = 32,
 305         .num_links = 2,
 306         .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC },
 307 };
 308
 309 static struct qcom_icc_node qnm_mnoc_hf = {
 310         .name = "qnm_mnoc_hf",
 311         .id = QCS615_MASTER_MNOC_HF_MEM_NOC,
 312         .channels = 1,
 313         .buswidth = 32,
 314         .num_links = 1,
 315         .links = { QCS615_SLAVE_LLCC },
 316 };
 317
 318 static struct qcom_icc_node qnm_mnoc_sf = {
 319         .name = "qnm_mnoc_sf",
 320         .id = QCS615_MASTER_MNOC_SF_MEM_NOC,
 321         .channels = 1,
 322         .buswidth = 32,
 323         .num_links = 2,
 324         .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC },
 325 };
 326
 327 static struct qcom_icc_node qnm_snoc_gc = {
 328         .name = "qnm_snoc_gc",
 329         .id = QCS615_MASTER_SNOC_GC_MEM_NOC,
 330         .channels = 1,
 331         .buswidth = 8,
 332         .num_links = 1,
 333         .links = { QCS615_SLAVE_LLCC },
 334 };
 335
 336 static struct qcom_icc_node qnm_snoc_sf = {
 337         .name = "qnm_snoc_sf",
 338         .id = QCS615_MASTER_SNOC_SF_MEM_NOC,
 339         .channels = 1,
 340         .buswidth = 16,
 341         .num_links = 1,
 342         .links = { QCS615_SLAVE_LLCC },
 343 };
 344
 345 static struct qcom_icc_node ipa_core_master = {
 346         .name = "ipa_core_master",
 347         .id = QCS615_MASTER_IPA_CORE,
 348         .channels = 1,
 349         .buswidth = 8,
 350         .num_links = 1,
 351         .links = { QCS615_SLAVE_IPA_CORE },
 352 };
 353
 354 static struct qcom_icc_node llcc_mc = {
 355         .name = "llcc_mc",
 356         .id = QCS615_MASTER_LLCC,
 357         .channels = 2,
 358         .buswidth = 4,
 359         .num_links = 1,
 360         .links = { QCS615_SLAVE_EBI1 },
 361 };
 362
 363 static struct qcom_icc_node qhm_mnoc_cfg = {
 364         .name = "qhm_mnoc_cfg",
 365         .id = QCS615_MASTER_CNOC_MNOC_CFG,
 366         .channels = 1,
 367         .buswidth = 4,
 368         .num_links = 1,
 369         .links = { QCS615_SLAVE_SERVICE_MNOC },
 370 };
 371
 372 static struct qcom_icc_node qxm_camnoc_hf0 = {
 373         .name = "qxm_camnoc_hf0",
 374         .id = QCS615_MASTER_CAMNOC_HF0,
 375         .channels = 1,
 376         .buswidth = 32,
 377         .num_links = 1,
 378         .links = { QCS615_SLAVE_MNOC_HF_MEM_NOC },
 379 };
 380
 381 static struct qcom_icc_node qxm_camnoc_hf1 = {
 382         .name = "qxm_camnoc_hf1",
 383         .id = QCS615_MASTER_CAMNOC_HF1,
 384         .channels = 1,
 385         .buswidth = 32,
 386         .num_links = 1,
 387         .links = { QCS615_SLAVE_MNOC_HF_MEM_NOC },
 388 };
 389
 390 static struct qcom_icc_node qxm_camnoc_sf = {
 391         .name = "qxm_camnoc_sf",
 392         .id = QCS615_MASTER_CAMNOC_SF,
 393         .channels = 1,
 394         .buswidth = 32,
 395         .num_links = 1,
 396         .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC },
 397 };
 398
 399 static struct qcom_icc_node qxm_mdp0 = {
 400         .name = "qxm_mdp0",
 401         .id = QCS615_MASTER_MDP0,
 402         .channels = 1,
 403         .buswidth = 32,
 404         .num_links = 1,
 405         .links = { QCS615_SLAVE_MNOC_HF_MEM_NOC },
 406 };
 407
 408 static struct qcom_icc_node qxm_rot = {
 409         .name = "qxm_rot",
 410         .id = QCS615_MASTER_ROTATOR,
 411         .channels = 1,
 412         .buswidth = 32,
 413         .num_links = 1,
 414         .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC },
 415 };
 416
 417 static struct qcom_icc_node qxm_venus0 = {
 418         .name = "qxm_venus0",
 419         .id = QCS615_MASTER_VIDEO_P0,
 420         .channels = 1,
 421         .buswidth = 32,
 422         .num_links = 1,
 423         .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC },
 424 };
 425
 426 static struct qcom_icc_node qxm_venus_arm9 = {
 427         .name = "qxm_venus_arm9",
 428         .id = QCS615_MASTER_VIDEO_PROC,
 429         .channels = 1,
 430         .buswidth = 8,
 431         .num_links = 1,
 432         .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC },
 433 };
 434
 435 static struct qcom_icc_node qhm_snoc_cfg = {
 436         .name = "qhm_snoc_cfg",
 437         .id = QCS615_MASTER_SNOC_CFG,
 438         .channels = 1,
 439         .buswidth = 4,
 440         .num_links = 1,
 441         .links = { QCS615_SLAVE_SERVICE_SNOC },
 442 };
 443
 444 static struct qcom_icc_node qnm_aggre1_noc = {
 445         .name = "qnm_aggre1_noc",
 446         .id = QCS615_MASTER_A1NOC_SNOC,
 447         .channels = 1,
 448         .buswidth = 16,
 449         .num_links = 8,
 450         .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC,
 451                    QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM,
 452                    QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0,
 453                    QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU },
 454 };
 455
 456 static struct qcom_icc_node qnm_gemnoc = {
 457         .name = "qnm_gemnoc",
 458         .id = QCS615_MASTER_GEM_NOC_SNOC,
 459         .channels = 1,
 460         .buswidth = 8,
 461         .num_links = 6,
 462         .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC,
 463                    QCS615_SLAVE_IMEM, QCS615_SLAVE_PIMEM,
 464                    QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU },
 465 };
 466
 467 static struct qcom_icc_node qnm_gemnoc_pcie = {
 468         .name = "qnm_gemnoc_pcie",
 469         .id = QCS615_MASTER_GEM_NOC_PCIE_SNOC,
 470         .channels = 1,
 471         .buswidth = 8,
 472         .num_links = 1,
 473         .links = { QCS615_SLAVE_PCIE_0 },
 474 };
 475
 476 static struct qcom_icc_node qnm_lpass_anoc = {
 477         .name = "qnm_lpass_anoc",
 478         .id = QCS615_MASTER_LPASS_ANOC,
 479         .channels = 1,
 480         .buswidth = 8,
 481         .num_links = 7,
 482         .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC,
 483                    QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM,
 484                    QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0,
 485                    QCS615_SLAVE_QDSS_STM },
 486 };
 487
 488 static struct qcom_icc_node qnm_pcie_anoc = {
 489         .name = "qnm_pcie_anoc",
 490         .id = QCS615_MASTER_ANOC_PCIE_SNOC,
 491         .channels = 1,
 492         .buswidth = 8,
 493         .num_links = 5,
 494         .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC,
 495                    QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM,
 496                    QCS615_SLAVE_QDSS_STM },
 497 };
 498
 499 static struct qcom_icc_node qxm_pimem = {
 500         .name = "qxm_pimem",
 501         .id = QCS615_MASTER_PIMEM,
 502         .channels = 1,
 503         .buswidth = 8,
 504         .num_links = 2,
 505         .links = { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM },
 506 };
 507
 508 static struct qcom_icc_node xm_gic = {
 509         .name = "xm_gic",
 510         .id = QCS615_MASTER_GIC,
 511         .channels = 1,
 512         .buswidth = 8,
 513         .num_links = 2,
 514         .links = { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM },
 515 };
 516
 517 static struct qcom_icc_node qns_a1noc_snoc = {
 518         .name = "qns_a1noc_snoc",
 519         .id = QCS615_SLAVE_A1NOC_SNOC,
 520         .channels = 1,
 521         .buswidth = 16,
 522         .num_links = 1,
 523         .links = { QCS615_MASTER_A1NOC_SNOC },
 524 };
 525
 526 static struct qcom_icc_node qns_lpass_snoc = {
 527         .name = "qns_lpass_snoc",
 528         .id = QCS615_SLAVE_LPASS_SNOC,
 529         .channels = 1,
 530         .buswidth = 8,
 531         .num_links = 1,
 532         .links = { QCS615_MASTER_LPASS_ANOC },
 533 };
 534
 535 static struct qcom_icc_node qns_pcie_snoc = {
 536         .name = "qns_pcie_snoc",
 537         .id = QCS615_SLAVE_ANOC_PCIE_SNOC,
 538         .channels = 1,
 539         .buswidth = 8,
 540         .num_links = 1,
 541         .links = { QCS615_MASTER_ANOC_PCIE_SNOC },
 542 };
 543
 544 static struct qcom_icc_node srvc_aggre2_noc = {
 545         .name = "srvc_aggre2_noc",
 546         .id = QCS615_SLAVE_SERVICE_A2NOC,
 547         .channels = 1,
 548         .buswidth = 4,
 549         .num_links = 0,
 550 };
 551
 552 static struct qcom_icc_node qns_camnoc_uncomp = {
 553         .name = "qns_camnoc_uncomp",
 554         .id = QCS615_SLAVE_CAMNOC_UNCOMP,
 555         .channels = 1,
 556         .buswidth = 32,
 557         .num_links = 0,
 558 };
 559
 560 static struct qcom_icc_node qhs_a1_noc_cfg = {
 561         .name = "qhs_a1_noc_cfg",
 562         .id = QCS615_SLAVE_A1NOC_CFG,
 563         .channels = 1,
 564         .buswidth = 4,
 565         .num_links = 1,
 566         .links = { QCS615_MASTER_A1NOC_CFG },
 567 };
 568
 569 static struct qcom_icc_node qhs_ahb2phy_east = {
 570         .name = "qhs_ahb2phy_east",
 571         .id = QCS615_SLAVE_AHB2PHY_EAST,
 572         .channels = 1,
 573         .buswidth = 4,
 574         .num_links = 0,
 575 };
 576
 577 static struct qcom_icc_node qhs_ahb2phy_west = {
 578         .name = "qhs_ahb2phy_west",
 579         .id = QCS615_SLAVE_AHB2PHY_WEST,
 580         .channels = 1,
 581         .buswidth = 4,
 582         .num_links = 0,
 583 };
 584
 585 static struct qcom_icc_node qhs_aop = {
 586         .name = "qhs_aop",
 587         .id = QCS615_SLAVE_AOP,
 588         .channels = 1,
 589         .buswidth = 4,
 590         .num_links = 0,
 591 };
 592
 593 static struct qcom_icc_node qhs_aoss = {
 594         .name = "qhs_aoss",
 595         .id = QCS615_SLAVE_AOSS,
 596         .channels = 1,
 597         .buswidth = 4,
 598         .num_links = 0,
 599 };
 600
 601 static struct qcom_icc_node qhs_camera_cfg = {
 602         .name = "qhs_camera_cfg",
 603         .id = QCS615_SLAVE_CAMERA_CFG,
 604         .channels = 1,
 605         .buswidth = 4,
 606         .num_links = 0,
 607 };
 608
 609 static struct qcom_icc_node qhs_clk_ctl = {
 610         .name = "qhs_clk_ctl",
 611         .id = QCS615_SLAVE_CLK_CTL,
 612         .channels = 1,
 613         .buswidth = 4,
 614         .num_links = 0,
 615 };
 616
 617 static struct qcom_icc_node qhs_cpr_cx = {
 618         .name = "qhs_cpr_cx",
 619         .id = QCS615_SLAVE_RBCPR_CX_CFG,
 620         .channels = 1,
 621         .buswidth = 4,
 622         .num_links = 0,
 623 };
 624
 625 static struct qcom_icc_node qhs_cpr_mx = {
 626         .name = "qhs_cpr_mx",
 627         .id = QCS615_SLAVE_RBCPR_MX_CFG,
 628         .channels = 1,
 629         .buswidth = 4,
 630         .num_links = 0,
 631 };
 632
 633 static struct qcom_icc_node qhs_crypto0_cfg = {
 634         .name = "qhs_crypto0_cfg",
 635         .id = QCS615_SLAVE_CRYPTO_0_CFG,
 636         .channels = 1,
 637         .buswidth = 4,
 638         .num_links = 0,
 639 };
 640
 641 static struct qcom_icc_node qhs_ddrss_cfg = {
 642         .name = "qhs_ddrss_cfg",
 643         .id = QCS615_SLAVE_CNOC_DDRSS,
 644         .channels = 1,
 645         .buswidth = 4,
 646         .num_links = 1,
 647         .links = { QCS615_MASTER_CNOC_DC_NOC },
 648 };
 649
 650 static struct qcom_icc_node qhs_display_cfg = {
 651         .name = "qhs_display_cfg",
 652         .id = QCS615_SLAVE_DISPLAY_CFG,
 653         .channels = 1,
 654         .buswidth = 4,
 655         .num_links = 0,
 656 };
 657
 658 static struct qcom_icc_node qhs_emac_avb_cfg = {
 659         .name = "qhs_emac_avb_cfg",
 660         .id = QCS615_SLAVE_EMAC_AVB_CFG,
 661         .channels = 1,
 662         .buswidth = 4,
 663         .num_links = 0,
 664 };
 665
 666 static struct qcom_icc_node qhs_glm = {
 667         .name = "qhs_glm",
 668         .id = QCS615_SLAVE_GLM,
 669         .channels = 1,
 670         .buswidth = 4,
 671         .num_links = 0,
 672 };
 673
 674 static struct qcom_icc_node qhs_gpuss_cfg = {
 675         .name = "qhs_gpuss_cfg",
 676         .id = QCS615_SLAVE_GFX3D_CFG,
 677         .channels = 1,
 678         .buswidth = 8,
 679         .num_links = 0,
 680 };
 681
 682 static struct qcom_icc_node qhs_imem_cfg = {
 683         .name = "qhs_imem_cfg",
 684         .id = QCS615_SLAVE_IMEM_CFG,
 685         .channels = 1,
 686         .buswidth = 4,
 687         .num_links = 0,
 688 };
 689
 690 static struct qcom_icc_node qhs_ipa = {
 691         .name = "qhs_ipa",
 692         .id = QCS615_SLAVE_IPA_CFG,
 693         .channels = 1,
 694         .buswidth = 4,
 695         .num_links = 0,
 696 };
 697
 698 static struct qcom_icc_node qhs_mnoc_cfg = {
 699         .name = "qhs_mnoc_cfg",
 700         .id = QCS615_SLAVE_CNOC_MNOC_CFG,
 701         .channels = 1,
 702         .buswidth = 4,
 703         .num_links = 1,
 704         .links = { QCS615_MASTER_CNOC_MNOC_CFG },
 705 };
 706
 707 static struct qcom_icc_node qhs_pcie_config = {
 708         .name = "qhs_pcie_config",
 709         .id = QCS615_SLAVE_PCIE_CFG,
 710         .channels = 1,
 711         .buswidth = 4,
 712         .num_links = 0,
 713 };
 714
 715 static struct qcom_icc_node qhs_pimem_cfg = {
 716         .name = "qhs_pimem_cfg",
 717         .id = QCS615_SLAVE_PIMEM_CFG,
 718         .channels = 1,
 719         .buswidth = 4,
 720         .num_links = 0,
 721 };
 722
 723 static struct qcom_icc_node qhs_prng = {
 724         .name = "qhs_prng",
 725         .id = QCS615_SLAVE_PRNG,
 726         .channels = 1,
 727         .buswidth = 4,
 728         .num_links = 0,
 729 };
 730
 731 static struct qcom_icc_node qhs_qdss_cfg = {
 732         .name = "qhs_qdss_cfg",
 733         .id = QCS615_SLAVE_QDSS_CFG,
 734         .channels = 1,
 735         .buswidth = 4,
 736         .num_links = 0,
 737 };
 738
 739 static struct qcom_icc_node qhs_qspi = {
 740         .name = "qhs_qspi",
 741         .id = QCS615_SLAVE_QSPI,
 742         .channels = 1,
 743         .buswidth = 4,
 744         .num_links = 0,
 745 };
 746
 747 static struct qcom_icc_node qhs_qup0 = {
 748         .name = "qhs_qup0",
 749         .id = QCS615_SLAVE_QUP_0,
 750         .channels = 1,
 751         .buswidth = 4,
 752         .num_links = 0,
 753 };
 754
 755 static struct qcom_icc_node qhs_qup1 = {
 756         .name = "qhs_qup1",
 757         .id = QCS615_SLAVE_QUP_1,
 758         .channels = 1,
 759         .buswidth = 4,
 760         .num_links = 0,
 761 };
 762
 763 static struct qcom_icc_node qhs_sdc1 = {
 764         .name = "qhs_sdc1",
 765         .id = QCS615_SLAVE_SDCC_1,
 766         .channels = 1,
 767         .buswidth = 4,
 768         .num_links = 0,
 769 };
 770
 771 static struct qcom_icc_node qhs_sdc2 = {
 772         .name = "qhs_sdc2",
 773         .id = QCS615_SLAVE_SDCC_2,
 774         .channels = 1,
 775         .buswidth = 4,
 776         .num_links = 0,
 777 };
 778
 779 static struct qcom_icc_node qhs_snoc_cfg = {
 780         .name = "qhs_snoc_cfg",
 781         .id = QCS615_SLAVE_SNOC_CFG,
 782         .channels = 1,
 783         .buswidth = 4,
 784         .num_links = 1,
 785         .links = { QCS615_MASTER_SNOC_CFG },
 786 };
 787
 788 static struct qcom_icc_node qhs_spdm = {
 789         .name = "qhs_spdm",
 790         .id = QCS615_SLAVE_SPDM_WRAPPER,
 791         .channels = 1,
 792         .buswidth = 4,
 793         .num_links = 0,
 794 };
 795
 796 static struct qcom_icc_node qhs_tcsr = {
 797         .name = "qhs_tcsr",
 798         .id = QCS615_SLAVE_TCSR,
 799         .channels = 1,
 800         .buswidth = 4,
 801         .num_links = 0,
 802 };
 803
 804 static struct qcom_icc_node qhs_tlmm_east = {
 805         .name = "qhs_tlmm_east",
 806         .id = QCS615_SLAVE_TLMM_EAST,
 807         .channels = 1,
 808         .buswidth = 4,
 809         .num_links = 0,
 810 };
 811
 812 static struct qcom_icc_node qhs_tlmm_south = {
 813         .name = "qhs_tlmm_south",
 814         .id = QCS615_SLAVE_TLMM_SOUTH,
 815         .channels = 1,
 816         .buswidth = 4,
 817         .num_links = 0,
 818 };
 819
 820 static struct qcom_icc_node qhs_tlmm_west = {
 821         .name = "qhs_tlmm_west",
 822         .id = QCS615_SLAVE_TLMM_WEST,
 823         .channels = 1,
 824         .buswidth = 4,
 825         .num_links = 0,
 826 };
 827
 828 static struct qcom_icc_node qhs_ufs_mem_cfg = {
 829         .name = "qhs_ufs_mem_cfg",
 830         .id = QCS615_SLAVE_UFS_MEM_CFG,
 831         .channels = 1,
 832         .buswidth = 4,
 833         .num_links = 0,
 834 };
 835
 836 static struct qcom_icc_node qhs_usb2 = {
 837         .name = "qhs_usb2",
 838         .id = QCS615_SLAVE_USB2,
 839         .channels = 1,
 840         .buswidth = 4,
 841         .num_links = 0,
 842 };
 843
 844 static struct qcom_icc_node qhs_usb3 = {
 845         .name = "qhs_usb3",
 846         .id = QCS615_SLAVE_USB3,
 847         .channels = 1,
 848         .buswidth = 4,
 849         .num_links = 0,
 850 };
 851
 852 static struct qcom_icc_node qhs_venus_cfg = {
 853         .name = "qhs_venus_cfg",
 854         .id = QCS615_SLAVE_VENUS_CFG,
 855         .channels = 1,
 856         .buswidth = 4,
 857         .num_links = 0,
 858 };
 859
 860 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
 861         .name = "qhs_vsense_ctrl_cfg",
 862         .id = QCS615_SLAVE_VSENSE_CTRL_CFG,
 863         .channels = 1,
 864         .buswidth = 4,
 865         .num_links = 0,
 866 };
 867
 868 static struct qcom_icc_node qns_cnoc_a2noc = {
 869         .name = "qns_cnoc_a2noc",
 870         .id = QCS615_SLAVE_CNOC_A2NOC,
 871         .channels = 1,
 872         .buswidth = 8,
 873         .num_links = 1,
 874         .links = { QCS615_MASTER_CNOC_A2NOC },
 875 };
 876
 877 static struct qcom_icc_node srvc_cnoc = {
 878         .name = "srvc_cnoc",
 879         .id = QCS615_SLAVE_SERVICE_CNOC,
 880         .channels = 1,
 881         .buswidth = 4,
 882         .num_links = 0,
 883 };
 884
 885 static struct qcom_icc_node qhs_dc_noc_gemnoc = {
 886         .name = "qhs_dc_noc_gemnoc",
 887         .id = QCS615_SLAVE_DC_NOC_GEMNOC,
 888         .channels = 1,
 889         .buswidth = 4,
 890         .num_links = 1,
 891         .links = { QCS615_MASTER_GEM_NOC_CFG },
 892 };
 893
 894 static struct qcom_icc_node qhs_llcc = {
 895         .name = "qhs_llcc",
 896         .id = QCS615_SLAVE_LLCC_CFG,
 897         .channels = 1,
 898         .buswidth = 4,
 899         .num_links = 0,
 900 };
 901
 902 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
 903         .name = "qhs_mdsp_ms_mpu_cfg",
 904         .id = QCS615_SLAVE_MSS_PROC_MS_MPU_CFG,
 905         .channels = 1,
 906         .buswidth = 4,
 907         .num_links = 0,
 908 };
 909
 910 static struct qcom_icc_node qns_gem_noc_snoc = {
 911         .name = "qns_gem_noc_snoc",
 912         .id = QCS615_SLAVE_GEM_NOC_SNOC,
 913         .channels = 1,
 914         .buswidth = 8,
 915         .num_links = 1,
 916         .links = { QCS615_MASTER_GEM_NOC_SNOC },
 917 };
 918
 919 static struct qcom_icc_node qns_llcc = {
 920         .name = "qns_llcc",
 921         .id = QCS615_SLAVE_LLCC,
 922         .channels = 1,
 923         .buswidth = 16,
 924         .num_links = 1,
 925         .links = { QCS615_MASTER_LLCC },
 926 };
 927
 928 static struct qcom_icc_node qns_sys_pcie = {
 929         .name = "qns_sys_pcie",
 930         .id = QCS615_SLAVE_MEM_NOC_PCIE_SNOC,
 931         .channels = 1,
 932         .buswidth = 8,
 933         .num_links = 1,
 934         .links = { QCS615_MASTER_GEM_NOC_PCIE_SNOC },
 935 };
 936
 937 static struct qcom_icc_node srvc_gemnoc = {
 938         .name = "srvc_gemnoc",
 939         .id = QCS615_SLAVE_SERVICE_GEM_NOC,
 940         .channels = 1,
 941         .buswidth = 4,
 942         .num_links = 0,
 943 };
 944
 945 static struct qcom_icc_node ipa_core_slave = {
 946         .name = "ipa_core_slave",
 947         .id = QCS615_SLAVE_IPA_CORE,
 948         .channels = 1,
 949         .buswidth = 8,
 950         .num_links = 0,
 951 };
 952
 953 static struct qcom_icc_node ebi = {
 954         .name = "ebi",
 955         .id = QCS615_SLAVE_EBI1,
 956         .channels = 2,
 957         .buswidth = 4,
 958         .num_links = 0,
 959 };
 960
 961 static struct qcom_icc_node qns2_mem_noc = {
 962         .name = "qns2_mem_noc",
 963         .id = QCS615_SLAVE_MNOC_SF_MEM_NOC,
 964         .channels = 1,
 965         .buswidth = 32,
 966         .num_links = 1,
 967         .links = { QCS615_MASTER_MNOC_SF_MEM_NOC },
 968 };
 969
 970 static struct qcom_icc_node qns_mem_noc_hf = {
 971         .name = "qns_mem_noc_hf",
 972         .id = QCS615_SLAVE_MNOC_HF_MEM_NOC,
 973         .channels = 1,
 974         .buswidth = 32,
 975         .num_links = 1,
 976         .links = { QCS615_MASTER_MNOC_HF_MEM_NOC },
 977 };
 978
 979 static struct qcom_icc_node srvc_mnoc = {
 980         .name = "srvc_mnoc",
 981         .id = QCS615_SLAVE_SERVICE_MNOC,
 982         .channels = 1,
 983         .buswidth = 4,
 984         .num_links = 0,
 985 };
 986
 987 static struct qcom_icc_node qhs_apss = {
 988         .name = "qhs_apss",
 989         .id = QCS615_SLAVE_APPSS,
 990         .channels = 1,
 991         .buswidth = 8,
 992         .num_links = 0,
 993 };
 994
 995 static struct qcom_icc_node qns_cnoc = {
 996         .name = "qns_cnoc",
 997         .id = QCS615_SLAVE_SNOC_CNOC,
 998         .channels = 1,
 999         .buswidth = 8,
1000         .num_links = 1,
1001         .links = { QCS615_MASTER_SNOC_CNOC },
1002 };
1003
1004 static struct qcom_icc_node qns_gemnoc_sf = {
1005         .name = "qns_gemnoc_sf",
1006         .id = QCS615_SLAVE_SNOC_GEM_NOC_SF,
1007         .channels = 1,
1008         .buswidth = 16,
1009         .num_links = 1,
1010         .links = { QCS615_MASTER_SNOC_SF_MEM_NOC },
1011 };
1012
1013 static struct qcom_icc_node qns_memnoc_gc = {
1014         .name = "qns_memnoc_gc",
1015         .id = QCS615_SLAVE_SNOC_MEM_NOC_GC,
1016         .channels = 1,
1017         .buswidth = 8,
1018         .num_links = 1,
1019         .links = { QCS615_MASTER_SNOC_GC_MEM_NOC },
1020 };
1021
1022 static struct qcom_icc_node qxs_imem = {
1023         .name = "qxs_imem",
1024         .id = QCS615_SLAVE_IMEM,
1025         .channels = 1,
1026         .buswidth = 8,
1027         .num_links = 0,
1028 };
1029
1030 static struct qcom_icc_node qxs_pimem = {
1031         .name = "qxs_pimem",
1032         .id = QCS615_SLAVE_PIMEM,
1033         .channels = 1,
1034         .buswidth = 8,
1035         .num_links = 0,
1036 };
1037
1038 static struct qcom_icc_node srvc_snoc = {
1039         .name = "srvc_snoc",
1040         .id = QCS615_SLAVE_SERVICE_SNOC,
1041         .channels = 1,
1042         .buswidth = 4,
1043         .num_links = 0,
1044 };
1045
1046 static struct qcom_icc_node xs_pcie = {
1047         .name = "xs_pcie",
1048         .id = QCS615_SLAVE_PCIE_0,
1049         .channels = 1,
1050         .buswidth = 8,
1051         .num_links = 0,
1052 };
1053
1054 static struct qcom_icc_node xs_qdss_stm = {
1055         .name = "xs_qdss_stm",
1056         .id = QCS615_SLAVE_QDSS_STM,
1057         .channels = 1,
1058         .buswidth = 4,
1059         .num_links = 0,
1060 };
1061
1062 static struct qcom_icc_node xs_sys_tcu_cfg = {
1063         .name = "xs_sys_tcu_cfg",
1064         .id = QCS615_SLAVE_TCU,
1065         .channels = 1,
1066         .buswidth = 8,
1067         .num_links = 0,
1068 };
1069
1070 static struct qcom_icc_bcm bcm_acv = {
1071         .name = "ACV",
1072         .num_nodes = 1,
1073         .nodes = { &ebi },
1074 };
1075
1076 static struct qcom_icc_bcm bcm_ce0 = {
1077         .name = "CE0",
1078         .num_nodes = 1,
1079         .nodes = { &qxm_crypto },
1080 };
1081
1082 static struct qcom_icc_bcm bcm_cn0 = {
1083         .name = "CN0",
1084         .keepalive = true,
1085         .num_nodes = 37,
1086         .nodes = { &qhm_spdm, &qnm_snoc,
1087                    &qhs_a1_noc_cfg, &qhs_aop,
1088                    &qhs_aoss, &qhs_camera_cfg,
1089                    &qhs_clk_ctl, &qhs_cpr_cx,
1090                    &qhs_cpr_mx, &qhs_crypto0_cfg,
1091                    &qhs_ddrss_cfg, &qhs_display_cfg,
1092                    &qhs_emac_avb_cfg, &qhs_glm,
1093                    &qhs_gpuss_cfg, &qhs_imem_cfg,
1094                    &qhs_ipa, &qhs_mnoc_cfg,
1095                    &qhs_pcie_config, &qhs_pimem_cfg,
1096                    &qhs_prng, &qhs_qdss_cfg,
1097                    &qhs_qup0, &qhs_qup1,
1098                    &qhs_snoc_cfg, &qhs_spdm,
1099                    &qhs_tcsr, &qhs_tlmm_east,
1100                    &qhs_tlmm_south, &qhs_tlmm_west,
1101                    &qhs_ufs_mem_cfg, &qhs_usb2,
1102                    &qhs_usb3, &qhs_venus_cfg,
1103                    &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc,
1104                    &srvc_cnoc },
1105 };
1106
1107 static struct qcom_icc_bcm bcm_cn1 = {
1108         .name = "CN1",
1109         .num_nodes = 8,
1110         .nodes = { &qhm_qspi, &xm_sdc1,
1111                    &xm_sdc2, &qhs_ahb2phy_east,
1112                    &qhs_ahb2phy_west, &qhs_qspi,
1113                    &qhs_sdc1, &qhs_sdc2 },
1114 };
1115
1116 static struct qcom_icc_bcm bcm_ip0 = {
1117         .name = "IP0",
1118         .num_nodes = 1,
1119         .nodes = { &ipa_core_slave },
1120 };
1121
1122 static struct qcom_icc_bcm bcm_mc0 = {
1123         .name = "MC0",
1124         .keepalive = true,
1125         .num_nodes = 1,
1126         .nodes = { &ebi },
1127 };
1128
1129 static struct qcom_icc_bcm bcm_mm0 = {
1130         .name = "MM0",
1131         .keepalive = true,
1132         .num_nodes = 1,
1133         .nodes = { &qns_mem_noc_hf },
1134 };
1135
1136 static struct qcom_icc_bcm bcm_mm1 = {
1137         .name = "MM1",
1138         .num_nodes = 7,
1139         .nodes = { &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp,
1140                    &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0,
1141                    &qxm_camnoc_hf1, &qxm_mdp0,
1142                    &qxm_rot },
1143 };
1144
1145 static struct qcom_icc_bcm bcm_mm2 = {
1146         .name = "MM2",
1147         .num_nodes = 2,
1148         .nodes = { &qxm_camnoc_sf, &qns2_mem_noc },
1149 };
1150
1151 static struct qcom_icc_bcm bcm_mm3 = {
1152         .name = "MM3",
1153         .num_nodes = 2,
1154         .nodes = { &qxm_venus0, &qxm_venus_arm9 },
1155 };
1156
1157 static struct qcom_icc_bcm bcm_qup0 = {
1158         .name = "QUP0",
1159         .keepalive = true,
1160         .vote_scale = 1,
1161         .num_nodes = 2,
1162         .nodes = { &qhm_qup0, &qhm_qup1 },
1163 };
1164
1165 static struct qcom_icc_bcm bcm_sh0 = {
1166         .name = "SH0",
1167         .keepalive = true,
1168         .num_nodes = 1,
1169         .nodes = { &qns_llcc },
1170 };
1171
1172 static struct qcom_icc_bcm bcm_sh2 = {
1173         .name = "SH2",
1174         .num_nodes = 1,
1175         .nodes = { &acm_apps },
1176 };
1177
1178 static struct qcom_icc_bcm bcm_sh3 = {
1179         .name = "SH3",
1180         .num_nodes = 1,
1181         .nodes = { &qns_gem_noc_snoc },
1182 };
1183
1184 static struct qcom_icc_bcm bcm_sn0 = {
1185         .name = "SN0",
1186         .keepalive = true,
1187         .num_nodes = 1,
1188         .nodes = { &qns_gemnoc_sf },
1189 };
1190
1191 static struct qcom_icc_bcm bcm_sn1 = {
1192         .name = "SN1",
1193         .num_nodes = 1,
1194         .nodes = { &qxs_imem },
1195 };
1196
1197 static struct qcom_icc_bcm bcm_sn2 = {
1198         .name = "SN2",
1199         .num_nodes = 1,
1200         .nodes = { &qns_memnoc_gc },
1201 };
1202
1203 static struct qcom_icc_bcm bcm_sn3 = {
1204         .name = "SN3",
1205         .num_nodes = 2,
1206         .nodes = { &srvc_aggre2_noc, &qns_cnoc },
1207 };
1208
1209 static struct qcom_icc_bcm bcm_sn4 = {
1210         .name = "SN4",
1211         .num_nodes = 1,
1212         .nodes = { &qxs_pimem },
1213 };
1214
1215 static struct qcom_icc_bcm bcm_sn5 = {
1216         .name = "SN5",
1217         .num_nodes = 1,
1218         .nodes = { &xs_qdss_stm },
1219 };
1220
1221 static struct qcom_icc_bcm bcm_sn8 = {
1222         .name = "SN8",
1223         .num_nodes = 2,
1224         .nodes = { &qnm_gemnoc_pcie, &xs_pcie },
1225 };
1226
1227 static struct qcom_icc_bcm bcm_sn9 = {
1228         .name = "SN9",
1229         .num_nodes = 1,
1230         .nodes = { &qnm_aggre1_noc },
1231 };
1232
1233 static struct qcom_icc_bcm bcm_sn12 = {
1234         .name = "SN12",
1235         .num_nodes = 2,
1236         .nodes = { &qxm_pimem, &xm_gic },
1237 };
1238
1239 static struct qcom_icc_bcm bcm_sn13 = {
1240         .name = "SN13",
1241         .num_nodes = 1,
1242         .nodes = { &qnm_lpass_anoc },
1243 };
1244
1245 static struct qcom_icc_bcm bcm_sn14 = {
1246         .name = "SN14",
1247         .num_nodes = 1,
1248         .nodes = { &qns_pcie_snoc },
1249 };
1250
1251 static struct qcom_icc_bcm bcm_sn15 = {
1252         .name = "SN15",
1253         .num_nodes = 1,
1254         .nodes = { &qnm_gemnoc },
1255 };
1256
1257 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1258         &bcm_ce0,
1259         &bcm_cn1,
1260         &bcm_qup0,
1261         &bcm_sn3,
1262         &bcm_sn14,
1263         &bcm_ip0,
1264 };
1265
1266 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1267         [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
1268         [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1269         [MASTER_QSPI] = &qhm_qspi,
1270         [MASTER_QUP_0] = &qhm_qup0,
1271         [MASTER_BLSP_1] = &qhm_qup1,
1272         [MASTER_CNOC_A2NOC] = &qnm_cnoc,
1273         [MASTER_CRYPTO] = &qxm_crypto,
1274         [MASTER_IPA] = &qxm_ipa,
1275         [MASTER_EMAC_EVB] = &xm_emac_avb,
1276         [MASTER_PCIE] = &xm_pcie,
1277         [MASTER_QDSS_ETR] = &xm_qdss_etr,
1278         [MASTER_SDCC_1] = &xm_sdc1,
1279         [MASTER_SDCC_2] = &xm_sdc2,
1280         [MASTER_UFS_MEM] = &xm_ufs_mem,
1281         [MASTER_USB2] = &xm_usb2,
1282         [MASTER_USB3_0] = &xm_usb3_0,
1283         [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1284         [SLAVE_LPASS_SNOC] = &qns_lpass_snoc,
1285         [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc,
1286         [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1287 };
1288
1289 static const struct qcom_icc_desc qcs615_aggre1_noc = {
1290         .nodes = aggre1_noc_nodes,
1291         .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1292         .bcms = aggre1_noc_bcms,
1293         .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1294 };
1295
1296 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
1297         &bcm_mm1,
1298 };
1299
1300 static struct qcom_icc_node * const camnoc_virt_nodes[] = {
1301         [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
1302         [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
1303         [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
1304         [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
1305 };
1306
1307 static const struct qcom_icc_desc qcs615_camnoc_virt = {
1308         .nodes = camnoc_virt_nodes,
1309         .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
1310         .bcms = camnoc_virt_bcms,
1311         .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
1312 };
1313
1314 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1315         &bcm_cn0,
1316         &bcm_cn1,
1317 };
1318
1319 static struct qcom_icc_node * const config_noc_nodes[] = {
1320         [MASTER_SPDM] = &qhm_spdm,
1321         [MASTER_SNOC_CNOC] = &qnm_snoc,
1322         [MASTER_QDSS_DAP] = &xm_qdss_dap,
1323         [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
1324         [SLAVE_AHB2PHY_EAST] = &qhs_ahb2phy_east,
1325         [SLAVE_AHB2PHY_WEST] = &qhs_ahb2phy_west,
1326         [SLAVE_AOP] = &qhs_aop,
1327         [SLAVE_AOSS] = &qhs_aoss,
1328         [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1329         [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1330         [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1331         [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1332         [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1333         [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
1334         [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1335         [SLAVE_EMAC_AVB_CFG] = &qhs_emac_avb_cfg,
1336         [SLAVE_GLM] = &qhs_glm,
1337         [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1338         [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1339         [SLAVE_IPA_CFG] = &qhs_ipa,
1340         [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
1341         [SLAVE_PCIE_CFG] = &qhs_pcie_config,
1342         [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1343         [SLAVE_PRNG] = &qhs_prng,
1344         [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1345         [SLAVE_QSPI] = &qhs_qspi,
1346         [SLAVE_QUP_0] = &qhs_qup0,
1347         [SLAVE_QUP_1] = &qhs_qup1,
1348         [SLAVE_SDCC_1] = &qhs_sdc1,
1349         [SLAVE_SDCC_2] = &qhs_sdc2,
1350         [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
1351         [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
1352         [SLAVE_TCSR] = &qhs_tcsr,
1353         [SLAVE_TLMM_EAST] = &qhs_tlmm_east,
1354         [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
1355         [SLAVE_TLMM_WEST] = &qhs_tlmm_west,
1356         [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1357         [SLAVE_USB2] = &qhs_usb2,
1358         [SLAVE_USB3] = &qhs_usb3,
1359         [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1360         [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1361         [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
1362         [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1363 };
1364
1365 static const struct qcom_icc_desc qcs615_config_noc = {
1366         .nodes = config_noc_nodes,
1367         .num_nodes = ARRAY_SIZE(config_noc_nodes),
1368         .bcms = config_noc_bcms,
1369         .num_bcms = ARRAY_SIZE(config_noc_bcms),
1370 };
1371
1372 static struct qcom_icc_node * const dc_noc_nodes[] = {
1373         [MASTER_CNOC_DC_NOC] = &qhm_cnoc,
1374         [SLAVE_DC_NOC_GEMNOC] = &qhs_dc_noc_gemnoc,
1375         [SLAVE_LLCC_CFG] = &qhs_llcc,
1376 };
1377
1378 static const struct qcom_icc_desc qcs615_dc_noc = {
1379         .nodes = dc_noc_nodes,
1380         .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1381 };
1382
1383 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1384         &bcm_sh0,
1385         &bcm_sh2,
1386         &bcm_sh3,
1387         &bcm_mm1,
1388 };
1389
1390 static struct qcom_icc_node * const gem_noc_nodes[] = {
1391         [MASTER_APPSS_PROC] = &acm_apps,
1392         [MASTER_GPU_TCU] = &acm_gpu_tcu,
1393         [MASTER_SYS_TCU] = &acm_sys_tcu,
1394         [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
1395         [MASTER_GFX3D] = &qnm_gpu,
1396         [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1397         [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1398         [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1399         [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1400         [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1401         [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
1402         [SLAVE_LLCC] = &qns_llcc,
1403         [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
1404         [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
1405 };
1406
1407 static const struct qcom_icc_desc qcs615_gem_noc = {
1408         .nodes = gem_noc_nodes,
1409         .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1410         .bcms = gem_noc_bcms,
1411         .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1412 };
1413
1414 static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
1415         &bcm_ip0,
1416 };
1417
1418 static struct qcom_icc_node * const ipa_virt_nodes[] = {
1419         [MASTER_IPA_CORE] = &ipa_core_master,
1420         [SLAVE_IPA_CORE] = &ipa_core_slave,
1421 };
1422
1423 static const struct qcom_icc_desc qcs615_ipa_virt = {
1424         .nodes = ipa_virt_nodes,
1425         .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
1426         .bcms = ipa_virt_bcms,
1427         .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
1428 };
1429
1430 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1431         &bcm_acv,
1432         &bcm_mc0,
1433 };
1434
1435 static struct qcom_icc_node * const mc_virt_nodes[] = {
1436         [MASTER_LLCC] = &llcc_mc,
1437         [SLAVE_EBI1] = &ebi,
1438 };
1439
1440 static const struct qcom_icc_desc qcs615_mc_virt = {
1441         .nodes = mc_virt_nodes,
1442         .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1443         .bcms = mc_virt_bcms,
1444         .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1445 };
1446
1447 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1448         &bcm_mm0,
1449         &bcm_mm1,
1450         &bcm_mm2,
1451         &bcm_mm3,
1452 };
1453
1454 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1455         [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
1456         [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
1457         [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
1458         [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1459         [MASTER_MDP0] = &qxm_mdp0,
1460         [MASTER_ROTATOR] = &qxm_rot,
1461         [MASTER_VIDEO_P0] = &qxm_venus0,
1462         [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
1463         [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
1464         [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1465         [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1466 };
1467
1468 static const struct qcom_icc_desc qcs615_mmss_noc = {
1469         .nodes = mmss_noc_nodes,
1470         .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1471         .bcms = mmss_noc_bcms,
1472         .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1473 };
1474
1475 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1476         &bcm_sn0,
1477         &bcm_sn1,
1478         &bcm_sn2,
1479         &bcm_sn3,
1480         &bcm_sn4,
1481         &bcm_sn5,
1482         &bcm_sn8,
1483         &bcm_sn9,
1484         &bcm_sn12,
1485         &bcm_sn13,
1486         &bcm_sn15,
1487 };
1488
1489 static struct qcom_icc_node * const system_noc_nodes[] = {
1490         [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1491         [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1492         [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
1493         [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1494         [MASTER_LPASS_ANOC] = &qnm_lpass_anoc,
1495         [MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc,
1496         [MASTER_PIMEM] = &qxm_pimem,
1497         [MASTER_GIC] = &xm_gic,
1498         [SLAVE_APPSS] = &qhs_apss,
1499         [SLAVE_SNOC_CNOC] = &qns_cnoc,
1500         [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1501         [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc,
1502         [SLAVE_IMEM] = &qxs_imem,
1503         [SLAVE_PIMEM] = &qxs_pimem,
1504         [SLAVE_SERVICE_SNOC] = &srvc_snoc,
1505         [SLAVE_PCIE_0] = &xs_pcie,
1506         [SLAVE_QDSS_STM] = &xs_qdss_stm,
1507         [SLAVE_TCU] = &xs_sys_tcu_cfg,
1508 };
1509
1510 static const struct qcom_icc_desc qcs615_system_noc = {
1511         .nodes = system_noc_nodes,
1512         .num_nodes = ARRAY_SIZE(system_noc_nodes),
1513         .bcms = system_noc_bcms,
1514         .num_bcms = ARRAY_SIZE(system_noc_bcms),
1515 };
1516
1517 static const struct of_device_id qnoc_of_match[] = {
1518         { .compatible = "qcom,qcs615-aggre1-noc",
1519           .data = &qcs615_aggre1_noc},
1520         { .compatible = "qcom,qcs615-camnoc-virt",
1521           .data = &qcs615_camnoc_virt},
1522         { .compatible = "qcom,qcs615-config-noc",
1523           .data = &qcs615_config_noc},
1524         { .compatible = "qcom,qcs615-dc-noc",
1525           .data = &qcs615_dc_noc},
1526         { .compatible = "qcom,qcs615-gem-noc",
1527           .data = &qcs615_gem_noc},
1528         { .compatible = "qcom,qcs615-ipa-virt",
1529           .data = &qcs615_ipa_virt},
1530         { .compatible = "qcom,qcs615-mc-virt",
1531           .data = &qcs615_mc_virt},
1532         { .compatible = "qcom,qcs615-mmss-noc",
1533           .data = &qcs615_mmss_noc},
1534         { .compatible = "qcom,qcs615-system-noc",
1535           .data = &qcs615_system_noc},
1536         { }
1537 };
1538 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1539
1540 static struct platform_driver qnoc_driver = {
1541         .probe = qcom_icc_rpmh_probe,
1542         .remove = qcom_icc_rpmh_remove,
1543         .driver = {
1544                 .name = "qnoc-qcs615",
1545                 .of_match_table = qnoc_of_match,
1546                 .sync_state = icc_sync_state,
1547         },
1548 };
1549
1550 static int __init qnoc_driver_init(void)
1551 {
1552         return platform_driver_register(&qnoc_driver);
1553 }
1554 core_initcall(qnoc_driver_init);
1555
1556 static void __exit qnoc_driver_exit(void)
1557 {
1558         platform_driver_unregister(&qnoc_driver);
1559 }
1560 module_exit(qnoc_driver_exit);
1561
1562 MODULE_DESCRIPTION("qcs615 NoC driver");
1563 MODULE_LICENSE("GPL");