1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <dt-bindings/interconnect/qcom,sm7150-rpmh.h>
15 #include "bcm-voter.h"
19 static struct qcom_icc_node qhm_a1noc_cfg
= {
20 .name
= "qhm-a1noc-cfg",
21 .id
= SM7150_MASTER_A1NOC_CFG
,
25 .links
= { SM7150_SLAVE_SERVICE_A1NOC
},
28 static struct qcom_icc_node qhm_qup_center
= {
29 .name
= "qhm_qup_center",
30 .id
= SM7150_MASTER_QUP_0
,
34 .links
= { SM7150_A1NOC_SNOC_SLV
},
37 static struct qcom_icc_node qhm_tsif
= {
39 .id
= SM7150_MASTER_TSIF
,
43 .links
= { SM7150_A1NOC_SNOC_SLV
},
46 static struct qcom_icc_node xm_emmc
= {
48 .id
= SM7150_MASTER_EMMC
,
52 .links
= { SM7150_A1NOC_SNOC_SLV
},
55 static struct qcom_icc_node xm_sdc2
= {
57 .id
= SM7150_MASTER_SDCC_2
,
61 .links
= { SM7150_A1NOC_SNOC_SLV
},
64 static struct qcom_icc_node xm_sdc4
= {
66 .id
= SM7150_MASTER_SDCC_4
,
70 .links
= { SM7150_A1NOC_SNOC_SLV
},
73 static struct qcom_icc_node xm_ufs_mem
= {
75 .id
= SM7150_MASTER_UFS_MEM
,
79 .links
= { SM7150_A1NOC_SNOC_SLV
},
82 static struct qcom_icc_node qhm_a2noc_cfg
= {
83 .name
= "qhm_a2noc_cfg",
84 .id
= SM7150_MASTER_A2NOC_CFG
,
88 .links
= { SM7150_SLAVE_SERVICE_A2NOC
},
91 static struct qcom_icc_node qhm_qdss_bam
= {
92 .name
= "qhm_qdss_bam",
93 .id
= SM7150_MASTER_QDSS_BAM
,
97 .links
= { SM7150_A2NOC_SNOC_SLV
},
100 static struct qcom_icc_node qhm_qup_north
= {
101 .name
= "qhm_qup_north",
102 .id
= SM7150_MASTER_QUP_1
,
106 .links
= { SM7150_A2NOC_SNOC_SLV
},
109 static struct qcom_icc_node qnm_cnoc
= {
111 .id
= SM7150_MASTER_CNOC_A2NOC
,
115 .links
= { SM7150_A2NOC_SNOC_SLV
},
118 static struct qcom_icc_node qxm_crypto
= {
119 .name
= "qxm_crypto",
120 .id
= SM7150_MASTER_CRYPTO_CORE_0
,
124 .links
= { SM7150_A2NOC_SNOC_SLV
},
127 static struct qcom_icc_node qxm_ipa
= {
129 .id
= SM7150_MASTER_IPA
,
133 .links
= { SM7150_A2NOC_SNOC_SLV
},
136 static struct qcom_icc_node xm_pcie3_0
= {
137 .name
= "xm_pcie3_0",
138 .id
= SM7150_MASTER_PCIE
,
142 .links
= { SM7150_SLAVE_ANOC_PCIE_GEM_NOC
},
145 static struct qcom_icc_node xm_qdss_etr
= {
146 .name
= "xm_qdss_etr",
147 .id
= SM7150_MASTER_QDSS_ETR
,
151 .links
= { SM7150_A2NOC_SNOC_SLV
},
154 static struct qcom_icc_node xm_usb3_0
= {
156 .id
= SM7150_MASTER_USB3
,
160 .links
= { SM7150_A2NOC_SNOC_SLV
},
163 static struct qcom_icc_node qxm_camnoc_hf0_uncomp
= {
164 .name
= "qxm_camnoc_hf0_uncomp",
165 .id
= SM7150_MASTER_CAMNOC_HF0_UNCOMP
,
169 .links
= { SM7150_SLAVE_CAMNOC_UNCOMP
},
172 static struct qcom_icc_node qxm_camnoc_rt_uncomp
= {
173 .name
= "qxm_camnoc_rt_uncomp",
174 .id
= SM7150_MASTER_CAMNOC_RT_UNCOMP
,
178 .links
= { SM7150_SLAVE_CAMNOC_UNCOMP
},
181 static struct qcom_icc_node qxm_camnoc_sf_uncomp
= {
182 .name
= "qxm_camnoc_sf_uncomp",
183 .id
= SM7150_MASTER_CAMNOC_SF_UNCOMP
,
187 .links
= { SM7150_SLAVE_CAMNOC_UNCOMP
},
190 static struct qcom_icc_node qxm_camnoc_nrt_uncomp
= {
191 .name
= "qxm_camnoc_nrt_uncomp",
192 .id
= SM7150_MASTER_CAMNOC_NRT_UNCOMP
,
196 .links
= { SM7150_SLAVE_CAMNOC_UNCOMP
},
199 static struct qcom_icc_node qnm_npu
= {
201 .id
= SM7150_MASTER_NPU
,
205 .links
= { SM7150_SLAVE_CDSP_GEM_NOC
},
208 static struct qcom_icc_node qhm_spdm
= {
210 .id
= SM7150_MASTER_SPDM
,
214 .links
= { SM7150_SLAVE_CNOC_A2NOC
},
217 static struct qcom_icc_node qnm_snoc
= {
219 .id
= SM7150_SNOC_CNOC_MAS
,
223 .links
= { SM7150_SLAVE_TLMM_SOUTH
,
224 SM7150_SLAVE_CAMERA_CFG
,
227 SM7150_SLAVE_CNOC_MNOC_CFG
,
228 SM7150_SLAVE_UFS_MEM_CFG
,
232 SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG
,
233 SM7150_SLAVE_A2NOC_CFG
,
234 SM7150_SLAVE_QDSS_CFG
,
235 SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG
,
236 SM7150_SLAVE_DISPLAY_CFG
,
237 SM7150_SLAVE_PCIE_CFG
,
238 SM7150_SLAVE_DISPLAY_THROTTLE_CFG
,
240 SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG
,
241 SM7150_SLAVE_CNOC_DDRSS
,
242 SM7150_SLAVE_AHB2PHY_NORTH
,
243 SM7150_SLAVE_SNOC_CFG
,
244 SM7150_SLAVE_GRAPHICS_3D_CFG
,
245 SM7150_SLAVE_VENUS_CFG
,
247 SM7150_SLAVE_CDSP_CFG
,
248 SM7150_SLAVE_CLK_CTL
,
251 SM7150_SLAVE_AHB2PHY_SOUTH
,
252 SM7150_SLAVE_SERVICE_CNOC
,
253 SM7150_SLAVE_AHB2PHY_WEST
,
255 SM7150_SLAVE_VENUS_THROTTLE_CFG
,
256 SM7150_SLAVE_IPA_CFG
,
257 SM7150_SLAVE_RBCPR_CX_CFG
,
258 SM7150_SLAVE_TLMM_WEST
,
259 SM7150_SLAVE_A1NOC_CFG
,
262 SM7150_SLAVE_VSENSE_CTRL_CFG
,
263 SM7150_SLAVE_EMMC_CFG
,
264 SM7150_SLAVE_SPDM_WRAPPER
,
265 SM7150_SLAVE_CRYPTO_0_CFG
,
266 SM7150_SLAVE_PIMEM_CFG
,
267 SM7150_SLAVE_TLMM_NORTH
,
268 SM7150_SLAVE_RBCPR_MX_CFG
,
269 SM7150_SLAVE_IMEM_CFG
273 static struct qcom_icc_node xm_qdss_dap
= {
274 .name
= "xm_qdss_dap",
275 .id
= SM7150_MASTER_QDSS_DAP
,
279 .links
= { SM7150_SLAVE_TLMM_SOUTH
,
280 SM7150_SLAVE_CAMERA_CFG
,
283 SM7150_SLAVE_CNOC_MNOC_CFG
,
284 SM7150_SLAVE_UFS_MEM_CFG
,
288 SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG
,
289 SM7150_SLAVE_A2NOC_CFG
,
290 SM7150_SLAVE_QDSS_CFG
,
291 SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG
,
292 SM7150_SLAVE_DISPLAY_CFG
,
293 SM7150_SLAVE_PCIE_CFG
,
294 SM7150_SLAVE_DISPLAY_THROTTLE_CFG
,
296 SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG
,
297 SM7150_SLAVE_CNOC_DDRSS
,
298 SM7150_SLAVE_CNOC_A2NOC
,
299 SM7150_SLAVE_AHB2PHY_NORTH
,
300 SM7150_SLAVE_SNOC_CFG
,
301 SM7150_SLAVE_GRAPHICS_3D_CFG
,
302 SM7150_SLAVE_VENUS_CFG
,
304 SM7150_SLAVE_CDSP_CFG
,
305 SM7150_SLAVE_CLK_CTL
,
308 SM7150_SLAVE_AHB2PHY_SOUTH
,
309 SM7150_SLAVE_SERVICE_CNOC
,
310 SM7150_SLAVE_AHB2PHY_WEST
,
312 SM7150_SLAVE_VENUS_THROTTLE_CFG
,
313 SM7150_SLAVE_IPA_CFG
,
314 SM7150_SLAVE_RBCPR_CX_CFG
,
315 SM7150_SLAVE_TLMM_WEST
,
316 SM7150_SLAVE_A1NOC_CFG
,
319 SM7150_SLAVE_VSENSE_CTRL_CFG
,
320 SM7150_SLAVE_EMMC_CFG
,
321 SM7150_SLAVE_SPDM_WRAPPER
,
322 SM7150_SLAVE_CRYPTO_0_CFG
,
323 SM7150_SLAVE_PIMEM_CFG
,
324 SM7150_SLAVE_TLMM_NORTH
,
325 SM7150_SLAVE_RBCPR_MX_CFG
,
326 SM7150_SLAVE_IMEM_CFG
330 static struct qcom_icc_node qhm_cnoc_dc_noc
= {
331 .name
= "qhm_cnoc_dc_noc",
332 .id
= SM7150_MASTER_CNOC_DC_NOC
,
336 .links
= { SM7150_SLAVE_LLCC_CFG
,
337 SM7150_SLAVE_GEM_NOC_CFG
341 static struct qcom_icc_node acm_apps
= {
343 .id
= SM7150_MASTER_AMPSS_M0
,
347 .links
= { SM7150_SLAVE_LLCC
,
348 SM7150_SLAVE_GEM_NOC_SNOC
352 static struct qcom_icc_node acm_sys_tcu
= {
353 .name
= "acm_sys_tcu",
354 .id
= SM7150_MASTER_SYS_TCU
,
358 .links
= { SM7150_SLAVE_LLCC
,
359 SM7150_SLAVE_GEM_NOC_SNOC
363 static struct qcom_icc_node qhm_gemnoc_cfg
= {
364 .name
= "qhm_gemnoc_cfg",
365 .id
= SM7150_MASTER_GEM_NOC_CFG
,
369 .links
= { SM7150_SLAVE_SERVICE_GEM_NOC
,
370 SM7150_SLAVE_MSS_PROC_MS_MPU_CFG
374 static struct qcom_icc_node qnm_cmpnoc
= {
375 .name
= "qnm_cmpnoc",
376 .id
= SM7150_MASTER_COMPUTE_NOC
,
380 .links
= { SM7150_SLAVE_LLCC
,
381 SM7150_SLAVE_GEM_NOC_SNOC
385 static struct qcom_icc_node qnm_mnoc_hf
= {
386 .name
= "qnm_mnoc_hf",
387 .id
= SM7150_MASTER_MNOC_HF_MEM_NOC
,
391 .links
= { SM7150_SLAVE_LLCC
},
394 static struct qcom_icc_node qnm_mnoc_sf
= {
395 .name
= "qnm_mnoc_sf",
396 .id
= SM7150_MASTER_MNOC_SF_MEM_NOC
,
400 .links
= { SM7150_SLAVE_LLCC
,
401 SM7150_SLAVE_GEM_NOC_SNOC
405 static struct qcom_icc_node qnm_pcie
= {
407 .id
= SM7150_MASTER_GEM_NOC_PCIE_SNOC
,
411 .links
= { SM7150_SLAVE_LLCC
,
412 SM7150_SLAVE_GEM_NOC_SNOC
416 static struct qcom_icc_node qnm_snoc_gc
= {
417 .name
= "qnm_snoc_gc",
418 .id
= SM7150_MASTER_SNOC_GC_MEM_NOC
,
422 .links
= { SM7150_SLAVE_LLCC
},
425 static struct qcom_icc_node qnm_snoc_sf
= {
426 .name
= "qnm_snoc_sf",
427 .id
= SM7150_MASTER_SNOC_SF_MEM_NOC
,
431 .links
= { SM7150_SLAVE_LLCC
},
434 static struct qcom_icc_node qxm_gpu
= {
436 .id
= SM7150_MASTER_GRAPHICS_3D
,
440 .links
= { SM7150_SLAVE_LLCC
,
441 SM7150_SLAVE_GEM_NOC_SNOC
445 static struct qcom_icc_node llcc_mc
= {
447 .id
= SM7150_MASTER_LLCC
,
451 .links
= { SM7150_SLAVE_EBI_CH0
},
454 static struct qcom_icc_node qhm_mnoc_cfg
= {
455 .name
= "qhm_mnoc_cfg",
456 .id
= SM7150_MASTER_CNOC_MNOC_CFG
,
460 .links
= { SM7150_SLAVE_SERVICE_MNOC
},
463 static struct qcom_icc_node qxm_camnoc_hf
= {
464 .name
= "qxm_camnoc_hf",
465 .id
= SM7150_MASTER_CAMNOC_HF0
,
469 .links
= { SM7150_SLAVE_MNOC_HF_MEM_NOC
},
472 static struct qcom_icc_node qxm_camnoc_nrt
= {
473 .name
= "qxm_camnoc_nrt",
474 .id
= SM7150_MASTER_CAMNOC_NRT
,
478 .links
= { SM7150_SLAVE_MNOC_SF_MEM_NOC
},
481 static struct qcom_icc_node qxm_camnoc_rt
= {
482 .name
= "qxm_camnoc_rt",
483 .id
= SM7150_MASTER_CAMNOC_RT
,
487 .links
= { SM7150_SLAVE_MNOC_HF_MEM_NOC
},
490 static struct qcom_icc_node qxm_camnoc_sf
= {
491 .name
= "qxm_camnoc_sf",
492 .id
= SM7150_MASTER_CAMNOC_SF
,
496 .links
= { SM7150_SLAVE_MNOC_SF_MEM_NOC
},
499 static struct qcom_icc_node qxm_mdp0
= {
501 .id
= SM7150_MASTER_MDP_PORT0
,
505 .links
= { SM7150_SLAVE_MNOC_HF_MEM_NOC
},
508 static struct qcom_icc_node qxm_mdp1
= {
510 .id
= SM7150_MASTER_MDP_PORT1
,
514 .links
= { SM7150_SLAVE_MNOC_HF_MEM_NOC
},
517 static struct qcom_icc_node qxm_rot
= {
519 .id
= SM7150_MASTER_ROTATOR
,
523 .links
= { SM7150_SLAVE_MNOC_SF_MEM_NOC
},
526 static struct qcom_icc_node qxm_venus0
= {
527 .name
= "qxm_venus0",
528 .id
= SM7150_MASTER_VIDEO_P0
,
532 .links
= { SM7150_SLAVE_MNOC_SF_MEM_NOC
},
535 static struct qcom_icc_node qxm_venus1
= {
536 .name
= "qxm_venus1",
537 .id
= SM7150_MASTER_VIDEO_P1
,
541 .links
= { SM7150_SLAVE_MNOC_SF_MEM_NOC
},
544 static struct qcom_icc_node qxm_venus_arm9
= {
545 .name
= "qxm_venus_arm9",
546 .id
= SM7150_MASTER_VIDEO_PROC
,
550 .links
= { SM7150_SLAVE_MNOC_SF_MEM_NOC
},
553 static struct qcom_icc_node qhm_snoc_cfg
= {
554 .name
= "qhm_snoc_cfg",
555 .id
= SM7150_MASTER_SNOC_CFG
,
559 .links
= { SM7150_SLAVE_SERVICE_SNOC
},
562 static struct qcom_icc_node qnm_aggre1_noc
= {
563 .name
= "qnm_aggre1_noc",
564 .id
= SM7150_A1NOC_SNOC_MAS
,
568 .links
= { SM7150_SLAVE_SNOC_GEM_NOC_SF
,
572 SM7150_SNOC_CNOC_SLV
,
573 SM7150_SLAVE_QDSS_STM
577 static struct qcom_icc_node qnm_aggre2_noc
= {
578 .name
= "qnm_aggre2_noc",
579 .id
= SM7150_A2NOC_SNOC_MAS
,
583 .links
= { SM7150_SLAVE_SNOC_GEM_NOC_SF
,
587 SM7150_SNOC_CNOC_SLV
,
589 SM7150_SLAVE_QDSS_STM
593 static struct qcom_icc_node qnm_gemnoc
= {
594 .name
= "qnm_gemnoc",
595 .id
= SM7150_MASTER_GEM_NOC_SNOC
,
599 .links
= { SM7150_SLAVE_PIMEM
,
602 SM7150_SNOC_CNOC_SLV
,
604 SM7150_SLAVE_QDSS_STM
608 static struct qcom_icc_node qxm_pimem
= {
610 .id
= SM7150_MASTER_PIMEM
,
614 .links
= { SM7150_SLAVE_SNOC_GEM_NOC_GC
,
619 static struct qcom_icc_node xm_gic
= {
621 .id
= SM7150_MASTER_GIC
,
625 .links
= { SM7150_SLAVE_SNOC_GEM_NOC_GC
,
630 static struct qcom_icc_node qns_a1noc_snoc
= {
631 .name
= "qns_a1noc_snoc",
632 .id
= SM7150_A1NOC_SNOC_SLV
,
636 .links
= { SM7150_A1NOC_SNOC_MAS
},
639 static struct qcom_icc_node srvc_aggre1_noc
= {
640 .name
= "srvc_aggre1_noc",
641 .id
= SM7150_SLAVE_SERVICE_A1NOC
,
646 static struct qcom_icc_node qns_a2noc_snoc
= {
647 .name
= "qns_a2noc_snoc",
648 .id
= SM7150_A2NOC_SNOC_SLV
,
652 .links
= { SM7150_A2NOC_SNOC_MAS
},
655 static struct qcom_icc_node qns_pcie_gemnoc
= {
656 .name
= "qns_pcie_gemnoc",
657 .id
= SM7150_SLAVE_ANOC_PCIE_GEM_NOC
,
661 .links
= { SM7150_MASTER_GEM_NOC_PCIE_SNOC
},
664 static struct qcom_icc_node srvc_aggre2_noc
= {
665 .name
= "srvc_aggre2_noc",
666 .id
= SM7150_SLAVE_SERVICE_A2NOC
,
671 static struct qcom_icc_node qns_camnoc_uncomp
= {
672 .name
= "qns_camnoc_uncomp",
673 .id
= SM7150_SLAVE_CAMNOC_UNCOMP
,
678 static struct qcom_icc_node qns_cdsp_gemnoc
= {
679 .name
= "qns_cdsp_gemnoc",
680 .id
= SM7150_SLAVE_CDSP_GEM_NOC
,
684 .links
= { SM7150_MASTER_COMPUTE_NOC
},
687 static struct qcom_icc_node qhs_a1_noc_cfg
= {
688 .name
= "qhs_a1_noc_cfg",
689 .id
= SM7150_SLAVE_A1NOC_CFG
,
693 .links
= { SM7150_MASTER_A1NOC_CFG
},
696 static struct qcom_icc_node qhs_a2_noc_cfg
= {
697 .name
= "qhs_a2_noc_cfg",
698 .id
= SM7150_SLAVE_A2NOC_CFG
,
702 .links
= { SM7150_MASTER_A2NOC_CFG
},
705 static struct qcom_icc_node qhs_ahb2phy_north
= {
706 .name
= "qhs_ahb2phy_north",
707 .id
= SM7150_SLAVE_AHB2PHY_NORTH
,
712 static struct qcom_icc_node qhs_ahb2phy_south
= {
713 .name
= "qhs_ahb2phy_south",
714 .id
= SM7150_SLAVE_AHB2PHY_SOUTH
,
719 static struct qcom_icc_node qhs_ahb2phy_west
= {
720 .name
= "qhs_ahb2phy_west",
721 .id
= SM7150_SLAVE_AHB2PHY_WEST
,
726 static struct qcom_icc_node qhs_aop
= {
728 .id
= SM7150_SLAVE_AOP
,
733 static struct qcom_icc_node qhs_aoss
= {
735 .id
= SM7150_SLAVE_AOSS
,
740 static struct qcom_icc_node qhs_camera_cfg
= {
741 .name
= "qhs_camera_cfg",
742 .id
= SM7150_SLAVE_CAMERA_CFG
,
747 static struct qcom_icc_node qhs_camera_nrt_thrott_cfg
= {
748 .name
= "qhs_camera_nrt_thrott_cfg",
749 .id
= SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG
,
754 static struct qcom_icc_node qhs_camera_rt_throttle_cfg
= {
755 .name
= "qhs_camera_rt_throttle_cfg",
756 .id
= SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG
,
761 static struct qcom_icc_node qhs_clk_ctl
= {
762 .name
= "qhs_clk_ctl",
763 .id
= SM7150_SLAVE_CLK_CTL
,
768 static struct qcom_icc_node qhs_compute_dsp_cfg
= {
769 .name
= "qhs_compute_dsp_cfg",
770 .id
= SM7150_SLAVE_CDSP_CFG
,
775 static struct qcom_icc_node qhs_cpr_cx
= {
776 .name
= "qhs_cpr_cx",
777 .id
= SM7150_SLAVE_RBCPR_CX_CFG
,
782 static struct qcom_icc_node qhs_cpr_mx
= {
783 .name
= "qhs_cpr_mx",
784 .id
= SM7150_SLAVE_RBCPR_MX_CFG
,
789 static struct qcom_icc_node qhs_crypto0_cfg
= {
790 .name
= "qhs_crypto0_cfg",
791 .id
= SM7150_SLAVE_CRYPTO_0_CFG
,
796 static struct qcom_icc_node qhs_ddrss_cfg
= {
797 .name
= "qhs_ddrss_cfg",
798 .id
= SM7150_SLAVE_CNOC_DDRSS
,
802 .links
= { SM7150_MASTER_CNOC_DC_NOC
},
805 static struct qcom_icc_node qhs_display_cfg
= {
806 .name
= "qhs_display_cfg",
807 .id
= SM7150_SLAVE_DISPLAY_CFG
,
812 static struct qcom_icc_node qhs_display_throttle_cfg
= {
813 .name
= "qhs_display_throttle_cfg",
814 .id
= SM7150_SLAVE_DISPLAY_THROTTLE_CFG
,
819 static struct qcom_icc_node qhs_emmc_cfg
= {
820 .name
= "qhs_emmc_cfg",
821 .id
= SM7150_SLAVE_EMMC_CFG
,
826 static struct qcom_icc_node qhs_glm
= {
828 .id
= SM7150_SLAVE_GLM
,
833 static struct qcom_icc_node qhs_gpuss_cfg
= {
834 .name
= "qhs_gpuss_cfg",
835 .id
= SM7150_SLAVE_GRAPHICS_3D_CFG
,
840 static struct qcom_icc_node qhs_imem_cfg
= {
841 .name
= "qhs_imem_cfg",
842 .id
= SM7150_SLAVE_IMEM_CFG
,
847 static struct qcom_icc_node qhs_ipa
= {
849 .id
= SM7150_SLAVE_IPA_CFG
,
854 static struct qcom_icc_node qhs_mnoc_cfg
= {
855 .name
= "qhs_mnoc_cfg",
856 .id
= SM7150_SLAVE_CNOC_MNOC_CFG
,
860 .links
= { SM7150_MASTER_CNOC_MNOC_CFG
},
863 static struct qcom_icc_node qhs_pcie_cfg
= {
864 .name
= "qhs_pcie_cfg",
865 .id
= SM7150_SLAVE_PCIE_CFG
,
870 static struct qcom_icc_node qhs_pdm
= {
872 .id
= SM7150_SLAVE_PDM
,
877 static struct qcom_icc_node qhs_pimem_cfg
= {
878 .name
= "qhs_pimem_cfg",
879 .id
= SM7150_SLAVE_PIMEM_CFG
,
884 static struct qcom_icc_node qhs_prng
= {
886 .id
= SM7150_SLAVE_PRNG
,
891 static struct qcom_icc_node qhs_qdss_cfg
= {
892 .name
= "qhs_qdss_cfg",
893 .id
= SM7150_SLAVE_QDSS_CFG
,
898 static struct qcom_icc_node qhs_qupv3_center
= {
899 .name
= "qhs_qupv3_center",
900 .id
= SM7150_SLAVE_QUP_0
,
905 static struct qcom_icc_node qhs_qupv3_north
= {
906 .name
= "qhs_qupv3_north",
907 .id
= SM7150_SLAVE_QUP_1
,
912 static struct qcom_icc_node qhs_sdc2
= {
914 .id
= SM7150_SLAVE_SDCC_2
,
919 static struct qcom_icc_node qhs_sdc4
= {
921 .id
= SM7150_SLAVE_SDCC_4
,
926 static struct qcom_icc_node qhs_snoc_cfg
= {
927 .name
= "qhs_snoc_cfg",
928 .id
= SM7150_SLAVE_SNOC_CFG
,
932 .links
= { SM7150_MASTER_SNOC_CFG
},
935 static struct qcom_icc_node qhs_spdm
= {
937 .id
= SM7150_SLAVE_SPDM_WRAPPER
,
942 static struct qcom_icc_node qhs_tcsr
= {
944 .id
= SM7150_SLAVE_TCSR
,
949 static struct qcom_icc_node qhs_tlmm_north
= {
950 .name
= "qhs_tlmm_north",
951 .id
= SM7150_SLAVE_TLMM_NORTH
,
956 static struct qcom_icc_node qhs_tlmm_south
= {
957 .name
= "qhs_tlmm_south",
958 .id
= SM7150_SLAVE_TLMM_SOUTH
,
963 static struct qcom_icc_node qhs_tlmm_west
= {
964 .name
= "qhs_tlmm_west",
965 .id
= SM7150_SLAVE_TLMM_WEST
,
970 static struct qcom_icc_node qhs_tsif
= {
972 .id
= SM7150_SLAVE_TSIF
,
977 static struct qcom_icc_node qhs_ufs_mem_cfg
= {
978 .name
= "qhs_ufs_mem_cfg",
979 .id
= SM7150_SLAVE_UFS_MEM_CFG
,
984 static struct qcom_icc_node qhs_usb3_0
= {
985 .name
= "qhs_usb3_0",
986 .id
= SM7150_SLAVE_USB3
,
991 static struct qcom_icc_node qhs_venus_cfg
= {
992 .name
= "qhs_venus_cfg",
993 .id
= SM7150_SLAVE_VENUS_CFG
,
998 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg
= {
999 .name
= "qhs_venus_cvp_throttle_cfg",
1000 .id
= SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG
,
1005 static struct qcom_icc_node qhs_venus_throttle_cfg
= {
1006 .name
= "qhs_venus_throttle_cfg",
1007 .id
= SM7150_SLAVE_VENUS_THROTTLE_CFG
,
1012 static struct qcom_icc_node qhs_vsense_ctrl_cfg
= {
1013 .name
= "qhs_vsense_ctrl_cfg",
1014 .id
= SM7150_SLAVE_VSENSE_CTRL_CFG
,
1019 static struct qcom_icc_node qns_cnoc_a2noc
= {
1020 .name
= "qns_cnoc_a2noc",
1021 .id
= SM7150_SLAVE_CNOC_A2NOC
,
1025 .links
= { SM7150_MASTER_CNOC_A2NOC
},
1028 static struct qcom_icc_node srvc_cnoc
= {
1029 .name
= "srvc_cnoc",
1030 .id
= SM7150_SLAVE_SERVICE_CNOC
,
1035 static struct qcom_icc_node qhs_gemnoc
= {
1036 .name
= "qhs_gemnoc",
1037 .id
= SM7150_SLAVE_GEM_NOC_CFG
,
1041 .links
= { SM7150_MASTER_GEM_NOC_CFG
},
1044 static struct qcom_icc_node qhs_llcc
= {
1046 .id
= SM7150_SLAVE_LLCC_CFG
,
1051 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg
= {
1052 .name
= "qhs_mdsp_ms_mpu_cfg",
1053 .id
= SM7150_SLAVE_MSS_PROC_MS_MPU_CFG
,
1058 static struct qcom_icc_node qns_gem_noc_snoc
= {
1059 .name
= "qns_gem_noc_snoc",
1060 .id
= SM7150_SLAVE_GEM_NOC_SNOC
,
1064 .links
= { SM7150_MASTER_GEM_NOC_SNOC
},
1067 static struct qcom_icc_node qns_llcc
= {
1069 .id
= SM7150_SLAVE_LLCC
,
1073 .links
= { SM7150_MASTER_LLCC
},
1076 static struct qcom_icc_node srvc_gemnoc
= {
1077 .name
= "srvc_gemnoc",
1078 .id
= SM7150_SLAVE_SERVICE_GEM_NOC
,
1083 static struct qcom_icc_node ebi
= {
1085 .id
= SM7150_SLAVE_EBI_CH0
,
1090 static struct qcom_icc_node qns2_mem_noc
= {
1091 .name
= "qns2_mem_noc",
1092 .id
= SM7150_SLAVE_MNOC_SF_MEM_NOC
,
1096 .links
= { SM7150_MASTER_MNOC_SF_MEM_NOC
},
1099 static struct qcom_icc_node qns_mem_noc_hf
= {
1100 .name
= "qns_mem_noc_hf",
1101 .id
= SM7150_SLAVE_MNOC_HF_MEM_NOC
,
1105 .links
= { SM7150_MASTER_MNOC_HF_MEM_NOC
},
1108 static struct qcom_icc_node srvc_mnoc
= {
1109 .name
= "srvc_mnoc",
1110 .id
= SM7150_SLAVE_SERVICE_MNOC
,
1115 static struct qcom_icc_node qhs_apss
= {
1117 .id
= SM7150_SLAVE_APPSS
,
1122 static struct qcom_icc_node qns_cnoc
= {
1124 .id
= SM7150_SNOC_CNOC_SLV
,
1128 .links
= { SM7150_SNOC_CNOC_MAS
},
1131 static struct qcom_icc_node qns_gemnoc_gc
= {
1132 .name
= "qns_gemnoc_gc",
1133 .id
= SM7150_SLAVE_SNOC_GEM_NOC_GC
,
1137 .links
= { SM7150_MASTER_SNOC_GC_MEM_NOC
},
1140 static struct qcom_icc_node qns_gemnoc_sf
= {
1141 .name
= "qns_gemnoc_sf",
1142 .id
= SM7150_SLAVE_SNOC_GEM_NOC_SF
,
1146 .links
= { SM7150_MASTER_SNOC_SF_MEM_NOC
},
1149 static struct qcom_icc_node qxs_imem
= {
1151 .id
= SM7150_SLAVE_OCIMEM
,
1156 static struct qcom_icc_node qxs_pimem
= {
1157 .name
= "qxs_pimem",
1158 .id
= SM7150_SLAVE_PIMEM
,
1163 static struct qcom_icc_node srvc_snoc
= {
1164 .name
= "srvc_snoc",
1165 .id
= SM7150_SLAVE_SERVICE_SNOC
,
1170 static struct qcom_icc_node xs_qdss_stm
= {
1171 .name
= "xs_qdss_stm",
1172 .id
= SM7150_SLAVE_QDSS_STM
,
1177 static struct qcom_icc_node xs_sys_tcu_cfg
= {
1178 .name
= "xs_sys_tcu_cfg",
1179 .id
= SM7150_SLAVE_TCU
,
1184 static struct qcom_icc_bcm bcm_acv
= {
1186 .enable_mask
= BIT(3),
1192 static struct qcom_icc_bcm bcm_mc0
= {
1199 static struct qcom_icc_bcm bcm_sh0
= {
1203 .nodes
= { &qns_llcc
},
1206 static struct qcom_icc_bcm bcm_mm0
= {
1210 .nodes
= { &qns_mem_noc_hf
},
1213 static struct qcom_icc_bcm bcm_mm1
= {
1217 .nodes
= { &qxm_camnoc_hf0_uncomp
,
1218 &qxm_camnoc_rt_uncomp
,
1219 &qxm_camnoc_sf_uncomp
,
1220 &qxm_camnoc_nrt_uncomp
,
1228 static struct qcom_icc_bcm bcm_sh2
= {
1232 .nodes
= { &qns_gem_noc_snoc
},
1235 static struct qcom_icc_bcm bcm_sh3
= {
1239 .nodes
= { &acm_sys_tcu
},
1242 static struct qcom_icc_bcm bcm_mm2
= {
1246 .nodes
= { &qxm_camnoc_nrt
,
1251 static struct qcom_icc_bcm bcm_mm3
= {
1255 .nodes
= { &qxm_camnoc_sf
,
1263 static struct qcom_icc_bcm bcm_sh5
= {
1267 .nodes
= { &acm_apps
},
1270 static struct qcom_icc_bcm bcm_sn0
= {
1274 .nodes
= { &qns_gemnoc_sf
},
1277 static struct qcom_icc_bcm bcm_sh8
= {
1281 .nodes
= { &qns_cdsp_gemnoc
},
1284 static struct qcom_icc_bcm bcm_sh10
= {
1288 .nodes
= { &qnm_npu
},
1291 static struct qcom_icc_bcm bcm_ce0
= {
1295 .nodes
= { &qxm_crypto
},
1298 static struct qcom_icc_bcm bcm_cn0
= {
1302 .nodes
= { &qhm_tsif
,
1316 &qhs_camera_nrt_thrott_cfg
,
1317 &qhs_camera_rt_throttle_cfg
,
1319 &qhs_compute_dsp_cfg
,
1325 &qhs_display_throttle_cfg
,
1351 &qhs_venus_cvp_throttle_cfg
,
1352 &qhs_venus_throttle_cfg
,
1353 &qhs_vsense_ctrl_cfg
,
1359 static struct qcom_icc_bcm bcm_qup0
= {
1363 .nodes
= { &qhm_qup_center
,
1368 static struct qcom_icc_bcm bcm_sn1
= {
1372 .nodes
= { &qxs_imem
},
1375 static struct qcom_icc_bcm bcm_sn2
= {
1379 .nodes
= { &qns_gemnoc_gc
},
1382 static struct qcom_icc_bcm bcm_sn4
= {
1386 .nodes
= { &qxs_pimem
},
1389 static struct qcom_icc_bcm bcm_sn9
= {
1393 .nodes
= { &qnm_aggre1_noc
,
1398 static struct qcom_icc_bcm bcm_sn11
= {
1402 .nodes
= { &qnm_aggre2_noc
,
1407 static struct qcom_icc_bcm bcm_sn12
= {
1411 .nodes
= { &qxm_pimem
,
1416 static struct qcom_icc_bcm bcm_sn14
= {
1420 .nodes
= { &qns_pcie_gemnoc
},
1423 static struct qcom_icc_bcm bcm_sn15
= {
1427 .nodes
= { &qnm_gemnoc
},
1430 static struct qcom_icc_bcm
* const aggre1_noc_bcms
[] = {
1436 static struct qcom_icc_node
* const aggre1_noc_nodes
[] = {
1437 [MASTER_A1NOC_CFG
] = &qhm_a1noc_cfg
,
1438 [MASTER_QUP_0
] = &qhm_qup_center
,
1439 [MASTER_TSIF
] = &qhm_tsif
,
1440 [MASTER_EMMC
] = &xm_emmc
,
1441 [MASTER_SDCC_2
] = &xm_sdc2
,
1442 [MASTER_SDCC_4
] = &xm_sdc4
,
1443 [MASTER_UFS_MEM
] = &xm_ufs_mem
,
1444 [A1NOC_SNOC_SLV
] = &qns_a1noc_snoc
,
1445 [SLAVE_SERVICE_A1NOC
] = &srvc_aggre1_noc
,
1448 static const struct qcom_icc_desc sm7150_aggre1_noc
= {
1449 .nodes
= aggre1_noc_nodes
,
1450 .num_nodes
= ARRAY_SIZE(aggre1_noc_nodes
),
1451 .bcms
= aggre1_noc_bcms
,
1452 .num_bcms
= ARRAY_SIZE(aggre1_noc_bcms
),
1455 static struct qcom_icc_bcm
* const aggre2_noc_bcms
[] = {
1462 static struct qcom_icc_node
* const aggre2_noc_nodes
[] = {
1463 [MASTER_A2NOC_CFG
] = &qhm_a2noc_cfg
,
1464 [MASTER_QDSS_BAM
] = &qhm_qdss_bam
,
1465 [MASTER_QUP_1
] = &qhm_qup_north
,
1466 [MASTER_CNOC_A2NOC
] = &qnm_cnoc
,
1467 [MASTER_CRYPTO_CORE_0
] = &qxm_crypto
,
1468 [MASTER_IPA
] = &qxm_ipa
,
1469 [MASTER_PCIE
] = &xm_pcie3_0
,
1470 [MASTER_QDSS_ETR
] = &xm_qdss_etr
,
1471 [MASTER_USB3
] = &xm_usb3_0
,
1472 [A2NOC_SNOC_SLV
] = &qns_a2noc_snoc
,
1473 [SLAVE_ANOC_PCIE_GEM_NOC
] = &qns_pcie_gemnoc
,
1474 [SLAVE_SERVICE_A2NOC
] = &srvc_aggre2_noc
,
1477 static const struct qcom_icc_desc sm7150_aggre2_noc
= {
1478 .nodes
= aggre2_noc_nodes
,
1479 .num_nodes
= ARRAY_SIZE(aggre2_noc_nodes
),
1480 .bcms
= aggre2_noc_bcms
,
1481 .num_bcms
= ARRAY_SIZE(aggre2_noc_bcms
),
1484 static struct qcom_icc_bcm
* const camnoc_virt_bcms
[] = {
1488 static struct qcom_icc_node
* const camnoc_virt_nodes
[] = {
1489 [MASTER_CAMNOC_HF0_UNCOMP
] = &qxm_camnoc_hf0_uncomp
,
1490 [MASTER_CAMNOC_RT_UNCOMP
] = &qxm_camnoc_rt_uncomp
,
1491 [MASTER_CAMNOC_SF_UNCOMP
] = &qxm_camnoc_sf_uncomp
,
1492 [MASTER_CAMNOC_NRT_UNCOMP
] = &qxm_camnoc_nrt_uncomp
,
1493 [SLAVE_CAMNOC_UNCOMP
] = &qns_camnoc_uncomp
,
1496 static const struct qcom_icc_desc sm7150_camnoc_virt
= {
1497 .nodes
= camnoc_virt_nodes
,
1498 .num_nodes
= ARRAY_SIZE(camnoc_virt_nodes
),
1499 .bcms
= camnoc_virt_bcms
,
1500 .num_bcms
= ARRAY_SIZE(camnoc_virt_bcms
),
1503 static struct qcom_icc_bcm
* const compute_noc_bcms
[] = {
1508 static struct qcom_icc_node
* const compute_noc_nodes
[] = {
1509 [MASTER_NPU
] = &qnm_npu
,
1510 [SLAVE_CDSP_GEM_NOC
] = &qns_cdsp_gemnoc
,
1513 static const struct qcom_icc_desc sm7150_compute_noc
= {
1514 .nodes
= compute_noc_nodes
,
1515 .num_nodes
= ARRAY_SIZE(compute_noc_nodes
),
1516 .bcms
= compute_noc_bcms
,
1517 .num_bcms
= ARRAY_SIZE(compute_noc_bcms
),
1520 static struct qcom_icc_bcm
* const config_noc_bcms
[] = {
1524 static struct qcom_icc_node
* const config_noc_nodes
[] = {
1525 [MASTER_SPDM
] = &qhm_spdm
,
1526 [SNOC_CNOC_MAS
] = &qnm_snoc
,
1527 [MASTER_QDSS_DAP
] = &xm_qdss_dap
,
1528 [SLAVE_A1NOC_CFG
] = &qhs_a1_noc_cfg
,
1529 [SLAVE_A2NOC_CFG
] = &qhs_a2_noc_cfg
,
1530 [SLAVE_AHB2PHY_NORTH
] = &qhs_ahb2phy_north
,
1531 [SLAVE_AHB2PHY_SOUTH
] = &qhs_ahb2phy_south
,
1532 [SLAVE_AHB2PHY_WEST
] = &qhs_ahb2phy_west
,
1533 [SLAVE_AOP
] = &qhs_aop
,
1534 [SLAVE_AOSS
] = &qhs_aoss
,
1535 [SLAVE_CAMERA_CFG
] = &qhs_camera_cfg
,
1536 [SLAVE_CAMERA_NRT_THROTTLE_CFG
] = &qhs_camera_nrt_thrott_cfg
,
1537 [SLAVE_CAMERA_RT_THROTTLE_CFG
] = &qhs_camera_rt_throttle_cfg
,
1538 [SLAVE_CLK_CTL
] = &qhs_clk_ctl
,
1539 [SLAVE_CDSP_CFG
] = &qhs_compute_dsp_cfg
,
1540 [SLAVE_RBCPR_CX_CFG
] = &qhs_cpr_cx
,
1541 [SLAVE_RBCPR_MX_CFG
] = &qhs_cpr_mx
,
1542 [SLAVE_CRYPTO_0_CFG
] = &qhs_crypto0_cfg
,
1543 [SLAVE_CNOC_DDRSS
] = &qhs_ddrss_cfg
,
1544 [SLAVE_DISPLAY_CFG
] = &qhs_display_cfg
,
1545 [SLAVE_DISPLAY_THROTTLE_CFG
] = &qhs_display_throttle_cfg
,
1546 [SLAVE_EMMC_CFG
] = &qhs_emmc_cfg
,
1547 [SLAVE_GLM
] = &qhs_glm
,
1548 [SLAVE_GRAPHICS_3D_CFG
] = &qhs_gpuss_cfg
,
1549 [SLAVE_IMEM_CFG
] = &qhs_imem_cfg
,
1550 [SLAVE_IPA_CFG
] = &qhs_ipa
,
1551 [SLAVE_CNOC_MNOC_CFG
] = &qhs_mnoc_cfg
,
1552 [SLAVE_PCIE_CFG
] = &qhs_pcie_cfg
,
1553 [SLAVE_PDM
] = &qhs_pdm
,
1554 [SLAVE_PIMEM_CFG
] = &qhs_pimem_cfg
,
1555 [SLAVE_PRNG
] = &qhs_prng
,
1556 [SLAVE_QDSS_CFG
] = &qhs_qdss_cfg
,
1557 [SLAVE_QUP_0
] = &qhs_qupv3_center
,
1558 [SLAVE_QUP_1
] = &qhs_qupv3_north
,
1559 [SLAVE_SDCC_2
] = &qhs_sdc2
,
1560 [SLAVE_SDCC_4
] = &qhs_sdc4
,
1561 [SLAVE_SNOC_CFG
] = &qhs_snoc_cfg
,
1562 [SLAVE_SPDM_WRAPPER
] = &qhs_spdm
,
1563 [SLAVE_TCSR
] = &qhs_tcsr
,
1564 [SLAVE_TLMM_NORTH
] = &qhs_tlmm_north
,
1565 [SLAVE_TLMM_SOUTH
] = &qhs_tlmm_south
,
1566 [SLAVE_TLMM_WEST
] = &qhs_tlmm_west
,
1567 [SLAVE_TSIF
] = &qhs_tsif
,
1568 [SLAVE_UFS_MEM_CFG
] = &qhs_ufs_mem_cfg
,
1569 [SLAVE_USB3
] = &qhs_usb3_0
,
1570 [SLAVE_VENUS_CFG
] = &qhs_venus_cfg
,
1571 [SLAVE_VENUS_CVP_THROTTLE_CFG
] = &qhs_venus_cvp_throttle_cfg
,
1572 [SLAVE_VENUS_THROTTLE_CFG
] = &qhs_venus_throttle_cfg
,
1573 [SLAVE_VSENSE_CTRL_CFG
] = &qhs_vsense_ctrl_cfg
,
1574 [SLAVE_CNOC_A2NOC
] = &qns_cnoc_a2noc
,
1575 [SLAVE_SERVICE_CNOC
] = &srvc_cnoc
,
1578 static const struct qcom_icc_desc sm7150_config_noc
= {
1579 .nodes
= config_noc_nodes
,
1580 .num_nodes
= ARRAY_SIZE(config_noc_nodes
),
1581 .bcms
= config_noc_bcms
,
1582 .num_bcms
= ARRAY_SIZE(config_noc_bcms
),
1585 static struct qcom_icc_bcm
* const dc_noc_bcms
[] = {
1588 static struct qcom_icc_node
* const dc_noc_nodes
[] = {
1589 [MASTER_CNOC_DC_NOC
] = &qhm_cnoc_dc_noc
,
1590 [SLAVE_GEM_NOC_CFG
] = &qhs_gemnoc
,
1591 [SLAVE_LLCC_CFG
] = &qhs_llcc
,
1594 static const struct qcom_icc_desc sm7150_dc_noc
= {
1595 .nodes
= dc_noc_nodes
,
1596 .num_nodes
= ARRAY_SIZE(dc_noc_nodes
),
1597 .bcms
= dc_noc_bcms
,
1598 .num_bcms
= ARRAY_SIZE(dc_noc_bcms
),
1601 static struct qcom_icc_bcm
* const gem_noc_bcms
[] = {
1608 static struct qcom_icc_node
* const gem_noc_nodes
[] = {
1609 [MASTER_AMPSS_M0
] = &acm_apps
,
1610 [MASTER_SYS_TCU
] = &acm_sys_tcu
,
1611 [MASTER_GEM_NOC_CFG
] = &qhm_gemnoc_cfg
,
1612 [MASTER_COMPUTE_NOC
] = &qnm_cmpnoc
,
1613 [MASTER_MNOC_HF_MEM_NOC
] = &qnm_mnoc_hf
,
1614 [MASTER_MNOC_SF_MEM_NOC
] = &qnm_mnoc_sf
,
1615 [MASTER_GEM_NOC_PCIE_SNOC
] = &qnm_pcie
,
1616 [MASTER_SNOC_GC_MEM_NOC
] = &qnm_snoc_gc
,
1617 [MASTER_SNOC_SF_MEM_NOC
] = &qnm_snoc_sf
,
1618 [MASTER_GRAPHICS_3D
] = &qxm_gpu
,
1619 [SLAVE_MSS_PROC_MS_MPU_CFG
] = &qhs_mdsp_ms_mpu_cfg
,
1620 [SLAVE_GEM_NOC_SNOC
] = &qns_gem_noc_snoc
,
1621 [SLAVE_LLCC
] = &qns_llcc
,
1622 [SLAVE_SERVICE_GEM_NOC
] = &srvc_gemnoc
,
1625 static const struct qcom_icc_desc sm7150_gem_noc
= {
1626 .nodes
= gem_noc_nodes
,
1627 .num_nodes
= ARRAY_SIZE(gem_noc_nodes
),
1628 .bcms
= gem_noc_bcms
,
1629 .num_bcms
= ARRAY_SIZE(gem_noc_bcms
),
1632 static struct qcom_icc_bcm
* const mc_virt_bcms
[] = {
1637 static struct qcom_icc_node
* const mc_virt_nodes
[] = {
1638 [MASTER_LLCC
] = &llcc_mc
,
1639 [SLAVE_EBI_CH0
] = &ebi
,
1642 static const struct qcom_icc_desc sm7150_mc_virt
= {
1643 .nodes
= mc_virt_nodes
,
1644 .num_nodes
= ARRAY_SIZE(mc_virt_nodes
),
1645 .bcms
= mc_virt_bcms
,
1646 .num_bcms
= ARRAY_SIZE(mc_virt_bcms
),
1649 static struct qcom_icc_bcm
* const mmss_noc_bcms
[] = {
1656 static struct qcom_icc_node
* const mmss_noc_nodes
[] = {
1657 [MASTER_CNOC_MNOC_CFG
] = &qhm_mnoc_cfg
,
1658 [MASTER_CAMNOC_HF0
] = &qxm_camnoc_hf
,
1659 [MASTER_CAMNOC_NRT
] = &qxm_camnoc_nrt
,
1660 [MASTER_CAMNOC_RT
] = &qxm_camnoc_rt
,
1661 [MASTER_CAMNOC_SF
] = &qxm_camnoc_sf
,
1662 [MASTER_MDP_PORT0
] = &qxm_mdp0
,
1663 [MASTER_MDP_PORT1
] = &qxm_mdp1
,
1664 [MASTER_ROTATOR
] = &qxm_rot
,
1665 [MASTER_VIDEO_P0
] = &qxm_venus0
,
1666 [MASTER_VIDEO_P1
] = &qxm_venus1
,
1667 [MASTER_VIDEO_PROC
] = &qxm_venus_arm9
,
1668 [SLAVE_MNOC_SF_MEM_NOC
] = &qns2_mem_noc
,
1669 [SLAVE_MNOC_HF_MEM_NOC
] = &qns_mem_noc_hf
,
1670 [SLAVE_SERVICE_MNOC
] = &srvc_mnoc
,
1673 static const struct qcom_icc_desc sm7150_mmss_noc
= {
1674 .nodes
= mmss_noc_nodes
,
1675 .num_nodes
= ARRAY_SIZE(mmss_noc_nodes
),
1676 .bcms
= mmss_noc_bcms
,
1677 .num_bcms
= ARRAY_SIZE(mmss_noc_bcms
),
1680 static struct qcom_icc_bcm
* const system_noc_bcms
[] = {
1691 static struct qcom_icc_node
* const system_noc_nodes
[] = {
1692 [MASTER_SNOC_CFG
] = &qhm_snoc_cfg
,
1693 [A1NOC_SNOC_MAS
] = &qnm_aggre1_noc
,
1694 [A2NOC_SNOC_MAS
] = &qnm_aggre2_noc
,
1695 [MASTER_GEM_NOC_SNOC
] = &qnm_gemnoc
,
1696 [MASTER_PIMEM
] = &qxm_pimem
,
1697 [MASTER_GIC
] = &xm_gic
,
1698 [SLAVE_APPSS
] = &qhs_apss
,
1699 [SNOC_CNOC_SLV
] = &qns_cnoc
,
1700 [SLAVE_SNOC_GEM_NOC_GC
] = &qns_gemnoc_gc
,
1701 [SLAVE_SNOC_GEM_NOC_SF
] = &qns_gemnoc_sf
,
1702 [SLAVE_OCIMEM
] = &qxs_imem
,
1703 [SLAVE_PIMEM
] = &qxs_pimem
,
1704 [SLAVE_SERVICE_SNOC
] = &srvc_snoc
,
1705 [SLAVE_QDSS_STM
] = &xs_qdss_stm
,
1706 [SLAVE_TCU
] = &xs_sys_tcu_cfg
,
1709 static const struct qcom_icc_desc sm7150_system_noc
= {
1710 .nodes
= system_noc_nodes
,
1711 .num_nodes
= ARRAY_SIZE(system_noc_nodes
),
1712 .bcms
= system_noc_bcms
,
1713 .num_bcms
= ARRAY_SIZE(system_noc_bcms
),
1716 static const struct of_device_id qnoc_of_match
[] = {
1717 { .compatible
= "qcom,sm7150-aggre1-noc", .data
= &sm7150_aggre1_noc
},
1718 { .compatible
= "qcom,sm7150-aggre2-noc", .data
= &sm7150_aggre2_noc
},
1719 { .compatible
= "qcom,sm7150-camnoc-virt", .data
= &sm7150_camnoc_virt
},
1720 { .compatible
= "qcom,sm7150-compute-noc", .data
= &sm7150_compute_noc
},
1721 { .compatible
= "qcom,sm7150-config-noc", .data
= &sm7150_config_noc
},
1722 { .compatible
= "qcom,sm7150-dc-noc", .data
= &sm7150_dc_noc
},
1723 { .compatible
= "qcom,sm7150-gem-noc", .data
= &sm7150_gem_noc
},
1724 { .compatible
= "qcom,sm7150-mc-virt", .data
= &sm7150_mc_virt
},
1725 { .compatible
= "qcom,sm7150-mmss-noc", .data
= &sm7150_mmss_noc
},
1726 { .compatible
= "qcom,sm7150-system-noc", .data
= &sm7150_system_noc
},
1729 MODULE_DEVICE_TABLE(of
, qnoc_of_match
);
1731 static struct platform_driver qnoc_driver
= {
1732 .probe
= qcom_icc_rpmh_probe
,
1733 .remove
= qcom_icc_rpmh_remove
,
1735 .name
= "qnoc-sm7150",
1736 .of_match_table
= qnoc_of_match
,
1737 .sync_state
= icc_sync_state
,
1741 static int __init
qnoc_driver_init(void)
1743 return platform_driver_register(&qnoc_driver
);
1745 core_initcall(qnoc_driver_init
);
1747 static void __exit
qnoc_driver_exit(void)
1749 platform_driver_unregister(&qnoc_driver
);
1751 module_exit(qnoc_driver_exit
);
1753 MODULE_DESCRIPTION("Qualcomm SM7150 NoC driver");
1754 MODULE_LICENSE("GPL");