1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include "bcm-voter.h"
19 static struct qcom_icc_node qhm_a1noc_cfg
= {
20 .name
= "qhm_a1noc_cfg",
21 .id
= SM8250_MASTER_A1NOC_CFG
,
25 .links
= { SM8250_SLAVE_SERVICE_A1NOC
},
28 static struct qcom_icc_node qhm_qspi
= {
30 .id
= SM8250_MASTER_QSPI_0
,
34 .links
= { SM8250_A1NOC_SNOC_SLV
},
37 static struct qcom_icc_node qhm_qup1
= {
39 .id
= SM8250_MASTER_QUP_1
,
43 .links
= { SM8250_A1NOC_SNOC_SLV
},
46 static struct qcom_icc_node qhm_qup2
= {
48 .id
= SM8250_MASTER_QUP_2
,
52 .links
= { SM8250_A1NOC_SNOC_SLV
},
55 static struct qcom_icc_node qhm_tsif
= {
57 .id
= SM8250_MASTER_TSIF
,
61 .links
= { SM8250_A1NOC_SNOC_SLV
},
64 static struct qcom_icc_node xm_pcie3_modem
= {
65 .name
= "xm_pcie3_modem",
66 .id
= SM8250_MASTER_PCIE_2
,
70 .links
= { SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1
},
73 static struct qcom_icc_node xm_sdc4
= {
75 .id
= SM8250_MASTER_SDCC_4
,
79 .links
= { SM8250_A1NOC_SNOC_SLV
},
82 static struct qcom_icc_node xm_ufs_mem
= {
84 .id
= SM8250_MASTER_UFS_MEM
,
88 .links
= { SM8250_A1NOC_SNOC_SLV
},
91 static struct qcom_icc_node xm_usb3_0
= {
93 .id
= SM8250_MASTER_USB3
,
97 .links
= { SM8250_A1NOC_SNOC_SLV
},
100 static struct qcom_icc_node xm_usb3_1
= {
102 .id
= SM8250_MASTER_USB3_1
,
106 .links
= { SM8250_A1NOC_SNOC_SLV
},
109 static struct qcom_icc_node qhm_a2noc_cfg
= {
110 .name
= "qhm_a2noc_cfg",
111 .id
= SM8250_MASTER_A2NOC_CFG
,
115 .links
= { SM8250_SLAVE_SERVICE_A2NOC
},
118 static struct qcom_icc_node qhm_qdss_bam
= {
119 .name
= "qhm_qdss_bam",
120 .id
= SM8250_MASTER_QDSS_BAM
,
124 .links
= { SM8250_A2NOC_SNOC_SLV
},
127 static struct qcom_icc_node qhm_qup0
= {
129 .id
= SM8250_MASTER_QUP_0
,
133 .links
= { SM8250_A2NOC_SNOC_SLV
},
136 static struct qcom_icc_node qnm_cnoc
= {
138 .id
= SM8250_MASTER_CNOC_A2NOC
,
142 .links
= { SM8250_A2NOC_SNOC_SLV
},
145 static struct qcom_icc_node qxm_crypto
= {
146 .name
= "qxm_crypto",
147 .id
= SM8250_MASTER_CRYPTO_CORE_0
,
151 .links
= { SM8250_A2NOC_SNOC_SLV
},
154 static struct qcom_icc_node qxm_ipa
= {
156 .id
= SM8250_MASTER_IPA
,
160 .links
= { SM8250_A2NOC_SNOC_SLV
},
163 static struct qcom_icc_node xm_pcie3_0
= {
164 .name
= "xm_pcie3_0",
165 .id
= SM8250_MASTER_PCIE
,
169 .links
= { SM8250_SLAVE_ANOC_PCIE_GEM_NOC
},
172 static struct qcom_icc_node xm_pcie3_1
= {
173 .name
= "xm_pcie3_1",
174 .id
= SM8250_MASTER_PCIE_1
,
178 .links
= { SM8250_SLAVE_ANOC_PCIE_GEM_NOC
},
181 static struct qcom_icc_node xm_qdss_etr
= {
182 .name
= "xm_qdss_etr",
183 .id
= SM8250_MASTER_QDSS_ETR
,
187 .links
= { SM8250_A2NOC_SNOC_SLV
},
190 static struct qcom_icc_node xm_sdc2
= {
192 .id
= SM8250_MASTER_SDCC_2
,
196 .links
= { SM8250_A2NOC_SNOC_SLV
},
199 static struct qcom_icc_node xm_ufs_card
= {
200 .name
= "xm_ufs_card",
201 .id
= SM8250_MASTER_UFS_CARD
,
205 .links
= { SM8250_A2NOC_SNOC_SLV
},
208 static struct qcom_icc_node qnm_npu
= {
210 .id
= SM8250_MASTER_NPU
,
214 .links
= { SM8250_SLAVE_CDSP_MEM_NOC
},
217 static struct qcom_icc_node qnm_snoc
= {
219 .id
= SM8250_SNOC_CNOC_MAS
,
223 .links
= { SM8250_SLAVE_CDSP_CFG
,
224 SM8250_SLAVE_CAMERA_CFG
,
225 SM8250_SLAVE_TLMM_SOUTH
,
226 SM8250_SLAVE_TLMM_NORTH
,
228 SM8250_SLAVE_TLMM_WEST
,
230 SM8250_SLAVE_CNOC_MNOC_CFG
,
231 SM8250_SLAVE_UFS_MEM_CFG
,
232 SM8250_SLAVE_SNOC_CFG
,
234 SM8250_SLAVE_CX_RDPM
,
235 SM8250_SLAVE_PCIE_1_CFG
,
236 SM8250_SLAVE_A2NOC_CFG
,
237 SM8250_SLAVE_QDSS_CFG
,
238 SM8250_SLAVE_DISPLAY_CFG
,
239 SM8250_SLAVE_PCIE_2_CFG
,
241 SM8250_SLAVE_DCC_CFG
,
242 SM8250_SLAVE_CNOC_DDRSS
,
243 SM8250_SLAVE_IPC_ROUTER_CFG
,
244 SM8250_SLAVE_PCIE_0_CFG
,
245 SM8250_SLAVE_RBCPR_MMCX_CFG
,
246 SM8250_SLAVE_NPU_CFG
,
247 SM8250_SLAVE_AHB2PHY_SOUTH
,
248 SM8250_SLAVE_AHB2PHY_NORTH
,
249 SM8250_SLAVE_GRAPHICS_3D_CFG
,
250 SM8250_SLAVE_VENUS_CFG
,
252 SM8250_SLAVE_IPA_CFG
,
253 SM8250_SLAVE_IMEM_CFG
,
255 SM8250_SLAVE_SERVICE_CNOC
,
256 SM8250_SLAVE_UFS_CARD_CFG
,
259 SM8250_SLAVE_RBCPR_CX_CFG
,
260 SM8250_SLAVE_A1NOC_CFG
,
263 SM8250_SLAVE_VSENSE_CTRL_CFG
,
265 SM8250_SLAVE_CRYPTO_0_CFG
,
266 SM8250_SLAVE_PIMEM_CFG
,
267 SM8250_SLAVE_RBCPR_MX_CFG
,
275 static struct qcom_icc_node xm_qdss_dap
= {
276 .name
= "xm_qdss_dap",
277 .id
= SM8250_MASTER_QDSS_DAP
,
281 .links
= { SM8250_SLAVE_CDSP_CFG
,
282 SM8250_SLAVE_CAMERA_CFG
,
283 SM8250_SLAVE_TLMM_SOUTH
,
284 SM8250_SLAVE_TLMM_NORTH
,
286 SM8250_SLAVE_TLMM_WEST
,
288 SM8250_SLAVE_CNOC_MNOC_CFG
,
289 SM8250_SLAVE_UFS_MEM_CFG
,
290 SM8250_SLAVE_SNOC_CFG
,
292 SM8250_SLAVE_CX_RDPM
,
293 SM8250_SLAVE_PCIE_1_CFG
,
294 SM8250_SLAVE_A2NOC_CFG
,
295 SM8250_SLAVE_QDSS_CFG
,
296 SM8250_SLAVE_DISPLAY_CFG
,
297 SM8250_SLAVE_PCIE_2_CFG
,
299 SM8250_SLAVE_DCC_CFG
,
300 SM8250_SLAVE_CNOC_DDRSS
,
301 SM8250_SLAVE_IPC_ROUTER_CFG
,
302 SM8250_SLAVE_CNOC_A2NOC
,
303 SM8250_SLAVE_PCIE_0_CFG
,
304 SM8250_SLAVE_RBCPR_MMCX_CFG
,
305 SM8250_SLAVE_NPU_CFG
,
306 SM8250_SLAVE_AHB2PHY_SOUTH
,
307 SM8250_SLAVE_AHB2PHY_NORTH
,
308 SM8250_SLAVE_GRAPHICS_3D_CFG
,
309 SM8250_SLAVE_VENUS_CFG
,
311 SM8250_SLAVE_IPA_CFG
,
312 SM8250_SLAVE_IMEM_CFG
,
314 SM8250_SLAVE_SERVICE_CNOC
,
315 SM8250_SLAVE_UFS_CARD_CFG
,
318 SM8250_SLAVE_RBCPR_CX_CFG
,
319 SM8250_SLAVE_A1NOC_CFG
,
322 SM8250_SLAVE_VSENSE_CTRL_CFG
,
324 SM8250_SLAVE_CRYPTO_0_CFG
,
325 SM8250_SLAVE_PIMEM_CFG
,
326 SM8250_SLAVE_RBCPR_MX_CFG
,
334 static struct qcom_icc_node qhm_cnoc_dc_noc
= {
335 .name
= "qhm_cnoc_dc_noc",
336 .id
= SM8250_MASTER_CNOC_DC_NOC
,
340 .links
= { SM8250_SLAVE_GEM_NOC_CFG
,
341 SM8250_SLAVE_LLCC_CFG
345 static struct qcom_icc_node alm_gpu_tcu
= {
346 .name
= "alm_gpu_tcu",
347 .id
= SM8250_MASTER_GPU_TCU
,
351 .links
= { SM8250_SLAVE_LLCC
,
352 SM8250_SLAVE_GEM_NOC_SNOC
356 static struct qcom_icc_node alm_sys_tcu
= {
357 .name
= "alm_sys_tcu",
358 .id
= SM8250_MASTER_SYS_TCU
,
362 .links
= { SM8250_SLAVE_LLCC
,
363 SM8250_SLAVE_GEM_NOC_SNOC
367 static struct qcom_icc_node chm_apps
= {
369 .id
= SM8250_MASTER_AMPSS_M0
,
373 .links
= { SM8250_SLAVE_LLCC
,
374 SM8250_SLAVE_GEM_NOC_SNOC
,
375 SM8250_SLAVE_MEM_NOC_PCIE_SNOC
379 static struct qcom_icc_node qhm_gemnoc_cfg
= {
380 .name
= "qhm_gemnoc_cfg",
381 .id
= SM8250_MASTER_GEM_NOC_CFG
,
385 .links
= { SM8250_SLAVE_SERVICE_GEM_NOC_2
,
386 SM8250_SLAVE_SERVICE_GEM_NOC_1
,
387 SM8250_SLAVE_SERVICE_GEM_NOC
391 static struct qcom_icc_node qnm_cmpnoc
= {
392 .name
= "qnm_cmpnoc",
393 .id
= SM8250_MASTER_COMPUTE_NOC
,
397 .links
= { SM8250_SLAVE_LLCC
,
398 SM8250_SLAVE_GEM_NOC_SNOC
402 static struct qcom_icc_node qnm_gpu
= {
404 .id
= SM8250_MASTER_GRAPHICS_3D
,
408 .links
= { SM8250_SLAVE_LLCC
,
409 SM8250_SLAVE_GEM_NOC_SNOC
},
412 static struct qcom_icc_node qnm_mnoc_hf
= {
413 .name
= "qnm_mnoc_hf",
414 .id
= SM8250_MASTER_MNOC_HF_MEM_NOC
,
418 .links
= { SM8250_SLAVE_LLCC
},
421 static struct qcom_icc_node qnm_mnoc_sf
= {
422 .name
= "qnm_mnoc_sf",
423 .id
= SM8250_MASTER_MNOC_SF_MEM_NOC
,
427 .links
= { SM8250_SLAVE_LLCC
,
428 SM8250_SLAVE_GEM_NOC_SNOC
432 static struct qcom_icc_node qnm_pcie
= {
434 .id
= SM8250_MASTER_ANOC_PCIE_GEM_NOC
,
438 .links
= { SM8250_SLAVE_LLCC
,
439 SM8250_SLAVE_GEM_NOC_SNOC
443 static struct qcom_icc_node qnm_snoc_gc
= {
444 .name
= "qnm_snoc_gc",
445 .id
= SM8250_MASTER_SNOC_GC_MEM_NOC
,
449 .links
= { SM8250_SLAVE_LLCC
},
452 static struct qcom_icc_node qnm_snoc_sf
= {
453 .name
= "qnm_snoc_sf",
454 .id
= SM8250_MASTER_SNOC_SF_MEM_NOC
,
458 .links
= { SM8250_SLAVE_LLCC
,
459 SM8250_SLAVE_GEM_NOC_SNOC
,
460 SM8250_SLAVE_MEM_NOC_PCIE_SNOC
464 static struct qcom_icc_node llcc_mc
= {
466 .id
= SM8250_MASTER_LLCC
,
470 .links
= { SM8250_SLAVE_EBI_CH0
},
473 static struct qcom_icc_node qhm_mnoc_cfg
= {
474 .name
= "qhm_mnoc_cfg",
475 .id
= SM8250_MASTER_CNOC_MNOC_CFG
,
479 .links
= { SM8250_SLAVE_SERVICE_MNOC
},
482 static struct qcom_icc_node qnm_camnoc_hf
= {
483 .name
= "qnm_camnoc_hf",
484 .id
= SM8250_MASTER_CAMNOC_HF
,
488 .links
= { SM8250_SLAVE_MNOC_HF_MEM_NOC
},
491 static struct qcom_icc_node qnm_camnoc_icp
= {
492 .name
= "qnm_camnoc_icp",
493 .id
= SM8250_MASTER_CAMNOC_ICP
,
497 .links
= { SM8250_SLAVE_MNOC_SF_MEM_NOC
},
500 static struct qcom_icc_node qnm_camnoc_sf
= {
501 .name
= "qnm_camnoc_sf",
502 .id
= SM8250_MASTER_CAMNOC_SF
,
506 .links
= { SM8250_SLAVE_MNOC_SF_MEM_NOC
},
509 static struct qcom_icc_node qnm_video0
= {
510 .name
= "qnm_video0",
511 .id
= SM8250_MASTER_VIDEO_P0
,
515 .links
= { SM8250_SLAVE_MNOC_SF_MEM_NOC
},
518 static struct qcom_icc_node qnm_video1
= {
519 .name
= "qnm_video1",
520 .id
= SM8250_MASTER_VIDEO_P1
,
524 .links
= { SM8250_SLAVE_MNOC_SF_MEM_NOC
},
527 static struct qcom_icc_node qnm_video_cvp
= {
528 .name
= "qnm_video_cvp",
529 .id
= SM8250_MASTER_VIDEO_PROC
,
533 .links
= { SM8250_SLAVE_MNOC_SF_MEM_NOC
},
536 static struct qcom_icc_node qxm_mdp0
= {
538 .id
= SM8250_MASTER_MDP_PORT0
,
542 .links
= { SM8250_SLAVE_MNOC_HF_MEM_NOC
},
545 static struct qcom_icc_node qxm_mdp1
= {
547 .id
= SM8250_MASTER_MDP_PORT1
,
551 .links
= { SM8250_SLAVE_MNOC_HF_MEM_NOC
},
554 static struct qcom_icc_node qxm_rot
= {
556 .id
= SM8250_MASTER_ROTATOR
,
560 .links
= { SM8250_SLAVE_MNOC_SF_MEM_NOC
},
563 static struct qcom_icc_node amm_npu_sys
= {
564 .name
= "amm_npu_sys",
565 .id
= SM8250_MASTER_NPU_SYS
,
569 .links
= { SM8250_SLAVE_NPU_COMPUTE_NOC
},
572 static struct qcom_icc_node amm_npu_sys_cdp_w
= {
573 .name
= "amm_npu_sys_cdp_w",
574 .id
= SM8250_MASTER_NPU_CDP
,
578 .links
= { SM8250_SLAVE_NPU_COMPUTE_NOC
},
581 static struct qcom_icc_node qhm_cfg
= {
583 .id
= SM8250_MASTER_NPU_NOC_CFG
,
587 .links
= { SM8250_SLAVE_SERVICE_NPU_NOC
,
588 SM8250_SLAVE_ISENSE_CFG
,
589 SM8250_SLAVE_NPU_LLM_CFG
,
590 SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG
,
592 SM8250_SLAVE_NPU_TCM
,
593 SM8250_SLAVE_NPU_CAL_DP0
,
594 SM8250_SLAVE_NPU_CAL_DP1
,
599 static struct qcom_icc_node qhm_snoc_cfg
= {
600 .name
= "qhm_snoc_cfg",
601 .id
= SM8250_MASTER_SNOC_CFG
,
605 .links
= { SM8250_SLAVE_SERVICE_SNOC
},
608 static struct qcom_icc_node qnm_aggre1_noc
= {
609 .name
= "qnm_aggre1_noc",
610 .id
= SM8250_A1NOC_SNOC_MAS
,
614 .links
= { SM8250_SLAVE_SNOC_GEM_NOC_SF
},
617 static struct qcom_icc_node qnm_aggre2_noc
= {
618 .name
= "qnm_aggre2_noc",
619 .id
= SM8250_A2NOC_SNOC_MAS
,
623 .links
= { SM8250_SLAVE_SNOC_GEM_NOC_SF
},
626 static struct qcom_icc_node qnm_gemnoc
= {
627 .name
= "qnm_gemnoc",
628 .id
= SM8250_MASTER_GEM_NOC_SNOC
,
632 .links
= { SM8250_SLAVE_PIMEM
,
635 SM8250_SNOC_CNOC_SLV
,
637 SM8250_SLAVE_QDSS_STM
641 static struct qcom_icc_node qnm_gemnoc_pcie
= {
642 .name
= "qnm_gemnoc_pcie",
643 .id
= SM8250_MASTER_GEM_NOC_PCIE_SNOC
,
647 .links
= { SM8250_SLAVE_PCIE_2
,
653 static struct qcom_icc_node qxm_pimem
= {
655 .id
= SM8250_MASTER_PIMEM
,
659 .links
= { SM8250_SLAVE_SNOC_GEM_NOC_GC
},
662 static struct qcom_icc_node xm_gic
= {
664 .id
= SM8250_MASTER_GIC
,
668 .links
= { SM8250_SLAVE_SNOC_GEM_NOC_GC
},
671 static struct qcom_icc_node qns_a1noc_snoc
= {
672 .name
= "qns_a1noc_snoc",
673 .id
= SM8250_A1NOC_SNOC_SLV
,
677 .links
= { SM8250_A1NOC_SNOC_MAS
},
680 static struct qcom_icc_node qns_pcie_modem_mem_noc
= {
681 .name
= "qns_pcie_modem_mem_noc",
682 .id
= SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1
,
686 .links
= { SM8250_MASTER_ANOC_PCIE_GEM_NOC
},
689 static struct qcom_icc_node srvc_aggre1_noc
= {
690 .name
= "srvc_aggre1_noc",
691 .id
= SM8250_SLAVE_SERVICE_A1NOC
,
696 static struct qcom_icc_node qns_a2noc_snoc
= {
697 .name
= "qns_a2noc_snoc",
698 .id
= SM8250_A2NOC_SNOC_SLV
,
702 .links
= { SM8250_A2NOC_SNOC_MAS
},
705 static struct qcom_icc_node qns_pcie_mem_noc
= {
706 .name
= "qns_pcie_mem_noc",
707 .id
= SM8250_SLAVE_ANOC_PCIE_GEM_NOC
,
711 .links
= { SM8250_MASTER_ANOC_PCIE_GEM_NOC
},
714 static struct qcom_icc_node srvc_aggre2_noc
= {
715 .name
= "srvc_aggre2_noc",
716 .id
= SM8250_SLAVE_SERVICE_A2NOC
,
721 static struct qcom_icc_node qns_cdsp_mem_noc
= {
722 .name
= "qns_cdsp_mem_noc",
723 .id
= SM8250_SLAVE_CDSP_MEM_NOC
,
727 .links
= { SM8250_MASTER_COMPUTE_NOC
},
730 static struct qcom_icc_node qhs_a1_noc_cfg
= {
731 .name
= "qhs_a1_noc_cfg",
732 .id
= SM8250_SLAVE_A1NOC_CFG
,
736 .links
= { SM8250_MASTER_A1NOC_CFG
},
739 static struct qcom_icc_node qhs_a2_noc_cfg
= {
740 .name
= "qhs_a2_noc_cfg",
741 .id
= SM8250_SLAVE_A2NOC_CFG
,
745 .links
= { SM8250_MASTER_A2NOC_CFG
},
748 static struct qcom_icc_node qhs_ahb2phy0
= {
749 .name
= "qhs_ahb2phy0",
750 .id
= SM8250_SLAVE_AHB2PHY_SOUTH
,
755 static struct qcom_icc_node qhs_ahb2phy1
= {
756 .name
= "qhs_ahb2phy1",
757 .id
= SM8250_SLAVE_AHB2PHY_NORTH
,
762 static struct qcom_icc_node qhs_aoss
= {
764 .id
= SM8250_SLAVE_AOSS
,
769 static struct qcom_icc_node qhs_camera_cfg
= {
770 .name
= "qhs_camera_cfg",
771 .id
= SM8250_SLAVE_CAMERA_CFG
,
776 static struct qcom_icc_node qhs_clk_ctl
= {
777 .name
= "qhs_clk_ctl",
778 .id
= SM8250_SLAVE_CLK_CTL
,
783 static struct qcom_icc_node qhs_compute_dsp
= {
784 .name
= "qhs_compute_dsp",
785 .id
= SM8250_SLAVE_CDSP_CFG
,
790 static struct qcom_icc_node qhs_cpr_cx
= {
791 .name
= "qhs_cpr_cx",
792 .id
= SM8250_SLAVE_RBCPR_CX_CFG
,
797 static struct qcom_icc_node qhs_cpr_mmcx
= {
798 .name
= "qhs_cpr_mmcx",
799 .id
= SM8250_SLAVE_RBCPR_MMCX_CFG
,
804 static struct qcom_icc_node qhs_cpr_mx
= {
805 .name
= "qhs_cpr_mx",
806 .id
= SM8250_SLAVE_RBCPR_MX_CFG
,
811 static struct qcom_icc_node qhs_crypto0_cfg
= {
812 .name
= "qhs_crypto0_cfg",
813 .id
= SM8250_SLAVE_CRYPTO_0_CFG
,
818 static struct qcom_icc_node qhs_cx_rdpm
= {
819 .name
= "qhs_cx_rdpm",
820 .id
= SM8250_SLAVE_CX_RDPM
,
825 static struct qcom_icc_node qhs_dcc_cfg
= {
826 .name
= "qhs_dcc_cfg",
827 .id
= SM8250_SLAVE_DCC_CFG
,
832 static struct qcom_icc_node qhs_ddrss_cfg
= {
833 .name
= "qhs_ddrss_cfg",
834 .id
= SM8250_SLAVE_CNOC_DDRSS
,
838 .links
= { SM8250_MASTER_CNOC_DC_NOC
},
841 static struct qcom_icc_node qhs_display_cfg
= {
842 .name
= "qhs_display_cfg",
843 .id
= SM8250_SLAVE_DISPLAY_CFG
,
848 static struct qcom_icc_node qhs_gpuss_cfg
= {
849 .name
= "qhs_gpuss_cfg",
850 .id
= SM8250_SLAVE_GRAPHICS_3D_CFG
,
855 static struct qcom_icc_node qhs_imem_cfg
= {
856 .name
= "qhs_imem_cfg",
857 .id
= SM8250_SLAVE_IMEM_CFG
,
862 static struct qcom_icc_node qhs_ipa
= {
864 .id
= SM8250_SLAVE_IPA_CFG
,
869 static struct qcom_icc_node qhs_ipc_router
= {
870 .name
= "qhs_ipc_router",
871 .id
= SM8250_SLAVE_IPC_ROUTER_CFG
,
876 static struct qcom_icc_node qhs_lpass_cfg
= {
877 .name
= "qhs_lpass_cfg",
878 .id
= SM8250_SLAVE_LPASS
,
883 static struct qcom_icc_node qhs_mnoc_cfg
= {
884 .name
= "qhs_mnoc_cfg",
885 .id
= SM8250_SLAVE_CNOC_MNOC_CFG
,
889 .links
= { SM8250_MASTER_CNOC_MNOC_CFG
},
892 static struct qcom_icc_node qhs_npu_cfg
= {
893 .name
= "qhs_npu_cfg",
894 .id
= SM8250_SLAVE_NPU_CFG
,
898 .links
= { SM8250_MASTER_NPU_NOC_CFG
},
901 static struct qcom_icc_node qhs_pcie0_cfg
= {
902 .name
= "qhs_pcie0_cfg",
903 .id
= SM8250_SLAVE_PCIE_0_CFG
,
908 static struct qcom_icc_node qhs_pcie1_cfg
= {
909 .name
= "qhs_pcie1_cfg",
910 .id
= SM8250_SLAVE_PCIE_1_CFG
,
915 static struct qcom_icc_node qhs_pcie_modem_cfg
= {
916 .name
= "qhs_pcie_modem_cfg",
917 .id
= SM8250_SLAVE_PCIE_2_CFG
,
922 static struct qcom_icc_node qhs_pdm
= {
924 .id
= SM8250_SLAVE_PDM
,
929 static struct qcom_icc_node qhs_pimem_cfg
= {
930 .name
= "qhs_pimem_cfg",
931 .id
= SM8250_SLAVE_PIMEM_CFG
,
936 static struct qcom_icc_node qhs_prng
= {
938 .id
= SM8250_SLAVE_PRNG
,
943 static struct qcom_icc_node qhs_qdss_cfg
= {
944 .name
= "qhs_qdss_cfg",
945 .id
= SM8250_SLAVE_QDSS_CFG
,
950 static struct qcom_icc_node qhs_qspi
= {
952 .id
= SM8250_SLAVE_QSPI_0
,
957 static struct qcom_icc_node qhs_qup0
= {
959 .id
= SM8250_SLAVE_QUP_0
,
964 static struct qcom_icc_node qhs_qup1
= {
966 .id
= SM8250_SLAVE_QUP_1
,
971 static struct qcom_icc_node qhs_qup2
= {
973 .id
= SM8250_SLAVE_QUP_2
,
978 static struct qcom_icc_node qhs_sdc2
= {
980 .id
= SM8250_SLAVE_SDCC_2
,
985 static struct qcom_icc_node qhs_sdc4
= {
987 .id
= SM8250_SLAVE_SDCC_4
,
992 static struct qcom_icc_node qhs_snoc_cfg
= {
993 .name
= "qhs_snoc_cfg",
994 .id
= SM8250_SLAVE_SNOC_CFG
,
998 .links
= { SM8250_MASTER_SNOC_CFG
},
1001 static struct qcom_icc_node qhs_tcsr
= {
1003 .id
= SM8250_SLAVE_TCSR
,
1008 static struct qcom_icc_node qhs_tlmm0
= {
1009 .name
= "qhs_tlmm0",
1010 .id
= SM8250_SLAVE_TLMM_NORTH
,
1015 static struct qcom_icc_node qhs_tlmm1
= {
1016 .name
= "qhs_tlmm1",
1017 .id
= SM8250_SLAVE_TLMM_SOUTH
,
1022 static struct qcom_icc_node qhs_tlmm2
= {
1023 .name
= "qhs_tlmm2",
1024 .id
= SM8250_SLAVE_TLMM_WEST
,
1029 static struct qcom_icc_node qhs_tsif
= {
1031 .id
= SM8250_SLAVE_TSIF
,
1036 static struct qcom_icc_node qhs_ufs_card_cfg
= {
1037 .name
= "qhs_ufs_card_cfg",
1038 .id
= SM8250_SLAVE_UFS_CARD_CFG
,
1043 static struct qcom_icc_node qhs_ufs_mem_cfg
= {
1044 .name
= "qhs_ufs_mem_cfg",
1045 .id
= SM8250_SLAVE_UFS_MEM_CFG
,
1050 static struct qcom_icc_node qhs_usb3_0
= {
1051 .name
= "qhs_usb3_0",
1052 .id
= SM8250_SLAVE_USB3
,
1057 static struct qcom_icc_node qhs_usb3_1
= {
1058 .name
= "qhs_usb3_1",
1059 .id
= SM8250_SLAVE_USB3_1
,
1064 static struct qcom_icc_node qhs_venus_cfg
= {
1065 .name
= "qhs_venus_cfg",
1066 .id
= SM8250_SLAVE_VENUS_CFG
,
1071 static struct qcom_icc_node qhs_vsense_ctrl_cfg
= {
1072 .name
= "qhs_vsense_ctrl_cfg",
1073 .id
= SM8250_SLAVE_VSENSE_CTRL_CFG
,
1078 static struct qcom_icc_node qns_cnoc_a2noc
= {
1079 .name
= "qns_cnoc_a2noc",
1080 .id
= SM8250_SLAVE_CNOC_A2NOC
,
1084 .links
= { SM8250_MASTER_CNOC_A2NOC
},
1087 static struct qcom_icc_node srvc_cnoc
= {
1088 .name
= "srvc_cnoc",
1089 .id
= SM8250_SLAVE_SERVICE_CNOC
,
1094 static struct qcom_icc_node qhs_llcc
= {
1096 .id
= SM8250_SLAVE_LLCC_CFG
,
1101 static struct qcom_icc_node qhs_memnoc
= {
1102 .name
= "qhs_memnoc",
1103 .id
= SM8250_SLAVE_GEM_NOC_CFG
,
1107 .links
= { SM8250_MASTER_GEM_NOC_CFG
},
1110 static struct qcom_icc_node qns_gem_noc_snoc
= {
1111 .name
= "qns_gem_noc_snoc",
1112 .id
= SM8250_SLAVE_GEM_NOC_SNOC
,
1116 .links
= { SM8250_MASTER_GEM_NOC_SNOC
},
1119 static struct qcom_icc_node qns_llcc
= {
1121 .id
= SM8250_SLAVE_LLCC
,
1125 .links
= { SM8250_MASTER_LLCC
},
1128 static struct qcom_icc_node qns_sys_pcie
= {
1129 .name
= "qns_sys_pcie",
1130 .id
= SM8250_SLAVE_MEM_NOC_PCIE_SNOC
,
1134 .links
= { SM8250_MASTER_GEM_NOC_PCIE_SNOC
},
1137 static struct qcom_icc_node srvc_even_gemnoc
= {
1138 .name
= "srvc_even_gemnoc",
1139 .id
= SM8250_SLAVE_SERVICE_GEM_NOC_1
,
1144 static struct qcom_icc_node srvc_odd_gemnoc
= {
1145 .name
= "srvc_odd_gemnoc",
1146 .id
= SM8250_SLAVE_SERVICE_GEM_NOC_2
,
1151 static struct qcom_icc_node srvc_sys_gemnoc
= {
1152 .name
= "srvc_sys_gemnoc",
1153 .id
= SM8250_SLAVE_SERVICE_GEM_NOC
,
1158 static struct qcom_icc_node ebi
= {
1160 .id
= SM8250_SLAVE_EBI_CH0
,
1165 static struct qcom_icc_node qns_mem_noc_hf
= {
1166 .name
= "qns_mem_noc_hf",
1167 .id
= SM8250_SLAVE_MNOC_HF_MEM_NOC
,
1171 .links
= { SM8250_MASTER_MNOC_HF_MEM_NOC
},
1174 static struct qcom_icc_node qns_mem_noc_sf
= {
1175 .name
= "qns_mem_noc_sf",
1176 .id
= SM8250_SLAVE_MNOC_SF_MEM_NOC
,
1180 .links
= { SM8250_MASTER_MNOC_SF_MEM_NOC
},
1183 static struct qcom_icc_node srvc_mnoc
= {
1184 .name
= "srvc_mnoc",
1185 .id
= SM8250_SLAVE_SERVICE_MNOC
,
1190 static struct qcom_icc_node qhs_cal_dp0
= {
1191 .name
= "qhs_cal_dp0",
1192 .id
= SM8250_SLAVE_NPU_CAL_DP0
,
1197 static struct qcom_icc_node qhs_cal_dp1
= {
1198 .name
= "qhs_cal_dp1",
1199 .id
= SM8250_SLAVE_NPU_CAL_DP1
,
1204 static struct qcom_icc_node qhs_cp
= {
1206 .id
= SM8250_SLAVE_NPU_CP
,
1211 static struct qcom_icc_node qhs_dma_bwmon
= {
1212 .name
= "qhs_dma_bwmon",
1213 .id
= SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG
,
1218 static struct qcom_icc_node qhs_dpm
= {
1220 .id
= SM8250_SLAVE_NPU_DPM
,
1225 static struct qcom_icc_node qhs_isense
= {
1226 .name
= "qhs_isense",
1227 .id
= SM8250_SLAVE_ISENSE_CFG
,
1232 static struct qcom_icc_node qhs_llm
= {
1234 .id
= SM8250_SLAVE_NPU_LLM_CFG
,
1239 static struct qcom_icc_node qhs_tcm
= {
1241 .id
= SM8250_SLAVE_NPU_TCM
,
1246 static struct qcom_icc_node qns_npu_sys
= {
1247 .name
= "qns_npu_sys",
1248 .id
= SM8250_SLAVE_NPU_COMPUTE_NOC
,
1253 static struct qcom_icc_node srvc_noc
= {
1255 .id
= SM8250_SLAVE_SERVICE_NPU_NOC
,
1260 static struct qcom_icc_node qhs_apss
= {
1262 .id
= SM8250_SLAVE_APPSS
,
1267 static struct qcom_icc_node qns_cnoc
= {
1269 .id
= SM8250_SNOC_CNOC_SLV
,
1273 .links
= { SM8250_SNOC_CNOC_MAS
},
1276 static struct qcom_icc_node qns_gemnoc_gc
= {
1277 .name
= "qns_gemnoc_gc",
1278 .id
= SM8250_SLAVE_SNOC_GEM_NOC_GC
,
1282 .links
= { SM8250_MASTER_SNOC_GC_MEM_NOC
},
1285 static struct qcom_icc_node qns_gemnoc_sf
= {
1286 .name
= "qns_gemnoc_sf",
1287 .id
= SM8250_SLAVE_SNOC_GEM_NOC_SF
,
1291 .links
= { SM8250_MASTER_SNOC_SF_MEM_NOC
},
1294 static struct qcom_icc_node qxs_imem
= {
1296 .id
= SM8250_SLAVE_OCIMEM
,
1301 static struct qcom_icc_node qxs_pimem
= {
1302 .name
= "qxs_pimem",
1303 .id
= SM8250_SLAVE_PIMEM
,
1308 static struct qcom_icc_node srvc_snoc
= {
1309 .name
= "srvc_snoc",
1310 .id
= SM8250_SLAVE_SERVICE_SNOC
,
1315 static struct qcom_icc_node xs_pcie_0
= {
1316 .name
= "xs_pcie_0",
1317 .id
= SM8250_SLAVE_PCIE_0
,
1322 static struct qcom_icc_node xs_pcie_1
= {
1323 .name
= "xs_pcie_1",
1324 .id
= SM8250_SLAVE_PCIE_1
,
1329 static struct qcom_icc_node xs_pcie_modem
= {
1330 .name
= "xs_pcie_modem",
1331 .id
= SM8250_SLAVE_PCIE_2
,
1336 static struct qcom_icc_node xs_qdss_stm
= {
1337 .name
= "xs_qdss_stm",
1338 .id
= SM8250_SLAVE_QDSS_STM
,
1343 static struct qcom_icc_node xs_sys_tcu_cfg
= {
1344 .name
= "xs_sys_tcu_cfg",
1345 .id
= SM8250_SLAVE_TCU
,
1350 static struct qcom_icc_node qup0_core_master
= {
1351 .name
= "qup0_core_master",
1352 .id
= SM8250_MASTER_QUP_CORE_0
,
1356 .links
= { SM8250_SLAVE_QUP_CORE_0
},
1359 static struct qcom_icc_node qup1_core_master
= {
1360 .name
= "qup1_core_master",
1361 .id
= SM8250_MASTER_QUP_CORE_1
,
1365 .links
= { SM8250_SLAVE_QUP_CORE_1
},
1368 static struct qcom_icc_node qup2_core_master
= {
1369 .name
= "qup2_core_master",
1370 .id
= SM8250_MASTER_QUP_CORE_2
,
1374 .links
= { SM8250_SLAVE_QUP_CORE_2
},
1377 static struct qcom_icc_node qup0_core_slave
= {
1378 .name
= "qup0_core_slave",
1379 .id
= SM8250_SLAVE_QUP_CORE_0
,
1384 static struct qcom_icc_node qup1_core_slave
= {
1385 .name
= "qup1_core_slave",
1386 .id
= SM8250_SLAVE_QUP_CORE_1
,
1391 static struct qcom_icc_node qup2_core_slave
= {
1392 .name
= "qup2_core_slave",
1393 .id
= SM8250_SLAVE_QUP_CORE_2
,
1398 static struct qcom_icc_bcm bcm_acv
= {
1400 .enable_mask
= BIT(3),
1406 static struct qcom_icc_bcm bcm_mc0
= {
1413 static struct qcom_icc_bcm bcm_sh0
= {
1417 .nodes
= { &qns_llcc
},
1420 static struct qcom_icc_bcm bcm_mm0
= {
1424 .nodes
= { &qns_mem_noc_hf
},
1427 static struct qcom_icc_bcm bcm_ce0
= {
1431 .nodes
= { &qxm_crypto
},
1434 static struct qcom_icc_bcm bcm_mm1
= {
1438 .nodes
= { &qnm_camnoc_hf
, &qxm_mdp0
, &qxm_mdp1
},
1441 static struct qcom_icc_bcm bcm_sh2
= {
1445 .nodes
= { &alm_gpu_tcu
, &alm_sys_tcu
},
1448 static struct qcom_icc_bcm bcm_mm2
= {
1452 .nodes
= { &qns_mem_noc_sf
},
1455 static struct qcom_icc_bcm bcm_qup0
= {
1459 .nodes
= { &qup0_core_master
, &qup1_core_master
, &qup2_core_master
},
1462 static struct qcom_icc_bcm bcm_sh3
= {
1466 .nodes
= { &qnm_cmpnoc
},
1469 static struct qcom_icc_bcm bcm_mm3
= {
1473 .nodes
= { &qnm_camnoc_icp
, &qnm_camnoc_sf
, &qnm_video0
, &qnm_video1
, &qnm_video_cvp
},
1476 static struct qcom_icc_bcm bcm_sh4
= {
1480 .nodes
= { &chm_apps
},
1483 static struct qcom_icc_bcm bcm_sn0
= {
1487 .nodes
= { &qns_gemnoc_sf
},
1490 static struct qcom_icc_bcm bcm_co0
= {
1494 .nodes
= { &qns_cdsp_mem_noc
},
1497 static struct qcom_icc_bcm bcm_cn0
= {
1501 .nodes
= { &qnm_snoc
,
1528 &qhs_pcie_modem_cfg
,
1550 &qhs_vsense_ctrl_cfg
,
1556 static struct qcom_icc_bcm bcm_sn1
= {
1560 .nodes
= { &qxs_imem
},
1563 static struct qcom_icc_bcm bcm_sn2
= {
1567 .nodes
= { &qns_gemnoc_gc
},
1570 static struct qcom_icc_bcm bcm_co2
= {
1574 .nodes
= { &qnm_npu
},
1577 static struct qcom_icc_bcm bcm_sn3
= {
1581 .nodes
= { &qxs_pimem
},
1584 static struct qcom_icc_bcm bcm_sn4
= {
1588 .nodes
= { &xs_qdss_stm
},
1591 static struct qcom_icc_bcm bcm_sn5
= {
1595 .nodes
= { &xs_pcie_modem
},
1598 static struct qcom_icc_bcm bcm_sn6
= {
1602 .nodes
= { &xs_pcie_0
, &xs_pcie_1
},
1605 static struct qcom_icc_bcm bcm_sn7
= {
1609 .nodes
= { &qnm_aggre1_noc
},
1612 static struct qcom_icc_bcm bcm_sn8
= {
1616 .nodes
= { &qnm_aggre2_noc
},
1619 static struct qcom_icc_bcm bcm_sn9
= {
1623 .nodes
= { &qnm_gemnoc_pcie
},
1626 static struct qcom_icc_bcm bcm_sn11
= {
1630 .nodes
= { &qnm_gemnoc
},
1633 static struct qcom_icc_bcm bcm_sn12
= {
1637 .nodes
= { &qns_pcie_modem_mem_noc
, &qns_pcie_mem_noc
},
1640 static struct qcom_icc_bcm
* const aggre1_noc_bcms
[] = {
1644 static struct qcom_icc_node
* const aggre1_noc_nodes
[] = {
1645 [MASTER_A1NOC_CFG
] = &qhm_a1noc_cfg
,
1646 [MASTER_QSPI_0
] = &qhm_qspi
,
1647 [MASTER_QUP_1
] = &qhm_qup1
,
1648 [MASTER_QUP_2
] = &qhm_qup2
,
1649 [MASTER_TSIF
] = &qhm_tsif
,
1650 [MASTER_PCIE_2
] = &xm_pcie3_modem
,
1651 [MASTER_SDCC_4
] = &xm_sdc4
,
1652 [MASTER_UFS_MEM
] = &xm_ufs_mem
,
1653 [MASTER_USB3
] = &xm_usb3_0
,
1654 [MASTER_USB3_1
] = &xm_usb3_1
,
1655 [A1NOC_SNOC_SLV
] = &qns_a1noc_snoc
,
1656 [SLAVE_ANOC_PCIE_GEM_NOC_1
] = &qns_pcie_modem_mem_noc
,
1657 [SLAVE_SERVICE_A1NOC
] = &srvc_aggre1_noc
,
1660 static const struct qcom_icc_desc sm8250_aggre1_noc
= {
1661 .nodes
= aggre1_noc_nodes
,
1662 .num_nodes
= ARRAY_SIZE(aggre1_noc_nodes
),
1663 .bcms
= aggre1_noc_bcms
,
1664 .num_bcms
= ARRAY_SIZE(aggre1_noc_bcms
),
1667 static struct qcom_icc_bcm
* const aggre2_noc_bcms
[] = {
1672 static struct qcom_icc_bcm
* const qup_virt_bcms
[] = {
1676 static struct qcom_icc_node
* const qup_virt_nodes
[] = {
1677 [MASTER_QUP_CORE_0
] = &qup0_core_master
,
1678 [MASTER_QUP_CORE_1
] = &qup1_core_master
,
1679 [MASTER_QUP_CORE_2
] = &qup2_core_master
,
1680 [SLAVE_QUP_CORE_0
] = &qup0_core_slave
,
1681 [SLAVE_QUP_CORE_1
] = &qup1_core_slave
,
1682 [SLAVE_QUP_CORE_2
] = &qup2_core_slave
,
1685 static const struct qcom_icc_desc sm8250_qup_virt
= {
1686 .nodes
= qup_virt_nodes
,
1687 .num_nodes
= ARRAY_SIZE(qup_virt_nodes
),
1688 .bcms
= qup_virt_bcms
,
1689 .num_bcms
= ARRAY_SIZE(qup_virt_bcms
),
1692 static struct qcom_icc_node
* const aggre2_noc_nodes
[] = {
1693 [MASTER_A2NOC_CFG
] = &qhm_a2noc_cfg
,
1694 [MASTER_QDSS_BAM
] = &qhm_qdss_bam
,
1695 [MASTER_QUP_0
] = &qhm_qup0
,
1696 [MASTER_CNOC_A2NOC
] = &qnm_cnoc
,
1697 [MASTER_CRYPTO_CORE_0
] = &qxm_crypto
,
1698 [MASTER_IPA
] = &qxm_ipa
,
1699 [MASTER_PCIE
] = &xm_pcie3_0
,
1700 [MASTER_PCIE_1
] = &xm_pcie3_1
,
1701 [MASTER_QDSS_ETR
] = &xm_qdss_etr
,
1702 [MASTER_SDCC_2
] = &xm_sdc2
,
1703 [MASTER_UFS_CARD
] = &xm_ufs_card
,
1704 [A2NOC_SNOC_SLV
] = &qns_a2noc_snoc
,
1705 [SLAVE_ANOC_PCIE_GEM_NOC
] = &qns_pcie_mem_noc
,
1706 [SLAVE_SERVICE_A2NOC
] = &srvc_aggre2_noc
,
1709 static const struct qcom_icc_desc sm8250_aggre2_noc
= {
1710 .nodes
= aggre2_noc_nodes
,
1711 .num_nodes
= ARRAY_SIZE(aggre2_noc_nodes
),
1712 .bcms
= aggre2_noc_bcms
,
1713 .num_bcms
= ARRAY_SIZE(aggre2_noc_bcms
),
1716 static struct qcom_icc_bcm
* const compute_noc_bcms
[] = {
1721 static struct qcom_icc_node
* const compute_noc_nodes
[] = {
1722 [MASTER_NPU
] = &qnm_npu
,
1723 [SLAVE_CDSP_MEM_NOC
] = &qns_cdsp_mem_noc
,
1726 static const struct qcom_icc_desc sm8250_compute_noc
= {
1727 .nodes
= compute_noc_nodes
,
1728 .num_nodes
= ARRAY_SIZE(compute_noc_nodes
),
1729 .bcms
= compute_noc_bcms
,
1730 .num_bcms
= ARRAY_SIZE(compute_noc_bcms
),
1733 static struct qcom_icc_bcm
* const config_noc_bcms
[] = {
1737 static struct qcom_icc_node
* const config_noc_nodes
[] = {
1738 [SNOC_CNOC_MAS
] = &qnm_snoc
,
1739 [MASTER_QDSS_DAP
] = &xm_qdss_dap
,
1740 [SLAVE_A1NOC_CFG
] = &qhs_a1_noc_cfg
,
1741 [SLAVE_A2NOC_CFG
] = &qhs_a2_noc_cfg
,
1742 [SLAVE_AHB2PHY_SOUTH
] = &qhs_ahb2phy0
,
1743 [SLAVE_AHB2PHY_NORTH
] = &qhs_ahb2phy1
,
1744 [SLAVE_AOSS
] = &qhs_aoss
,
1745 [SLAVE_CAMERA_CFG
] = &qhs_camera_cfg
,
1746 [SLAVE_CLK_CTL
] = &qhs_clk_ctl
,
1747 [SLAVE_CDSP_CFG
] = &qhs_compute_dsp
,
1748 [SLAVE_RBCPR_CX_CFG
] = &qhs_cpr_cx
,
1749 [SLAVE_RBCPR_MMCX_CFG
] = &qhs_cpr_mmcx
,
1750 [SLAVE_RBCPR_MX_CFG
] = &qhs_cpr_mx
,
1751 [SLAVE_CRYPTO_0_CFG
] = &qhs_crypto0_cfg
,
1752 [SLAVE_CX_RDPM
] = &qhs_cx_rdpm
,
1753 [SLAVE_DCC_CFG
] = &qhs_dcc_cfg
,
1754 [SLAVE_CNOC_DDRSS
] = &qhs_ddrss_cfg
,
1755 [SLAVE_DISPLAY_CFG
] = &qhs_display_cfg
,
1756 [SLAVE_GRAPHICS_3D_CFG
] = &qhs_gpuss_cfg
,
1757 [SLAVE_IMEM_CFG
] = &qhs_imem_cfg
,
1758 [SLAVE_IPA_CFG
] = &qhs_ipa
,
1759 [SLAVE_IPC_ROUTER_CFG
] = &qhs_ipc_router
,
1760 [SLAVE_LPASS
] = &qhs_lpass_cfg
,
1761 [SLAVE_CNOC_MNOC_CFG
] = &qhs_mnoc_cfg
,
1762 [SLAVE_NPU_CFG
] = &qhs_npu_cfg
,
1763 [SLAVE_PCIE_0_CFG
] = &qhs_pcie0_cfg
,
1764 [SLAVE_PCIE_1_CFG
] = &qhs_pcie1_cfg
,
1765 [SLAVE_PCIE_2_CFG
] = &qhs_pcie_modem_cfg
,
1766 [SLAVE_PDM
] = &qhs_pdm
,
1767 [SLAVE_PIMEM_CFG
] = &qhs_pimem_cfg
,
1768 [SLAVE_PRNG
] = &qhs_prng
,
1769 [SLAVE_QDSS_CFG
] = &qhs_qdss_cfg
,
1770 [SLAVE_QSPI_0
] = &qhs_qspi
,
1771 [SLAVE_QUP_0
] = &qhs_qup0
,
1772 [SLAVE_QUP_1
] = &qhs_qup1
,
1773 [SLAVE_QUP_2
] = &qhs_qup2
,
1774 [SLAVE_SDCC_2
] = &qhs_sdc2
,
1775 [SLAVE_SDCC_4
] = &qhs_sdc4
,
1776 [SLAVE_SNOC_CFG
] = &qhs_snoc_cfg
,
1777 [SLAVE_TCSR
] = &qhs_tcsr
,
1778 [SLAVE_TLMM_NORTH
] = &qhs_tlmm0
,
1779 [SLAVE_TLMM_SOUTH
] = &qhs_tlmm1
,
1780 [SLAVE_TLMM_WEST
] = &qhs_tlmm2
,
1781 [SLAVE_TSIF
] = &qhs_tsif
,
1782 [SLAVE_UFS_CARD_CFG
] = &qhs_ufs_card_cfg
,
1783 [SLAVE_UFS_MEM_CFG
] = &qhs_ufs_mem_cfg
,
1784 [SLAVE_USB3
] = &qhs_usb3_0
,
1785 [SLAVE_USB3_1
] = &qhs_usb3_1
,
1786 [SLAVE_VENUS_CFG
] = &qhs_venus_cfg
,
1787 [SLAVE_VSENSE_CTRL_CFG
] = &qhs_vsense_ctrl_cfg
,
1788 [SLAVE_CNOC_A2NOC
] = &qns_cnoc_a2noc
,
1789 [SLAVE_SERVICE_CNOC
] = &srvc_cnoc
,
1792 static const struct qcom_icc_desc sm8250_config_noc
= {
1793 .nodes
= config_noc_nodes
,
1794 .num_nodes
= ARRAY_SIZE(config_noc_nodes
),
1795 .bcms
= config_noc_bcms
,
1796 .num_bcms
= ARRAY_SIZE(config_noc_bcms
),
1799 static struct qcom_icc_bcm
* const dc_noc_bcms
[] = {
1802 static struct qcom_icc_node
* const dc_noc_nodes
[] = {
1803 [MASTER_CNOC_DC_NOC
] = &qhm_cnoc_dc_noc
,
1804 [SLAVE_LLCC_CFG
] = &qhs_llcc
,
1805 [SLAVE_GEM_NOC_CFG
] = &qhs_memnoc
,
1808 static const struct qcom_icc_desc sm8250_dc_noc
= {
1809 .nodes
= dc_noc_nodes
,
1810 .num_nodes
= ARRAY_SIZE(dc_noc_nodes
),
1811 .bcms
= dc_noc_bcms
,
1812 .num_bcms
= ARRAY_SIZE(dc_noc_bcms
),
1815 static struct qcom_icc_bcm
* const gem_noc_bcms
[] = {
1822 static struct qcom_icc_node
* const gem_noc_nodes
[] = {
1823 [MASTER_GPU_TCU
] = &alm_gpu_tcu
,
1824 [MASTER_SYS_TCU
] = &alm_sys_tcu
,
1825 [MASTER_AMPSS_M0
] = &chm_apps
,
1826 [MASTER_GEM_NOC_CFG
] = &qhm_gemnoc_cfg
,
1827 [MASTER_COMPUTE_NOC
] = &qnm_cmpnoc
,
1828 [MASTER_GRAPHICS_3D
] = &qnm_gpu
,
1829 [MASTER_MNOC_HF_MEM_NOC
] = &qnm_mnoc_hf
,
1830 [MASTER_MNOC_SF_MEM_NOC
] = &qnm_mnoc_sf
,
1831 [MASTER_ANOC_PCIE_GEM_NOC
] = &qnm_pcie
,
1832 [MASTER_SNOC_GC_MEM_NOC
] = &qnm_snoc_gc
,
1833 [MASTER_SNOC_SF_MEM_NOC
] = &qnm_snoc_sf
,
1834 [SLAVE_GEM_NOC_SNOC
] = &qns_gem_noc_snoc
,
1835 [SLAVE_LLCC
] = &qns_llcc
,
1836 [SLAVE_MEM_NOC_PCIE_SNOC
] = &qns_sys_pcie
,
1837 [SLAVE_SERVICE_GEM_NOC_1
] = &srvc_even_gemnoc
,
1838 [SLAVE_SERVICE_GEM_NOC_2
] = &srvc_odd_gemnoc
,
1839 [SLAVE_SERVICE_GEM_NOC
] = &srvc_sys_gemnoc
,
1842 static const struct qcom_icc_desc sm8250_gem_noc
= {
1843 .nodes
= gem_noc_nodes
,
1844 .num_nodes
= ARRAY_SIZE(gem_noc_nodes
),
1845 .bcms
= gem_noc_bcms
,
1846 .num_bcms
= ARRAY_SIZE(gem_noc_bcms
),
1849 static struct qcom_icc_bcm
* const mc_virt_bcms
[] = {
1854 static struct qcom_icc_node
* const mc_virt_nodes
[] = {
1855 [MASTER_LLCC
] = &llcc_mc
,
1856 [SLAVE_EBI_CH0
] = &ebi
,
1859 static const struct qcom_icc_desc sm8250_mc_virt
= {
1860 .nodes
= mc_virt_nodes
,
1861 .num_nodes
= ARRAY_SIZE(mc_virt_nodes
),
1862 .bcms
= mc_virt_bcms
,
1863 .num_bcms
= ARRAY_SIZE(mc_virt_bcms
),
1866 static struct qcom_icc_bcm
* const mmss_noc_bcms
[] = {
1873 static struct qcom_icc_node
* const mmss_noc_nodes
[] = {
1874 [MASTER_CNOC_MNOC_CFG
] = &qhm_mnoc_cfg
,
1875 [MASTER_CAMNOC_HF
] = &qnm_camnoc_hf
,
1876 [MASTER_CAMNOC_ICP
] = &qnm_camnoc_icp
,
1877 [MASTER_CAMNOC_SF
] = &qnm_camnoc_sf
,
1878 [MASTER_VIDEO_P0
] = &qnm_video0
,
1879 [MASTER_VIDEO_P1
] = &qnm_video1
,
1880 [MASTER_VIDEO_PROC
] = &qnm_video_cvp
,
1881 [MASTER_MDP_PORT0
] = &qxm_mdp0
,
1882 [MASTER_MDP_PORT1
] = &qxm_mdp1
,
1883 [MASTER_ROTATOR
] = &qxm_rot
,
1884 [SLAVE_MNOC_HF_MEM_NOC
] = &qns_mem_noc_hf
,
1885 [SLAVE_MNOC_SF_MEM_NOC
] = &qns_mem_noc_sf
,
1886 [SLAVE_SERVICE_MNOC
] = &srvc_mnoc
,
1889 static const struct qcom_icc_desc sm8250_mmss_noc
= {
1890 .nodes
= mmss_noc_nodes
,
1891 .num_nodes
= ARRAY_SIZE(mmss_noc_nodes
),
1892 .bcms
= mmss_noc_bcms
,
1893 .num_bcms
= ARRAY_SIZE(mmss_noc_bcms
),
1896 static struct qcom_icc_bcm
* const npu_noc_bcms
[] = {
1899 static struct qcom_icc_node
* const npu_noc_nodes
[] = {
1900 [MASTER_NPU_SYS
] = &amm_npu_sys
,
1901 [MASTER_NPU_CDP
] = &amm_npu_sys_cdp_w
,
1902 [MASTER_NPU_NOC_CFG
] = &qhm_cfg
,
1903 [SLAVE_NPU_CAL_DP0
] = &qhs_cal_dp0
,
1904 [SLAVE_NPU_CAL_DP1
] = &qhs_cal_dp1
,
1905 [SLAVE_NPU_CP
] = &qhs_cp
,
1906 [SLAVE_NPU_INT_DMA_BWMON_CFG
] = &qhs_dma_bwmon
,
1907 [SLAVE_NPU_DPM
] = &qhs_dpm
,
1908 [SLAVE_ISENSE_CFG
] = &qhs_isense
,
1909 [SLAVE_NPU_LLM_CFG
] = &qhs_llm
,
1910 [SLAVE_NPU_TCM
] = &qhs_tcm
,
1911 [SLAVE_NPU_COMPUTE_NOC
] = &qns_npu_sys
,
1912 [SLAVE_SERVICE_NPU_NOC
] = &srvc_noc
,
1915 static const struct qcom_icc_desc sm8250_npu_noc
= {
1916 .nodes
= npu_noc_nodes
,
1917 .num_nodes
= ARRAY_SIZE(npu_noc_nodes
),
1918 .bcms
= npu_noc_bcms
,
1919 .num_bcms
= ARRAY_SIZE(npu_noc_bcms
),
1922 static struct qcom_icc_bcm
* const system_noc_bcms
[] = {
1936 static struct qcom_icc_node
* const system_noc_nodes
[] = {
1937 [MASTER_SNOC_CFG
] = &qhm_snoc_cfg
,
1938 [A1NOC_SNOC_MAS
] = &qnm_aggre1_noc
,
1939 [A2NOC_SNOC_MAS
] = &qnm_aggre2_noc
,
1940 [MASTER_GEM_NOC_SNOC
] = &qnm_gemnoc
,
1941 [MASTER_GEM_NOC_PCIE_SNOC
] = &qnm_gemnoc_pcie
,
1942 [MASTER_PIMEM
] = &qxm_pimem
,
1943 [MASTER_GIC
] = &xm_gic
,
1944 [SLAVE_APPSS
] = &qhs_apss
,
1945 [SNOC_CNOC_SLV
] = &qns_cnoc
,
1946 [SLAVE_SNOC_GEM_NOC_GC
] = &qns_gemnoc_gc
,
1947 [SLAVE_SNOC_GEM_NOC_SF
] = &qns_gemnoc_sf
,
1948 [SLAVE_OCIMEM
] = &qxs_imem
,
1949 [SLAVE_PIMEM
] = &qxs_pimem
,
1950 [SLAVE_SERVICE_SNOC
] = &srvc_snoc
,
1951 [SLAVE_PCIE_0
] = &xs_pcie_0
,
1952 [SLAVE_PCIE_1
] = &xs_pcie_1
,
1953 [SLAVE_PCIE_2
] = &xs_pcie_modem
,
1954 [SLAVE_QDSS_STM
] = &xs_qdss_stm
,
1955 [SLAVE_TCU
] = &xs_sys_tcu_cfg
,
1958 static const struct qcom_icc_desc sm8250_system_noc
= {
1959 .nodes
= system_noc_nodes
,
1960 .num_nodes
= ARRAY_SIZE(system_noc_nodes
),
1961 .bcms
= system_noc_bcms
,
1962 .num_bcms
= ARRAY_SIZE(system_noc_bcms
),
1965 static const struct of_device_id qnoc_of_match
[] = {
1966 { .compatible
= "qcom,sm8250-aggre1-noc",
1967 .data
= &sm8250_aggre1_noc
},
1968 { .compatible
= "qcom,sm8250-aggre2-noc",
1969 .data
= &sm8250_aggre2_noc
},
1970 { .compatible
= "qcom,sm8250-compute-noc",
1971 .data
= &sm8250_compute_noc
},
1972 { .compatible
= "qcom,sm8250-config-noc",
1973 .data
= &sm8250_config_noc
},
1974 { .compatible
= "qcom,sm8250-dc-noc",
1975 .data
= &sm8250_dc_noc
},
1976 { .compatible
= "qcom,sm8250-gem-noc",
1977 .data
= &sm8250_gem_noc
},
1978 { .compatible
= "qcom,sm8250-mc-virt",
1979 .data
= &sm8250_mc_virt
},
1980 { .compatible
= "qcom,sm8250-mmss-noc",
1981 .data
= &sm8250_mmss_noc
},
1982 { .compatible
= "qcom,sm8250-npu-noc",
1983 .data
= &sm8250_npu_noc
},
1984 { .compatible
= "qcom,sm8250-qup-virt",
1985 .data
= &sm8250_qup_virt
},
1986 { .compatible
= "qcom,sm8250-system-noc",
1987 .data
= &sm8250_system_noc
},
1990 MODULE_DEVICE_TABLE(of
, qnoc_of_match
);
1992 static struct platform_driver qnoc_driver
= {
1993 .probe
= qcom_icc_rpmh_probe
,
1994 .remove
= qcom_icc_rpmh_remove
,
1996 .name
= "qnoc-sm8250",
1997 .of_match_table
= qnoc_of_match
,
1998 .sync_state
= icc_sync_state
,
2001 module_platform_driver(qnoc_driver
);
2003 MODULE_DESCRIPTION("Qualcomm SM8250 NoC driver");
2004 MODULE_LICENSE("GPL v2");