?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Revert "unicode: Don't special case ignorable code points"
[linux.git] / drivers / net / dsa / mv88e6xxx / port.c
blobdc777ddce1f3d954381ccdc27491f0ca2624f2ce
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88E6xxx Switch Port Registers support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/if_bridge.h>
13 #include <linux/phy.h>
14 #include <linux/phylink.h>
15 #include <linux/property.h>
16
17 #include "chip.h"
18 #include "global2.h"
19 #include "port.h"
20 #include "serdes.h"
21
22 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
23 u16 *val)
24 {
25 int addr = chip->info->port_base_addr + port;
26
27 return mv88e6xxx_read(chip, addr, reg, val);
28 }
29
30 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg,
31 int bit, int val)
32 {
33 int addr = chip->info->port_base_addr + port;
34
35 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val);
36 }
37
38 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
39 u16 val)
40 {
41 int addr = chip->info->port_base_addr + port;
42
43 return mv88e6xxx_write(chip, addr, reg, val);
44 }
45
46 /* Offset 0x00: MAC (or PCS or Physical) Status Register
47 *
48 * For most devices, this is read only. However the 6185 has the MyPause
49 * bit read/write.
50 */
51 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
52 int pause)
53 {
54 u16 reg;
55 int err;
56
57 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
58 if (err)
59 return err;
60
61 if (pause)
62 reg |= MV88E6XXX_PORT_STS_MY_PAUSE;
63 else
64 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE;
65
66 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
67 }
68
69 /* Offset 0x01: MAC (or PCS or Physical) Control Register
70 *
71 * Link, Duplex and Flow Control have one force bit, one value bit.
72 *
73 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
74 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
75 * Newer chips need a ForcedSpd bit 13 set to consider the value.
76 */
77
78 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
79 phy_interface_t mode)
80 {
81 u16 reg;
82 int err;
83
84 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
85 if (err)
86 return err;
87
88 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
89 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK);
90
91 switch (mode) {
92 case PHY_INTERFACE_MODE_RGMII_RXID:
93 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
94 break;
95 case PHY_INTERFACE_MODE_RGMII_TXID:
96 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
97 break;
98 case PHY_INTERFACE_MODE_RGMII_ID:
99 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
100 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
101 break;
102 case PHY_INTERFACE_MODE_RGMII:
103 break;
104 default:
105 return 0;
106 }
107
108 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
109 if (err)
110 return err;
111
112 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
113 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
114 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
115
116 return 0;
117 }
118
119 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
120 phy_interface_t mode)
121 {
122 if (port < 5)
123 return -EOPNOTSUPP;
124
125 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
126 }
127
128 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
129 phy_interface_t mode)
130 {
131 if (port != 0)
132 return -EOPNOTSUPP;
133
134 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
135 }
136
137 int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
138 phy_interface_t mode)
139 {
140 if (port != 2 && port != 5 && port != 6)
141 return -EOPNOTSUPP;
142
143 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
144 }
145
146 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
147 {
148 u16 reg;
149 int err;
150
151 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
152 if (err)
153 return err;
154
155 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
156 MV88E6XXX_PORT_MAC_CTL_LINK_UP);
157
158 switch (link) {
159 case LINK_FORCED_DOWN:
160 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
161 break;
162 case LINK_FORCED_UP:
163 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
164 MV88E6XXX_PORT_MAC_CTL_LINK_UP;
165 break;
166 case LINK_UNFORCED:
167 /* normal link detection */
168 break;
169 default:
170 return -EINVAL;
171 }
172
173 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
174 if (err)
175 return err;
176
177 dev_dbg(chip->dev, "p%d: %s link %s\n", port,
178 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
179 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
180
181 return 0;
182 }
183
184 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
185 {
186 const struct mv88e6xxx_ops *ops = chip->info->ops;
187 int err = 0;
188 int link;
189
190 if (isup)
191 link = LINK_FORCED_UP;
192 else
193 link = LINK_FORCED_DOWN;
194
195 if (ops->port_set_link)
196 err = ops->port_set_link(chip, port, link);
197
198 return err;
199 }
200
201 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
202 {
203 const struct mv88e6xxx_ops *ops = chip->info->ops;
204 int err = 0;
205 int link;
206
207 if (mode == MLO_AN_INBAND)
208 link = LINK_UNFORCED;
209 else if (isup)
210 link = LINK_FORCED_UP;
211 else
212 link = LINK_FORCED_DOWN;
213
214 if (ops->port_set_link)
215 err = ops->port_set_link(chip, port, link);
216
217 return err;
218 }
219
220 static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip,
221 int port, int speed, bool alt_bit,
222 bool force_bit, int duplex)
223 {
224 u16 reg, ctrl;
225 int err;
226
227 switch (speed) {
228 case 10:
229 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
230 break;
231 case 100:
232 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
233 break;
234 case 200:
235 if (alt_bit)
236 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
237 MV88E6390_PORT_MAC_CTL_ALTSPEED;
238 else
239 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200;
240 break;
241 case 1000:
242 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
243 break;
244 case 2500:
245 if (alt_bit)
246 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
247 MV88E6390_PORT_MAC_CTL_ALTSPEED;
248 else
249 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000;
250 break;
251 case 10000:
252 /* all bits set, fall through... */
253 case SPEED_UNFORCED:
254 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
255 break;
256 default:
257 return -EOPNOTSUPP;
258 }
259
260 switch (duplex) {
261 case DUPLEX_HALF:
262 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
263 break;
264 case DUPLEX_FULL:
265 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
266 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
267 break;
268 case DUPLEX_UNFORCED:
269 /* normal duplex detection */
270 break;
271 default:
272 return -EOPNOTSUPP;
273 }
274
275 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
276 if (err)
277 return err;
278
279 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
280 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
281 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL);
282
283 if (alt_bit)
284 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
285 if (force_bit) {
286 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
287 if (speed != SPEED_UNFORCED)
288 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
289 }
290 reg |= ctrl;
291
292 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
293 if (err)
294 return err;
295
296 if (speed != SPEED_UNFORCED)
297 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
298 else
299 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
300 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
301 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
302 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
303
304 return 0;
305 }
306
307 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
308 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
309 int speed, int duplex)
310 {
311 if (speed == 200 || speed > 1000)
312 return -EOPNOTSUPP;
313
314 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
315 duplex);
316 }
317
318 /* Support 10, 100 Mbps (e.g. 88E6250 family) */
319 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
320 int speed, int duplex)
321 {
322 if (speed > 100)
323 return -EOPNOTSUPP;
324
325 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
326 duplex);
327 }
328
329 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */
330 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
331 int speed, int duplex)
332 {
333 if (speed > 2500)
334 return -EOPNOTSUPP;
335
336 if (speed == 200 && port != 0)
337 return -EOPNOTSUPP;
338
339 if (speed == 2500 && port < 5)
340 return -EOPNOTSUPP;
341
342 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true,
343 duplex);
344 }
345
346 phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip,
347 int port)
348 {
349 if (port == 5)
350 return PHY_INTERFACE_MODE_2500BASEX;
351
352 return PHY_INTERFACE_MODE_NA;
353 }
354
355 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
356 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
357 int speed, int duplex)
358 {
359 if (speed > 1000)
360 return -EOPNOTSUPP;
361
362 if (speed == 200 && port < 5)
363 return -EOPNOTSUPP;
364
365 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false,
366 duplex);
367 }
368
369 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
370 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
371 int speed, int duplex)
372 {
373 if (speed > 2500)
374 return -EOPNOTSUPP;
375
376 if (speed == 200 && port != 0)
377 return -EOPNOTSUPP;
378
379 if (speed == 2500 && port < 9)
380 return -EOPNOTSUPP;
381
382 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
383 duplex);
384 }
385
386 phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip,
387 int port)
388 {
389 if (port == 9 || port == 10)
390 return PHY_INTERFACE_MODE_2500BASEX;
391
392 return PHY_INTERFACE_MODE_NA;
393 }
394
395 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
396 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
397 int speed, int duplex)
398 {
399 if (speed == 200 && port != 0)
400 return -EOPNOTSUPP;
401
402 if (speed >= 2500 && port < 9)
403 return -EOPNOTSUPP;
404
405 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
406 duplex);
407 }
408
409 phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
410 int port)
411 {
412 if (port == 9 || port == 10)
413 return PHY_INTERFACE_MODE_XAUI;
414
415 return PHY_INTERFACE_MODE_NA;
416 }
417
418 /* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X)
419 * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register
420 * values for speeds 2500 & 5000 conflict.
421 */
422 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
423 int speed, int duplex)
424 {
425 u16 reg, ctrl;
426 int err;
427
428 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 &&
429 speed > 2500)
430 return -EOPNOTSUPP;
431
432 if (speed == 200 && port != 0)
433 return -EOPNOTSUPP;
434
435 if (speed >= 2500 && port > 0 && port < 9)
436 return -EOPNOTSUPP;
437
438 switch (speed) {
439 case 10:
440 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
441 break;
442 case 100:
443 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
444 break;
445 case 200:
446 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
447 MV88E6390_PORT_MAC_CTL_ALTSPEED;
448 break;
449 case 1000:
450 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
451 break;
452 case 2500:
453 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000 |
454 MV88E6390_PORT_MAC_CTL_ALTSPEED;
455 break;
456 case 5000:
457 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
458 MV88E6390_PORT_MAC_CTL_ALTSPEED;
459 break;
460 case 10000:
461 case SPEED_UNFORCED:
462 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
463 break;
464 default:
465 return -EOPNOTSUPP;
466 }
467
468 switch (duplex) {
469 case DUPLEX_HALF:
470 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
471 break;
472 case DUPLEX_FULL:
473 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
474 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
475 break;
476 case DUPLEX_UNFORCED:
477 /* normal duplex detection */
478 break;
479 default:
480 return -EOPNOTSUPP;
481 }
482
483 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
484 if (err)
485 return err;
486
487 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
488 MV88E6390_PORT_MAC_CTL_ALTSPEED |
489 MV88E6390_PORT_MAC_CTL_FORCE_SPEED);
490
491 if (speed != SPEED_UNFORCED)
492 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
493
494 reg |= ctrl;
495
496 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
497 if (err)
498 return err;
499
500 if (speed != SPEED_UNFORCED)
501 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
502 else
503 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
504 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
505 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
506 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
507
508 return 0;
509 }
510
511 phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
512 int port)
513 {
514
515 if (port != 0 && port != 9 && port != 10)
516 return PHY_INTERFACE_MODE_NA;
517
518 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361)
519 return PHY_INTERFACE_MODE_2500BASEX;
520
521 return PHY_INTERFACE_MODE_10GBASER;
522 }
523
524 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
525 phy_interface_t mode, bool force)
526 {
527 u16 cmode;
528 u16 reg;
529 int err;
530
531 /* Default to a slow mode, so freeing up SERDES interfaces for
532 * other ports which might use them for SFPs.
533 */
534 if (mode == PHY_INTERFACE_MODE_NA)
535 mode = PHY_INTERFACE_MODE_1000BASEX;
536
537 switch (mode) {
538 case PHY_INTERFACE_MODE_RMII:
539 cmode = MV88E6XXX_PORT_STS_CMODE_RMII;
540 break;
541 case PHY_INTERFACE_MODE_RGMII:
542 case PHY_INTERFACE_MODE_RGMII_ID:
543 case PHY_INTERFACE_MODE_RGMII_RXID:
544 case PHY_INTERFACE_MODE_RGMII_TXID:
545 cmode = MV88E6XXX_PORT_STS_CMODE_RGMII;
546 break;
547 case PHY_INTERFACE_MODE_1000BASEX:
548 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX;
549 break;
550 case PHY_INTERFACE_MODE_SGMII:
551 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII;
552 break;
553 case PHY_INTERFACE_MODE_2500BASEX:
554 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX;
555 break;
556 case PHY_INTERFACE_MODE_5GBASER:
557 cmode = MV88E6393X_PORT_STS_CMODE_5GBASER;
558 break;
559 case PHY_INTERFACE_MODE_XGMII:
560 case PHY_INTERFACE_MODE_XAUI:
561 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI;
562 break;
563 case PHY_INTERFACE_MODE_RXAUI:
564 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI;
565 break;
566 case PHY_INTERFACE_MODE_10GBASER:
567 cmode = MV88E6393X_PORT_STS_CMODE_10GBASER;
568 break;
569 case PHY_INTERFACE_MODE_USXGMII:
570 cmode = MV88E6393X_PORT_STS_CMODE_USXGMII;
571 break;
572 default:
573 cmode = 0;
574 }
575
576 /* cmode doesn't change, nothing to do for us unless forced */
577 if (cmode == chip->ports[port].cmode && !force)
578 return 0;
579
580 chip->ports[port].cmode = 0;
581
582 if (cmode) {
583 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
584 if (err)
585 return err;
586
587 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
588 reg |= cmode;
589
590 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
591 if (err)
592 return err;
593
594 chip->ports[port].cmode = cmode;
595 }
596
597 return 0;
598 }
599
600 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
601 phy_interface_t mode)
602 {
603 if (port != 9 && port != 10)
604 return -EOPNOTSUPP;
605
606 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
607 }
608
609 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
610 phy_interface_t mode)
611 {
612 if (port != 9 && port != 10)
613 return -EOPNOTSUPP;
614
615 switch (mode) {
616 case PHY_INTERFACE_MODE_NA:
617 return 0;
618 case PHY_INTERFACE_MODE_XGMII:
619 case PHY_INTERFACE_MODE_XAUI:
620 case PHY_INTERFACE_MODE_RXAUI:
621 return -EINVAL;
622 default:
623 break;
624 }
625
626 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
627 }
628
629 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
630 phy_interface_t mode)
631 {
632 int err;
633 u16 reg;
634
635 if (port != 0 && port != 9 && port != 10)
636 return -EOPNOTSUPP;
637
638 if (port == 9 || port == 10) {
639 switch (mode) {
640 case PHY_INTERFACE_MODE_RMII:
641 case PHY_INTERFACE_MODE_RGMII:
642 case PHY_INTERFACE_MODE_RGMII_ID:
643 case PHY_INTERFACE_MODE_RGMII_RXID:
644 case PHY_INTERFACE_MODE_RGMII_TXID:
645 return -EINVAL;
646 default:
647 break;
648 }
649 }
650
651 /* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */
652 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
653 if (err)
654 return err;
655
656 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE;
657 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE;
658 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
659 if (err)
660 return err;
661
662 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
663 }
664
665 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip,
666 int port)
667 {
668 int err, addr;
669 u16 reg, bits;
670
671 if (port != 5)
672 return -EOPNOTSUPP;
673
674 addr = chip->info->port_base_addr + port;
675
676 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, &reg);
677 if (err)
678 return err;
679
680 bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE |
681 MV88E6341_PORT_RESERVED_1A_SGMII_AN;
682
683 if ((reg & bits) == bits)
684 return 0;
685
686 reg |= bits;
687 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg);
688 }
689
690 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
691 phy_interface_t mode)
692 {
693 int err;
694
695 if (port != 5)
696 return -EOPNOTSUPP;
697
698 switch (mode) {
699 case PHY_INTERFACE_MODE_NA:
700 return 0;
701 case PHY_INTERFACE_MODE_XGMII:
702 case PHY_INTERFACE_MODE_XAUI:
703 case PHY_INTERFACE_MODE_RXAUI:
704 return -EINVAL;
705 default:
706 break;
707 }
708
709 err = mv88e6341_port_set_cmode_writable(chip, port);
710 if (err)
711 return err;
712
713 return mv88e6xxx_port_set_cmode(chip, port, mode, true);
714 }
715
716 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
717 {
718 int err;
719 u16 reg;
720
721 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
722 if (err)
723 return err;
724
725 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK;
726
727 return 0;
728 }
729
730 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
731 {
732 int err;
733 u16 reg;
734
735 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
736 if (err)
737 return err;
738
739 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
740
741 return 0;
742 }
743
744 /* Offset 0x02: Jamming Control
745 *
746 * Do not limit the period of time that this port can be paused for by
747 * the remote end or the period of time that this port can pause the
748 * remote end.
749 */
750 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
751 u8 out)
752 {
753 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
754 out << 8 | in);
755 }
756
757 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
758 u8 out)
759 {
760 int err;
761
762 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
763 MV88E6390_PORT_FLOW_CTL_UPDATE |
764 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in);
765 if (err)
766 return err;
767
768 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
769 MV88E6390_PORT_FLOW_CTL_UPDATE |
770 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out);
771 }
772
773 /* Offset 0x04: Port Control Register */
774
775 static const char * const mv88e6xxx_port_state_names[] = {
776 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled",
777 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening",
778 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning",
779 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding",
780 };
781
782 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
783 {
784 u16 reg;
785 int err;
786
787 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
788 if (err)
789 return err;
790
791 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
792
793 switch (state) {
794 case BR_STATE_DISABLED:
795 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED;
796 break;
797 case BR_STATE_BLOCKING:
798 case BR_STATE_LISTENING:
799 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
800 break;
801 case BR_STATE_LEARNING:
802 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
803 break;
804 case BR_STATE_FORWARDING:
805 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
806 break;
807 default:
808 return -EINVAL;
809 }
810
811 reg |= state;
812
813 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
814 if (err)
815 return err;
816
817 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
818 mv88e6xxx_port_state_names[state]);
819
820 return 0;
821 }
822
823 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
824 enum mv88e6xxx_egress_mode mode)
825 {
826 int err;
827 u16 reg;
828
829 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
830 if (err)
831 return err;
832
833 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
834
835 switch (mode) {
836 case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
837 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
838 break;
839 case MV88E6XXX_EGRESS_MODE_UNTAGGED:
840 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
841 break;
842 case MV88E6XXX_EGRESS_MODE_TAGGED:
843 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
844 break;
845 case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
846 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
847 break;
848 default:
849 return -EINVAL;
850 }
851
852 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
853 }
854
855 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
856 enum mv88e6xxx_frame_mode mode)
857 {
858 int err;
859 u16 reg;
860
861 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
862 if (err)
863 return err;
864
865 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
866
867 switch (mode) {
868 case MV88E6XXX_FRAME_MODE_NORMAL:
869 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
870 break;
871 case MV88E6XXX_FRAME_MODE_DSA:
872 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
873 break;
874 default:
875 return -EINVAL;
876 }
877
878 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
879 }
880
881 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
882 enum mv88e6xxx_frame_mode mode)
883 {
884 int err;
885 u16 reg;
886
887 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
888 if (err)
889 return err;
890
891 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
892
893 switch (mode) {
894 case MV88E6XXX_FRAME_MODE_NORMAL:
895 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
896 break;
897 case MV88E6XXX_FRAME_MODE_DSA:
898 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
899 break;
900 case MV88E6XXX_FRAME_MODE_PROVIDER:
901 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
902 break;
903 case MV88E6XXX_FRAME_MODE_ETHERTYPE:
904 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
905 break;
906 default:
907 return -EINVAL;
908 }
909
910 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
911 }
912
913 int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
914 int port, bool unicast)
915 {
916 int err;
917 u16 reg;
918
919 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
920 if (err)
921 return err;
922
923 if (unicast)
924 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
925 else
926 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
927
928 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
929 }
930
931 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,
932 bool unicast)
933 {
934 int err;
935 u16 reg;
936
937 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
938 if (err)
939 return err;
940
941 if (unicast)
942 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
943 else
944 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
945
946 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
947 }
948
949 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,
950 bool multicast)
951 {
952 int err;
953 u16 reg;
954
955 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
956 if (err)
957 return err;
958
959 if (multicast)
960 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
961 else
962 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
963
964 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
965 }
966
967 /* Offset 0x05: Port Control 1 */
968
969 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
970 bool message_port)
971 {
972 u16 val;
973 int err;
974
975 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
976 if (err)
977 return err;
978
979 if (message_port)
980 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
981 else
982 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
983
984 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
985 }
986
987 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
988 bool trunk, u8 id)
989 {
990 u16 val;
991 int err;
992
993 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
994 if (err)
995 return err;
996
997 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK;
998
999 if (trunk)
1000 val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT |
1001 (id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT);
1002 else
1003 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT;
1004
1005 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
1006 }
1007
1008 /* Offset 0x06: Port Based VLAN Map */
1009
1010 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
1011 {
1012 const u16 mask = mv88e6xxx_port_mask(chip);
1013 u16 reg;
1014 int err;
1015
1016 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, &reg);
1017 if (err)
1018 return err;
1019
1020 reg &= ~mask;
1021 reg |= map & mask;
1022
1023 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1024 if (err)
1025 return err;
1026
1027 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
1028
1029 return 0;
1030 }
1031
1032 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
1033 {
1034 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
1035 u16 reg;
1036 int err;
1037
1038 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1039 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, &reg);
1040 if (err)
1041 return err;
1042
1043 *fid = (reg & 0xf000) >> 12;
1044
1045 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
1046 if (upper_mask) {
1047 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1048 &reg);
1049 if (err)
1050 return err;
1051
1052 *fid |= (reg & upper_mask) << 4;
1053 }
1054
1055 return 0;
1056 }
1057
1058 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
1059 {
1060 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
1061 u16 reg;
1062 int err;
1063
1064 if (fid >= mv88e6xxx_num_databases(chip))
1065 return -EINVAL;
1066
1067 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1068 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, &reg);
1069 if (err)
1070 return err;
1071
1072 reg &= 0x0fff;
1073 reg |= (fid & 0x000f) << 12;
1074
1075 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1076 if (err)
1077 return err;
1078
1079 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
1080 if (upper_mask) {
1081 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1082 &reg);
1083 if (err)
1084 return err;
1085
1086 reg &= ~upper_mask;
1087 reg |= (fid >> 4) & upper_mask;
1088
1089 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
1090 reg);
1091 if (err)
1092 return err;
1093 }
1094
1095 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
1096
1097 return 0;
1098 }
1099
1100 /* Offset 0x07: Default Port VLAN ID & Priority */
1101
1102 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
1103 {
1104 u16 reg;
1105 int err;
1106
1107 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1108 &reg);
1109 if (err)
1110 return err;
1111
1112 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1113
1114 return 0;
1115 }
1116
1117 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
1118 {
1119 u16 reg;
1120 int err;
1121
1122 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1123 &reg);
1124 if (err)
1125 return err;
1126
1127 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1128 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1129
1130 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1131 reg);
1132 if (err)
1133 return err;
1134
1135 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
1136
1137 return 0;
1138 }
1139
1140 /* Offset 0x08: Port Control 2 Register */
1141
1142 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1143 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled",
1144 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback",
1145 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check",
1146 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",
1147 };
1148
1149 int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
1150 int port, bool multicast)
1151 {
1152 int err;
1153 u16 reg;
1154
1155 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1156 if (err)
1157 return err;
1158
1159 if (multicast)
1160 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1161 else
1162 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1163
1164 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1165 }
1166
1167 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1168 int upstream_port)
1169 {
1170 int err;
1171 u16 reg;
1172
1173 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1174 if (err)
1175 return err;
1176
1177 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
1178 reg |= upstream_port;
1179
1180 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1181 }
1182
1183 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
1184 enum mv88e6xxx_egress_direction direction,
1185 bool mirror)
1186 {
1187 bool *mirror_port;
1188 u16 reg;
1189 u16 bit;
1190 int err;
1191
1192 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1193 if (err)
1194 return err;
1195
1196 switch (direction) {
1197 case MV88E6XXX_EGRESS_DIR_INGRESS:
1198 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR;
1199 mirror_port = &chip->ports[port].mirror_ingress;
1200 break;
1201 case MV88E6XXX_EGRESS_DIR_EGRESS:
1202 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR;
1203 mirror_port = &chip->ports[port].mirror_egress;
1204 break;
1205 default:
1206 return -EINVAL;
1207 }
1208
1209 reg &= ~bit;
1210 if (mirror)
1211 reg |= bit;
1212
1213 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1214 if (!err)
1215 *mirror_port = mirror;
1216
1217 return err;
1218 }
1219
1220 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port,
1221 bool locked)
1222 {
1223 u16 reg;
1224 int err;
1225
1226 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
1227 if (err)
1228 return err;
1229
1230 reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK;
1231 if (locked)
1232 reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK;
1233
1234 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1235 if (err)
1236 return err;
1237
1238 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, &reg);
1239 if (err)
1240 return err;
1241
1242 reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT;
1243 if (locked)
1244 reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT;
1245
1246 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg);
1247 }
1248
1249 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
1250 u16 mode)
1251 {
1252 u16 reg;
1253 int err;
1254
1255 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1256 if (err)
1257 return err;
1258
1259 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1260 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1261
1262 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1263 if (err)
1264 return err;
1265
1266 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
1267 mv88e6xxx_port_8021q_mode_names[mode]);
1268
1269 return 0;
1270 }
1271
1272 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,
1273 bool drop_untagged)
1274 {
1275 u16 old, new;
1276 int err;
1277
1278 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old);
1279 if (err)
1280 return err;
1281
1282 if (drop_untagged)
1283 new = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED;
1284 else
1285 new = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED;
1286
1287 if (new == old)
1288 return 0;
1289
1290 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new);
1291 }
1292
1293 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map)
1294 {
1295 u16 reg;
1296 int err;
1297
1298 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1299 if (err)
1300 return err;
1301
1302 if (map)
1303 reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
1304 else
1305 reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA;
1306
1307 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1308 }
1309
1310 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
1311 size_t size)
1312 {
1313 u16 reg;
1314 int err;
1315
1316 size += VLAN_ETH_HLEN + ETH_FCS_LEN;
1317
1318 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1319 if (err)
1320 return err;
1321
1322 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
1323
1324 if (size <= 1522)
1325 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
1326 else if (size <= 2048)
1327 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
1328 else if (size <= 10240)
1329 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
1330 else
1331 return -ERANGE;
1332
1333 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1334 }
1335
1336 /* Offset 0x09: Port Rate Control */
1337
1338 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1339 {
1340 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1341 0x0000);
1342 }
1343
1344 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1345 {
1346 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1347 0x0001);
1348 }
1349
1350 /* Offset 0x0B: Port Association Vector */
1351
1352 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port,
1353 u16 pav)
1354 {
1355 u16 reg, mask;
1356 int err;
1357
1358 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1359 &reg);
1360 if (err)
1361 return err;
1362
1363 mask = mv88e6xxx_port_mask(chip);
1364 reg &= ~mask;
1365 reg |= pav & mask;
1366
1367 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1368 reg);
1369 }
1370
1371 /* Offset 0x0C: Port ATU Control */
1372
1373 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
1374 {
1375 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
1376 }
1377
1378 /* Offset 0x0D: (Priority) Override Register */
1379
1380 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
1381 {
1382 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
1383 }
1384
1385 /* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */
1386
1387 static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port,
1388 u16 pointer, u8 *data)
1389 {
1390 u16 reg;
1391 int err;
1392
1393 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1394 pointer);
1395 if (err)
1396 return err;
1397
1398 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1399 &reg);
1400 if (err)
1401 return err;
1402
1403 *data = reg;
1404
1405 return 0;
1406 }
1407
1408 static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port,
1409 u16 pointer, u8 data)
1410 {
1411 u16 reg;
1412
1413 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data;
1414
1415 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1416 reg);
1417 }
1418
1419 static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip,
1420 u16 pointer, u8 data)
1421 {
1422 int err, port;
1423
1424 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1425 if (dsa_is_unused_port(chip->ds, port))
1426 continue;
1427
1428 err = mv88e6393x_port_policy_write(chip, port, pointer, data);
1429 if (err)
1430 return err;
1431 }
1432
1433 return 0;
1434 }
1435
1436 int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip,
1437 enum mv88e6xxx_egress_direction direction,
1438 int port)
1439 {
1440 u16 ptr;
1441 int err;
1442
1443 switch (direction) {
1444 case MV88E6XXX_EGRESS_DIR_INGRESS:
1445 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST;
1446 err = mv88e6393x_port_policy_write_all(chip, ptr, port);
1447 if (err)
1448 return err;
1449 break;
1450 case MV88E6XXX_EGRESS_DIR_EGRESS:
1451 ptr = MV88E6393X_G2_EGRESS_MONITOR_DEST;
1452 err = mv88e6xxx_g2_write(chip, ptr, port);
1453 if (err)
1454 return err;
1455 break;
1456 }
1457
1458 return 0;
1459 }
1460
1461 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1462 int upstream_port)
1463 {
1464 u16 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST;
1465 u8 data = MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI |
1466 upstream_port;
1467
1468 return mv88e6393x_port_policy_write(chip, port, ptr, data);
1469 }
1470
1471 int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
1472 {
1473 u16 ptr;
1474 int err;
1475
1476 /* Consider the frames with reserved multicast destination
1477 * addresses matching 01:80:c2:00:00:00 and
1478 * 01:80:c2:00:00:02 as MGMT.
1479 */
1480 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO;
1481 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1482 if (err)
1483 return err;
1484
1485 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI;
1486 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1487 if (err)
1488 return err;
1489
1490 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO;
1491 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1492 if (err)
1493 return err;
1494
1495 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI;
1496 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1497 if (err)
1498 return err;
1499
1500 return 0;
1501 }
1502
1503 /* Offset 0x10 & 0x11: EPC */
1504
1505 static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port)
1506 {
1507 int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY);
1508
1509 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0);
1510 }
1511
1512 /* Port Ether type for 6393X family */
1513
1514 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1515 u16 etype)
1516 {
1517 u16 val;
1518 int err;
1519
1520 err = mv88e6393x_port_epc_wait_ready(chip, port);
1521 if (err)
1522 return err;
1523
1524 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype);
1525 if (err)
1526 return err;
1527
1528 val = MV88E6393X_PORT_EPC_CMD_BUSY |
1529 MV88E6393X_PORT_EPC_CMD_WRITE |
1530 MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE;
1531
1532 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val);
1533 }
1534
1535 /* Offset 0x0f: Port Ether type */
1536
1537 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1538 u16 etype)
1539 {
1540 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
1541 }
1542
1543 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1544 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1545 */
1546
1547 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1548 {
1549 int err;
1550
1551 /* Use a direct priority mapping for all IEEE tagged frames */
1552 err = mv88e6xxx_port_write(chip, port,
1553 MV88E6095_PORT_IEEE_PRIO_REMAP_0123,
1554 0x3210);
1555 if (err)
1556 return err;
1557
1558 return mv88e6xxx_port_write(chip, port,
1559 MV88E6095_PORT_IEEE_PRIO_REMAP_4567,
1560 0x7654);
1561 }
1562
1563 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
1564 int port, u16 table, u8 ptr, u16 data)
1565 {
1566 u16 reg;
1567
1568 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table |
1569 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) |
1570 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK);
1571
1572 return mv88e6xxx_port_write(chip, port,
1573 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
1574 }
1575
1576 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1577 {
1578 int err, i;
1579 u16 table;
1580
1581 for (i = 0; i <= 7; i++) {
1582 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP;
1583 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
1584 (i | i << 4));
1585 if (err)
1586 return err;
1587
1588 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP;
1589 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1590 if (err)
1591 return err;
1592
1593 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP;
1594 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1595 if (err)
1596 return err;
1597
1598 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP;
1599 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1600 if (err)
1601 return err;
1602 }
1603
1604 return 0;
1605 }
1606
1607 /* Offset 0x0E: Policy Control Register */
1608
1609 static int
1610 mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping,
1611 enum mv88e6xxx_policy_action action,
1612 u16 *mask, u16 *val, int *shift)
1613 {
1614 switch (mapping) {
1615 case MV88E6XXX_POLICY_MAPPING_DA:
1616 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK);
1617 *mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK;
1618 break;
1619 case MV88E6XXX_POLICY_MAPPING_SA:
1620 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK);
1621 *mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK;
1622 break;
1623 case MV88E6XXX_POLICY_MAPPING_VTU:
1624 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK);
1625 *mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK;
1626 break;
1627 case MV88E6XXX_POLICY_MAPPING_ETYPE:
1628 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK);
1629 *mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK;
1630 break;
1631 case MV88E6XXX_POLICY_MAPPING_PPPOE:
1632 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK);
1633 *mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK;
1634 break;
1635 case MV88E6XXX_POLICY_MAPPING_VBAS:
1636 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK);
1637 *mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK;
1638 break;
1639 case MV88E6XXX_POLICY_MAPPING_OPT82:
1640 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK);
1641 *mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK;
1642 break;
1643 case MV88E6XXX_POLICY_MAPPING_UDP:
1644 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK);
1645 *mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK;
1646 break;
1647 default:
1648 return -EOPNOTSUPP;
1649 }
1650
1651 switch (action) {
1652 case MV88E6XXX_POLICY_ACTION_NORMAL:
1653 *val = MV88E6XXX_PORT_POLICY_CTL_NORMAL;
1654 break;
1655 case MV88E6XXX_POLICY_ACTION_MIRROR:
1656 *val = MV88E6XXX_PORT_POLICY_CTL_MIRROR;
1657 break;
1658 case MV88E6XXX_POLICY_ACTION_TRAP:
1659 *val = MV88E6XXX_PORT_POLICY_CTL_TRAP;
1660 break;
1661 case MV88E6XXX_POLICY_ACTION_DISCARD:
1662 *val = MV88E6XXX_PORT_POLICY_CTL_DISCARD;
1663 break;
1664 default:
1665 return -EOPNOTSUPP;
1666 }
1667
1668 return 0;
1669 }
1670
1671 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1672 enum mv88e6xxx_policy_mapping mapping,
1673 enum mv88e6xxx_policy_action action)
1674 {
1675 u16 reg, mask, val;
1676 int shift;
1677 int err;
1678
1679 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask,
1680 &val, &shift);
1681 if (err)
1682 return err;
1683
1684 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, &reg);
1685 if (err)
1686 return err;
1687
1688 reg &= ~mask;
1689 reg |= (val << shift) & mask;
1690
1691 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg);
1692 }
1693
1694 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1695 enum mv88e6xxx_policy_mapping mapping,
1696 enum mv88e6xxx_policy_action action)
1697 {
1698 u16 mask, val;
1699 int shift;
1700 int err;
1701 u16 ptr;
1702 u8 reg;
1703
1704 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask,
1705 &val, &shift);
1706 if (err)
1707 return err;
1708
1709 /* The 16-bit Port Policy CTL register from older chips is on 6393x
1710 * changed to Port Policy MGMT CTL, which can access more data, but
1711 * indirectly. The original 16-bit value is divided into two 8-bit
1712 * registers.
1713 */
1714 ptr = shift / 8;
1715 shift %= 8;
1716 mask >>= ptr * 8;
1717 ptr <<= 8;
1718
1719 err = mv88e6393x_port_policy_read(chip, port, ptr, &reg);
1720 if (err)
1721 return err;
1722
1723 reg &= ~mask;
1724 reg |= (val << shift) & mask;
1725
1726 return mv88e6393x_port_policy_write(chip, port, ptr, reg);
1727 }
Linux Kernel