drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf2.h

   1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
   2
   3 /* MDIO support for Mellanox Gigabit Ethernet driver
   4  *
   5  * Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES, ALL RIGHTS RESERVED.
   6  *
   7  * This software product is a proprietary product of NVIDIA CORPORATION &
   8  * AFFILIATES (the "Company") and all right, title, and interest in and to the
   9  * software product, including all associated intellectual property rights, are
  10  * and shall remain exclusively with the Company.
  11  *
  12  * This software product is governed by the End User License Agreement
  13  * provided with the software product.
  14  */
  15
  16 #ifndef __MLXBF_GIGE_MDIO_BF2_H__
  17 #define __MLXBF_GIGE_MDIO_BF2_H__
  18
  19 #include <linux/bitfield.h>
  20
  21 #define MLXBF2_GIGE_MDIO_GW_OFFSET      0x0
  22 #define MLXBF2_GIGE_MDIO_CFG_OFFSET     0x4
  23
  24 /* MDIO GW register bits */
  25 #define MLXBF2_GIGE_MDIO_GW_AD_MASK     GENMASK(15, 0)
  26 #define MLXBF2_GIGE_MDIO_GW_DEVAD_MASK  GENMASK(20, 16)
  27 #define MLXBF2_GIGE_MDIO_GW_PARTAD_MASK GENMASK(25, 21)
  28 #define MLXBF2_GIGE_MDIO_GW_OPCODE_MASK GENMASK(27, 26)
  29 #define MLXBF2_GIGE_MDIO_GW_ST1_MASK    GENMASK(28, 28)
  30 #define MLXBF2_GIGE_MDIO_GW_BUSY_MASK   GENMASK(30, 30)
  31
  32 #define MLXBF2_GIGE_MDIO_GW_AD_SHIFT     0
  33 #define MLXBF2_GIGE_MDIO_GW_DEVAD_SHIFT  16
  34 #define MLXBF2_GIGE_MDIO_GW_PARTAD_SHIFT 21
  35 #define MLXBF2_GIGE_MDIO_GW_OPCODE_SHIFT 26
  36 #define MLXBF2_GIGE_MDIO_GW_ST1_SHIFT    28
  37 #define MLXBF2_GIGE_MDIO_GW_BUSY_SHIFT   30
  38
  39 /* MDIO config register bits */
  40 #define MLXBF2_GIGE_MDIO_CFG_MDIO_MODE_MASK             GENMASK(1, 0)
  41 #define MLXBF2_GIGE_MDIO_CFG_MDIO3_3_MASK               GENMASK(2, 2)
  42 #define MLXBF2_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK       GENMASK(4, 4)
  43 #define MLXBF2_GIGE_MDIO_CFG_MDC_PERIOD_MASK            GENMASK(15, 8)
  44 #define MLXBF2_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK          GENMASK(23, 16)
  45 #define MLXBF2_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK         GENMASK(31, 24)
  46
  47 #define MLXBF2_GIGE_MDIO_CFG_VAL (FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_MODE_MASK, 1) | \
  48                                  FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO3_3_MASK, 1) | \
  49                                  FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, 1) | \
  50                                  FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) | \
  51                                  FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13))
  52
  53 #endif /* __MLXBF_GIGE_MDIO_BF2_H__ */