1 # SPDX-License-Identifier: GPL-2.0
2 obj-
$(CONFIG_ARM_CCI_PMU
) += arm-cci.o
3 obj-
$(CONFIG_ARM_CCN
) += arm-ccn.o
4 obj-
$(CONFIG_ARM_CMN
) += arm-cmn.o
5 obj-
$(CONFIG_ARM_DSU_PMU
) += arm_dsu_pmu.o
6 obj-
$(CONFIG_ARM_NI
) += arm-ni.o
7 obj-
$(CONFIG_ARM_PMU
) += arm_pmu.o arm_pmu_platform.o
8 obj-
$(CONFIG_ARM_PMU_ACPI
) += arm_pmu_acpi.o
9 obj-
$(CONFIG_ARM_PMUV3
) += arm_pmuv3.o
10 obj-
$(CONFIG_ARM_V6_PMU
) += arm_v6_pmu.o
11 obj-
$(CONFIG_ARM_V7_PMU
) += arm_v7_pmu.o
12 obj-
$(CONFIG_ARM_XSCALE_PMU
) += arm_xscale_pmu.o
13 obj-
$(CONFIG_ARM_SMMU_V3_PMU
) += arm_smmuv3_pmu.o
14 obj-
$(CONFIG_FSL_IMX8_DDR_PMU
) += fsl_imx8_ddr_perf.o
15 obj-
$(CONFIG_FSL_IMX9_DDR_PMU
) += fsl_imx9_ddr_perf.o
16 obj-
$(CONFIG_HISI_PMU
) += hisilicon
/
17 obj-
$(CONFIG_QCOM_L2_PMU
) += qcom_l2_pmu.o
18 obj-
$(CONFIG_QCOM_L3_PMU
) += qcom_l3_pmu.o
19 obj-
$(CONFIG_RISCV_PMU
) += riscv_pmu.o
20 obj-
$(CONFIG_RISCV_PMU_LEGACY
) += riscv_pmu_legacy.o
21 obj-
$(CONFIG_RISCV_PMU_SBI
) += riscv_pmu_sbi.o
22 obj-
$(CONFIG_STARFIVE_STARLINK_PMU
) += starfive_starlink_pmu.o
23 obj-
$(CONFIG_THUNDERX2_PMU
) += thunderx2_pmu.o
24 obj-
$(CONFIG_XGENE_PMU
) += xgene_pmu.o
25 obj-
$(CONFIG_ARM_SPE_PMU
) += arm_spe_pmu.o
26 obj-
$(CONFIG_ARM_DMC620_PMU
) += arm_dmc620_pmu.o
27 obj-
$(CONFIG_MARVELL_CN10K_TAD_PMU
) += marvell_cn10k_tad_pmu.o
28 obj-
$(CONFIG_MARVELL_CN10K_DDR_PMU
) += marvell_cn10k_ddr_pmu.o
29 obj-
$(CONFIG_MARVELL_PEM_PMU
) += marvell_pem_pmu.o
30 obj-
$(CONFIG_APPLE_M1_CPU_PMU
) += apple_m1_cpu_pmu.o
31 obj-
$(CONFIG_ALIBABA_UNCORE_DRW_PMU
) += alibaba_uncore_drw_pmu.o
32 obj-
$(CONFIG_DWC_PCIE_PMU
) += dwc_pcie_pmu.o
33 obj-
$(CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU
) += arm_cspmu
/
34 obj-
$(CONFIG_MESON_DDR_PMU
) += amlogic
/
35 obj-
$(CONFIG_CXL_PMU
) += cxl_pmu.o
