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Merge tag 'powerpc-6.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[linux.git] / drivers / pinctrl / mediatek / pinctrl-airoha.c
blob547a798b71c8aea740259b8f388116cacb91b75d
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Author: Lorenzo Bianconi <lorenzo@kernel.org>
4 * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
5 * Author: Markus Gothe <markus.gothe@genexis.eu>
6 */
7
8 #include <dt-bindings/pinctrl/mt65xx.h>
9 #include <linux/bits.h>
10 #include <linux/cleanup.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/of.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_platform.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/pinctrl/pinmux.h>
25 #include <linux/platform_device.h>
26 #include <linux/regmap.h>
27
28 #include "../core.h"
29 #include "../pinconf.h"
30 #include "../pinmux.h"
31
32 #define PINCTRL_PIN_GROUP(id) \
33 PINCTRL_PINGROUP(#id, id##_pins, ARRAY_SIZE(id##_pins))
34
35 #define PINCTRL_FUNC_DESC(id) \
36 { \
37 .desc = { \
38 .func = { \
39 .name = #id, \
40 .groups = id##_groups, \
41 .ngroups = ARRAY_SIZE(id##_groups), \
42 } \
43 }, \
44 .groups = id##_func_group, \
45 .group_size = ARRAY_SIZE(id##_func_group), \
46 }
47
48 #define PINCTRL_CONF_DESC(p, offset, mask) \
49 { \
50 .pin = p, \
51 .reg = { offset, mask }, \
52 }
53
54 /* MUX */
55 #define REG_GPIO_2ND_I2C_MODE 0x0214
56 #define GPIO_MDC_IO_MASTER_MODE_MODE BIT(14)
57 #define GPIO_I2C_MASTER_MODE_MODE BIT(13)
58 #define GPIO_I2S_MODE_MASK BIT(12)
59 #define GPIO_I2C_SLAVE_MODE_MODE BIT(11)
60 #define GPIO_LAN3_LED1_MODE_MASK BIT(10)
61 #define GPIO_LAN3_LED0_MODE_MASK BIT(9)
62 #define GPIO_LAN2_LED1_MODE_MASK BIT(8)
63 #define GPIO_LAN2_LED0_MODE_MASK BIT(7)
64 #define GPIO_LAN1_LED1_MODE_MASK BIT(6)
65 #define GPIO_LAN1_LED0_MODE_MASK BIT(5)
66 #define GPIO_LAN0_LED1_MODE_MASK BIT(4)
67 #define GPIO_LAN0_LED0_MODE_MASK BIT(3)
68 #define PON_TOD_1PPS_MODE_MASK BIT(2)
69 #define GSW_TOD_1PPS_MODE_MASK BIT(1)
70 #define GPIO_2ND_I2C_MODE_MASK BIT(0)
71
72 #define REG_GPIO_SPI_CS1_MODE 0x0218
73 #define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
74 #define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
75 #define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
76 #define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
77 #define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
78 #define GPIO_PCM_SPI_MODE_MASK BIT(16)
79 #define GPIO_PCM2_MODE_MASK BIT(13)
80 #define GPIO_PCM1_MODE_MASK BIT(12)
81 #define GPIO_PCM_INT_MODE_MASK BIT(9)
82 #define GPIO_PCM_RESET_MODE_MASK BIT(8)
83 #define GPIO_SPI_QUAD_MODE_MASK BIT(4)
84 #define GPIO_SPI_CS4_MODE_MASK BIT(3)
85 #define GPIO_SPI_CS3_MODE_MASK BIT(2)
86 #define GPIO_SPI_CS2_MODE_MASK BIT(1)
87 #define GPIO_SPI_CS1_MODE_MASK BIT(0)
88
89 #define REG_GPIO_PON_MODE 0x021c
90 #define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
91 #define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
92 #define GPIO_PCIE_RESET2_MASK BIT(12)
93 #define SIPO_RCLK_MODE_MASK BIT(11)
94 #define GPIO_PCIE_RESET1_MASK BIT(10)
95 #define GPIO_PCIE_RESET0_MASK BIT(9)
96 #define GPIO_UART5_MODE_MASK BIT(8)
97 #define GPIO_UART4_MODE_MASK BIT(7)
98 #define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6)
99 #define GPIO_HSUART_MODE_MASK BIT(5)
100 #define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4)
101 #define GPIO_UART2_MODE_MASK BIT(3)
102 #define GPIO_SIPO_MODE_MASK BIT(2)
103 #define GPIO_EMMC_MODE_MASK BIT(1)
104 #define GPIO_PON_MODE_MASK BIT(0)
105
106 #define REG_NPU_UART_EN 0x0224
107 #define JTAG_UDI_EN_MASK BIT(4)
108 #define JTAG_DFD_EN_MASK BIT(3)
109
110 /* LED MAP */
111 #define REG_LAN_LED0_MAPPING 0x027c
112 #define REG_LAN_LED1_MAPPING 0x0280
113
114 #define LAN4_LED_MAPPING_MASK GENMASK(18, 16)
115 #define LAN4_PHY4_LED_MAP BIT(18)
116 #define LAN4_PHY2_LED_MAP BIT(17)
117 #define LAN4_PHY1_LED_MAP BIT(16)
118 #define LAN4_PHY0_LED_MAP 0
119 #define LAN4_PHY3_LED_MAP GENMASK(17, 16)
120
121 #define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
122 #define LAN3_PHY4_LED_MAP BIT(14)
123 #define LAN3_PHY2_LED_MAP BIT(13)
124 #define LAN3_PHY1_LED_MAP BIT(12)
125 #define LAN3_PHY0_LED_MAP 0
126 #define LAN3_PHY3_LED_MAP GENMASK(13, 12)
127
128 #define LAN2_LED_MAPPING_MASK GENMASK(10, 8)
129 #define LAN2_PHY4_LED_MAP BIT(12)
130 #define LAN2_PHY2_LED_MAP BIT(11)
131 #define LAN2_PHY1_LED_MAP BIT(10)
132 #define LAN2_PHY0_LED_MAP 0
133 #define LAN2_PHY3_LED_MAP GENMASK(11, 10)
134
135 #define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
136 #define LAN1_PHY4_LED_MAP BIT(6)
137 #define LAN1_PHY2_LED_MAP BIT(5)
138 #define LAN1_PHY1_LED_MAP BIT(4)
139 #define LAN1_PHY0_LED_MAP 0
140 #define LAN1_PHY3_LED_MAP GENMASK(5, 4)
141
142 #define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
143 #define LAN0_PHY4_LED_MAP BIT(3)
144 #define LAN0_PHY2_LED_MAP BIT(2)
145 #define LAN0_PHY1_LED_MAP BIT(1)
146 #define LAN0_PHY0_LED_MAP 0
147 #define LAN0_PHY3_LED_MAP GENMASK(2, 1)
148
149 /* CONF */
150 #define REG_I2C_SDA_E2 0x001c
151 #define SPI_MISO_E2_MASK BIT(14)
152 #define SPI_MOSI_E2_MASK BIT(13)
153 #define SPI_CLK_E2_MASK BIT(12)
154 #define SPI_CS0_E2_MASK BIT(11)
155 #define PCIE2_RESET_E2_MASK BIT(10)
156 #define PCIE1_RESET_E2_MASK BIT(9)
157 #define PCIE0_RESET_E2_MASK BIT(8)
158 #define UART1_RXD_E2_MASK BIT(3)
159 #define UART1_TXD_E2_MASK BIT(2)
160 #define I2C_SCL_E2_MASK BIT(1)
161 #define I2C_SDA_E2_MASK BIT(0)
162
163 #define REG_I2C_SDA_E4 0x0020
164 #define SPI_MISO_E4_MASK BIT(14)
165 #define SPI_MOSI_E4_MASK BIT(13)
166 #define SPI_CLK_E4_MASK BIT(12)
167 #define SPI_CS0_E4_MASK BIT(11)
168 #define PCIE2_RESET_E4_MASK BIT(10)
169 #define PCIE1_RESET_E4_MASK BIT(9)
170 #define PCIE0_RESET_E4_MASK BIT(8)
171 #define UART1_RXD_E4_MASK BIT(3)
172 #define UART1_TXD_E4_MASK BIT(2)
173 #define I2C_SCL_E4_MASK BIT(1)
174 #define I2C_SDA_E4_MASK BIT(0)
175
176 #define REG_GPIO_L_E2 0x0024
177 #define REG_GPIO_L_E4 0x0028
178 #define REG_GPIO_H_E2 0x002c
179 #define REG_GPIO_H_E4 0x0030
180
181 #define REG_I2C_SDA_PU 0x0044
182 #define SPI_MISO_PU_MASK BIT(14)
183 #define SPI_MOSI_PU_MASK BIT(13)
184 #define SPI_CLK_PU_MASK BIT(12)
185 #define SPI_CS0_PU_MASK BIT(11)
186 #define PCIE2_RESET_PU_MASK BIT(10)
187 #define PCIE1_RESET_PU_MASK BIT(9)
188 #define PCIE0_RESET_PU_MASK BIT(8)
189 #define UART1_RXD_PU_MASK BIT(3)
190 #define UART1_TXD_PU_MASK BIT(2)
191 #define I2C_SCL_PU_MASK BIT(1)
192 #define I2C_SDA_PU_MASK BIT(0)
193
194 #define REG_I2C_SDA_PD 0x0048
195 #define SPI_MISO_PD_MASK BIT(14)
196 #define SPI_MOSI_PD_MASK BIT(13)
197 #define SPI_CLK_PD_MASK BIT(12)
198 #define SPI_CS0_PD_MASK BIT(11)
199 #define PCIE2_RESET_PD_MASK BIT(10)
200 #define PCIE1_RESET_PD_MASK BIT(9)
201 #define PCIE0_RESET_PD_MASK BIT(8)
202 #define UART1_RXD_PD_MASK BIT(3)
203 #define UART1_TXD_PD_MASK BIT(2)
204 #define I2C_SCL_PD_MASK BIT(1)
205 #define I2C_SDA_PD_MASK BIT(0)
206
207 #define REG_GPIO_L_PU 0x004c
208 #define REG_GPIO_L_PD 0x0050
209 #define REG_GPIO_H_PU 0x0054
210 #define REG_GPIO_H_PD 0x0058
211
212 #define REG_PCIE_RESET_OD 0x018c
213 #define PCIE2_RESET_OD_MASK BIT(2)
214 #define PCIE1_RESET_OD_MASK BIT(1)
215 #define PCIE0_RESET_OD_MASK BIT(0)
216
217 /* GPIOs */
218 #define REG_GPIO_CTRL 0x0000
219 #define REG_GPIO_DATA 0x0004
220 #define REG_GPIO_INT 0x0008
221 #define REG_GPIO_INT_EDGE 0x000c
222 #define REG_GPIO_INT_LEVEL 0x0010
223 #define REG_GPIO_OE 0x0014
224 #define REG_GPIO_CTRL1 0x0020
225
226 /* PWM MODE CONF */
227 #define REG_GPIO_FLASH_MODE_CFG 0x0034
228 #define GPIO15_FLASH_MODE_CFG BIT(15)
229 #define GPIO14_FLASH_MODE_CFG BIT(14)
230 #define GPIO13_FLASH_MODE_CFG BIT(13)
231 #define GPIO12_FLASH_MODE_CFG BIT(12)
232 #define GPIO11_FLASH_MODE_CFG BIT(11)
233 #define GPIO10_FLASH_MODE_CFG BIT(10)
234 #define GPIO9_FLASH_MODE_CFG BIT(9)
235 #define GPIO8_FLASH_MODE_CFG BIT(8)
236 #define GPIO7_FLASH_MODE_CFG BIT(7)
237 #define GPIO6_FLASH_MODE_CFG BIT(6)
238 #define GPIO5_FLASH_MODE_CFG BIT(5)
239 #define GPIO4_FLASH_MODE_CFG BIT(4)
240 #define GPIO3_FLASH_MODE_CFG BIT(3)
241 #define GPIO2_FLASH_MODE_CFG BIT(2)
242 #define GPIO1_FLASH_MODE_CFG BIT(1)
243 #define GPIO0_FLASH_MODE_CFG BIT(0)
244
245 #define REG_GPIO_CTRL2 0x0060
246 #define REG_GPIO_CTRL3 0x0064
247
248 /* PWM MODE CONF EXT */
249 #define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
250 #define GPIO51_FLASH_MODE_CFG BIT(31)
251 #define GPIO50_FLASH_MODE_CFG BIT(30)
252 #define GPIO49_FLASH_MODE_CFG BIT(29)
253 #define GPIO48_FLASH_MODE_CFG BIT(28)
254 #define GPIO47_FLASH_MODE_CFG BIT(27)
255 #define GPIO46_FLASH_MODE_CFG BIT(26)
256 #define GPIO45_FLASH_MODE_CFG BIT(25)
257 #define GPIO44_FLASH_MODE_CFG BIT(24)
258 #define GPIO43_FLASH_MODE_CFG BIT(23)
259 #define GPIO42_FLASH_MODE_CFG BIT(22)
260 #define GPIO41_FLASH_MODE_CFG BIT(21)
261 #define GPIO40_FLASH_MODE_CFG BIT(20)
262 #define GPIO39_FLASH_MODE_CFG BIT(19)
263 #define GPIO38_FLASH_MODE_CFG BIT(18)
264 #define GPIO37_FLASH_MODE_CFG BIT(17)
265 #define GPIO36_FLASH_MODE_CFG BIT(16)
266 #define GPIO31_FLASH_MODE_CFG BIT(15)
267 #define GPIO30_FLASH_MODE_CFG BIT(14)
268 #define GPIO29_FLASH_MODE_CFG BIT(13)
269 #define GPIO28_FLASH_MODE_CFG BIT(12)
270 #define GPIO27_FLASH_MODE_CFG BIT(11)
271 #define GPIO26_FLASH_MODE_CFG BIT(10)
272 #define GPIO25_FLASH_MODE_CFG BIT(9)
273 #define GPIO24_FLASH_MODE_CFG BIT(8)
274 #define GPIO23_FLASH_MODE_CFG BIT(7)
275 #define GPIO22_FLASH_MODE_CFG BIT(6)
276 #define GPIO21_FLASH_MODE_CFG BIT(5)
277 #define GPIO20_FLASH_MODE_CFG BIT(4)
278 #define GPIO19_FLASH_MODE_CFG BIT(3)
279 #define GPIO18_FLASH_MODE_CFG BIT(2)
280 #define GPIO17_FLASH_MODE_CFG BIT(1)
281 #define GPIO16_FLASH_MODE_CFG BIT(0)
282
283 #define REG_GPIO_DATA1 0x0070
284 #define REG_GPIO_OE1 0x0078
285 #define REG_GPIO_INT1 0x007c
286 #define REG_GPIO_INT_EDGE1 0x0080
287 #define REG_GPIO_INT_EDGE2 0x0084
288 #define REG_GPIO_INT_EDGE3 0x0088
289 #define REG_GPIO_INT_LEVEL1 0x008c
290 #define REG_GPIO_INT_LEVEL2 0x0090
291 #define REG_GPIO_INT_LEVEL3 0x0094
292
293 #define AIROHA_NUM_PINS 64
294 #define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2)
295 #define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4)
296
297 static const u32 gpio_data_regs[] = {
298 REG_GPIO_DATA,
299 REG_GPIO_DATA1
300 };
301
302 static const u32 gpio_out_regs[] = {
303 REG_GPIO_OE,
304 REG_GPIO_OE1
305 };
306
307 static const u32 gpio_dir_regs[] = {
308 REG_GPIO_CTRL,
309 REG_GPIO_CTRL1,
310 REG_GPIO_CTRL2,
311 REG_GPIO_CTRL3
312 };
313
314 static const u32 irq_status_regs[] = {
315 REG_GPIO_INT,
316 REG_GPIO_INT1
317 };
318
319 static const u32 irq_level_regs[] = {
320 REG_GPIO_INT_LEVEL,
321 REG_GPIO_INT_LEVEL1,
322 REG_GPIO_INT_LEVEL2,
323 REG_GPIO_INT_LEVEL3
324 };
325
326 static const u32 irq_edge_regs[] = {
327 REG_GPIO_INT_EDGE,
328 REG_GPIO_INT_EDGE1,
329 REG_GPIO_INT_EDGE2,
330 REG_GPIO_INT_EDGE3
331 };
332
333 struct airoha_pinctrl_reg {
334 u32 offset;
335 u32 mask;
336 };
337
338 enum airoha_pinctrl_mux_func {
339 AIROHA_FUNC_MUX,
340 AIROHA_FUNC_PWM_MUX,
341 AIROHA_FUNC_PWM_EXT_MUX,
342 };
343
344 struct airoha_pinctrl_func_group {
345 const char *name;
346 struct {
347 enum airoha_pinctrl_mux_func mux;
348 u32 offset;
349 u32 mask;
350 u32 val;
351 } regmap[2];
352 int regmap_size;
353 };
354
355 struct airoha_pinctrl_func {
356 const struct function_desc desc;
357 const struct airoha_pinctrl_func_group *groups;
358 u8 group_size;
359 };
360
361 struct airoha_pinctrl_conf {
362 u32 pin;
363 struct airoha_pinctrl_reg reg;
364 };
365
366 struct airoha_pinctrl_gpiochip {
367 struct gpio_chip chip;
368
369 /* gpio */
370 const u32 *data;
371 const u32 *dir;
372 const u32 *out;
373 /* irq */
374 const u32 *status;
375 const u32 *level;
376 const u32 *edge;
377
378 u32 irq_type[AIROHA_NUM_PINS];
379 };
380
381 struct airoha_pinctrl {
382 struct pinctrl_dev *ctrl;
383
384 struct regmap *chip_scu;
385 struct regmap *regmap;
386
387 struct airoha_pinctrl_gpiochip gpiochip;
388 };
389
390 static struct pinctrl_pin_desc airoha_pinctrl_pins[] = {
391 PINCTRL_PIN(0, "uart1_txd"),
392 PINCTRL_PIN(1, "uart1_rxd"),
393 PINCTRL_PIN(2, "i2c_scl"),
394 PINCTRL_PIN(3, "i2c_sda"),
395 PINCTRL_PIN(4, "spi_cs0"),
396 PINCTRL_PIN(5, "spi_clk"),
397 PINCTRL_PIN(6, "spi_mosi"),
398 PINCTRL_PIN(7, "spi_miso"),
399 PINCTRL_PIN(13, "gpio0"),
400 PINCTRL_PIN(14, "gpio1"),
401 PINCTRL_PIN(15, "gpio2"),
402 PINCTRL_PIN(16, "gpio3"),
403 PINCTRL_PIN(17, "gpio4"),
404 PINCTRL_PIN(18, "gpio5"),
405 PINCTRL_PIN(19, "gpio6"),
406 PINCTRL_PIN(20, "gpio7"),
407 PINCTRL_PIN(21, "gpio8"),
408 PINCTRL_PIN(22, "gpio9"),
409 PINCTRL_PIN(23, "gpio10"),
410 PINCTRL_PIN(24, "gpio11"),
411 PINCTRL_PIN(25, "gpio12"),
412 PINCTRL_PIN(26, "gpio13"),
413 PINCTRL_PIN(27, "gpio14"),
414 PINCTRL_PIN(28, "gpio15"),
415 PINCTRL_PIN(29, "gpio16"),
416 PINCTRL_PIN(30, "gpio17"),
417 PINCTRL_PIN(31, "gpio18"),
418 PINCTRL_PIN(32, "gpio19"),
419 PINCTRL_PIN(33, "gpio20"),
420 PINCTRL_PIN(34, "gpio21"),
421 PINCTRL_PIN(35, "gpio22"),
422 PINCTRL_PIN(36, "gpio23"),
423 PINCTRL_PIN(37, "gpio24"),
424 PINCTRL_PIN(38, "gpio25"),
425 PINCTRL_PIN(39, "gpio26"),
426 PINCTRL_PIN(40, "gpio27"),
427 PINCTRL_PIN(41, "gpio28"),
428 PINCTRL_PIN(42, "gpio29"),
429 PINCTRL_PIN(43, "gpio30"),
430 PINCTRL_PIN(44, "gpio31"),
431 PINCTRL_PIN(45, "gpio32"),
432 PINCTRL_PIN(46, "gpio33"),
433 PINCTRL_PIN(47, "gpio34"),
434 PINCTRL_PIN(48, "gpio35"),
435 PINCTRL_PIN(49, "gpio36"),
436 PINCTRL_PIN(50, "gpio37"),
437 PINCTRL_PIN(51, "gpio38"),
438 PINCTRL_PIN(52, "gpio39"),
439 PINCTRL_PIN(53, "gpio40"),
440 PINCTRL_PIN(54, "gpio41"),
441 PINCTRL_PIN(55, "gpio42"),
442 PINCTRL_PIN(56, "gpio43"),
443 PINCTRL_PIN(57, "gpio44"),
444 PINCTRL_PIN(58, "gpio45"),
445 PINCTRL_PIN(59, "gpio46"),
446 PINCTRL_PIN(61, "pcie_reset0"),
447 PINCTRL_PIN(62, "pcie_reset1"),
448 PINCTRL_PIN(63, "pcie_reset2"),
449 };
450
451 static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 };
452 static const int pon_tod_1pps_pins[] = { 46 };
453 static const int gsw_tod_1pps_pins[] = { 46 };
454 static const int sipo_pins[] = { 16, 17 };
455 static const int sipo_rclk_pins[] = { 16, 17, 43 };
456 static const int mdio_pins[] = { 14, 15 };
457 static const int uart2_pins[] = { 48, 55 };
458 static const int uart2_cts_rts_pins[] = { 46, 47 };
459 static const int hsuart_pins[] = { 28, 29 };
460 static const int hsuart_cts_rts_pins[] = { 26, 27 };
461 static const int uart4_pins[] = { 38, 39 };
462 static const int uart5_pins[] = { 18, 19 };
463 static const int i2c0_pins[] = { 2, 3 };
464 static const int i2c1_pins[] = { 14, 15 };
465 static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
466 static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
467 static const int i2s_pins[] = { 26, 27, 28, 29 };
468 static const int pcm1_pins[] = { 22, 23, 24, 25 };
469 static const int pcm2_pins[] = { 18, 19, 20, 21 };
470 static const int spi_quad_pins[] = { 32, 33 };
471 static const int spi_pins[] = { 4, 5, 6, 7 };
472 static const int spi_cs1_pins[] = { 34 };
473 static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
474 static const int pcm_spi_int_pins[] = { 14 };
475 static const int pcm_spi_rst_pins[] = { 15 };
476 static const int pcm_spi_cs1_pins[] = { 43 };
477 static const int pcm_spi_cs2_pins[] = { 40 };
478 static const int pcm_spi_cs2_p128_pins[] = { 40 };
479 static const int pcm_spi_cs2_p156_pins[] = { 40 };
480 static const int pcm_spi_cs3_pins[] = { 41 };
481 static const int pcm_spi_cs4_pins[] = { 42 };
482 static const int emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
483 static const int pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
484 static const int gpio0_pins[] = { 13 };
485 static const int gpio1_pins[] = { 14 };
486 static const int gpio2_pins[] = { 15 };
487 static const int gpio3_pins[] = { 16 };
488 static const int gpio4_pins[] = { 17 };
489 static const int gpio5_pins[] = { 18 };
490 static const int gpio6_pins[] = { 19 };
491 static const int gpio7_pins[] = { 20 };
492 static const int gpio8_pins[] = { 21 };
493 static const int gpio9_pins[] = { 22 };
494 static const int gpio10_pins[] = { 23 };
495 static const int gpio11_pins[] = { 24 };
496 static const int gpio12_pins[] = { 25 };
497 static const int gpio13_pins[] = { 26 };
498 static const int gpio14_pins[] = { 27 };
499 static const int gpio15_pins[] = { 28 };
500 static const int gpio16_pins[] = { 29 };
501 static const int gpio17_pins[] = { 30 };
502 static const int gpio18_pins[] = { 31 };
503 static const int gpio19_pins[] = { 32 };
504 static const int gpio20_pins[] = { 33 };
505 static const int gpio21_pins[] = { 34 };
506 static const int gpio22_pins[] = { 35 };
507 static const int gpio23_pins[] = { 36 };
508 static const int gpio24_pins[] = { 37 };
509 static const int gpio25_pins[] = { 38 };
510 static const int gpio26_pins[] = { 39 };
511 static const int gpio27_pins[] = { 40 };
512 static const int gpio28_pins[] = { 41 };
513 static const int gpio29_pins[] = { 42 };
514 static const int gpio30_pins[] = { 43 };
515 static const int gpio31_pins[] = { 44 };
516 static const int gpio33_pins[] = { 46 };
517 static const int gpio34_pins[] = { 47 };
518 static const int gpio35_pins[] = { 48 };
519 static const int gpio36_pins[] = { 49 };
520 static const int gpio37_pins[] = { 50 };
521 static const int gpio38_pins[] = { 51 };
522 static const int gpio39_pins[] = { 52 };
523 static const int gpio40_pins[] = { 53 };
524 static const int gpio41_pins[] = { 54 };
525 static const int gpio42_pins[] = { 55 };
526 static const int gpio43_pins[] = { 56 };
527 static const int gpio44_pins[] = { 57 };
528 static const int gpio45_pins[] = { 58 };
529 static const int gpio46_pins[] = { 59 };
530 static const int pcie_reset0_pins[] = { 61 };
531 static const int pcie_reset1_pins[] = { 62 };
532 static const int pcie_reset2_pins[] = { 63 };
533
534 static const struct pingroup airoha_pinctrl_groups[] = {
535 PINCTRL_PIN_GROUP(pon),
536 PINCTRL_PIN_GROUP(pon_tod_1pps),
537 PINCTRL_PIN_GROUP(gsw_tod_1pps),
538 PINCTRL_PIN_GROUP(sipo),
539 PINCTRL_PIN_GROUP(sipo_rclk),
540 PINCTRL_PIN_GROUP(mdio),
541 PINCTRL_PIN_GROUP(uart2),
542 PINCTRL_PIN_GROUP(uart2_cts_rts),
543 PINCTRL_PIN_GROUP(hsuart),
544 PINCTRL_PIN_GROUP(hsuart_cts_rts),
545 PINCTRL_PIN_GROUP(uart4),
546 PINCTRL_PIN_GROUP(uart5),
547 PINCTRL_PIN_GROUP(i2c0),
548 PINCTRL_PIN_GROUP(i2c1),
549 PINCTRL_PIN_GROUP(jtag_udi),
550 PINCTRL_PIN_GROUP(jtag_dfd),
551 PINCTRL_PIN_GROUP(i2s),
552 PINCTRL_PIN_GROUP(pcm1),
553 PINCTRL_PIN_GROUP(pcm2),
554 PINCTRL_PIN_GROUP(spi),
555 PINCTRL_PIN_GROUP(spi_quad),
556 PINCTRL_PIN_GROUP(spi_cs1),
557 PINCTRL_PIN_GROUP(pcm_spi),
558 PINCTRL_PIN_GROUP(pcm_spi_int),
559 PINCTRL_PIN_GROUP(pcm_spi_rst),
560 PINCTRL_PIN_GROUP(pcm_spi_cs1),
561 PINCTRL_PIN_GROUP(pcm_spi_cs2_p128),
562 PINCTRL_PIN_GROUP(pcm_spi_cs2_p156),
563 PINCTRL_PIN_GROUP(pcm_spi_cs2),
564 PINCTRL_PIN_GROUP(pcm_spi_cs3),
565 PINCTRL_PIN_GROUP(pcm_spi_cs4),
566 PINCTRL_PIN_GROUP(emmc),
567 PINCTRL_PIN_GROUP(pnand),
568 PINCTRL_PIN_GROUP(gpio0),
569 PINCTRL_PIN_GROUP(gpio1),
570 PINCTRL_PIN_GROUP(gpio2),
571 PINCTRL_PIN_GROUP(gpio3),
572 PINCTRL_PIN_GROUP(gpio4),
573 PINCTRL_PIN_GROUP(gpio5),
574 PINCTRL_PIN_GROUP(gpio6),
575 PINCTRL_PIN_GROUP(gpio7),
576 PINCTRL_PIN_GROUP(gpio8),
577 PINCTRL_PIN_GROUP(gpio9),
578 PINCTRL_PIN_GROUP(gpio10),
579 PINCTRL_PIN_GROUP(gpio11),
580 PINCTRL_PIN_GROUP(gpio12),
581 PINCTRL_PIN_GROUP(gpio13),
582 PINCTRL_PIN_GROUP(gpio14),
583 PINCTRL_PIN_GROUP(gpio15),
584 PINCTRL_PIN_GROUP(gpio16),
585 PINCTRL_PIN_GROUP(gpio17),
586 PINCTRL_PIN_GROUP(gpio18),
587 PINCTRL_PIN_GROUP(gpio19),
588 PINCTRL_PIN_GROUP(gpio20),
589 PINCTRL_PIN_GROUP(gpio21),
590 PINCTRL_PIN_GROUP(gpio22),
591 PINCTRL_PIN_GROUP(gpio23),
592 PINCTRL_PIN_GROUP(gpio24),
593 PINCTRL_PIN_GROUP(gpio25),
594 PINCTRL_PIN_GROUP(gpio26),
595 PINCTRL_PIN_GROUP(gpio27),
596 PINCTRL_PIN_GROUP(gpio28),
597 PINCTRL_PIN_GROUP(gpio29),
598 PINCTRL_PIN_GROUP(gpio30),
599 PINCTRL_PIN_GROUP(gpio31),
600 PINCTRL_PIN_GROUP(gpio33),
601 PINCTRL_PIN_GROUP(gpio34),
602 PINCTRL_PIN_GROUP(gpio35),
603 PINCTRL_PIN_GROUP(gpio36),
604 PINCTRL_PIN_GROUP(gpio37),
605 PINCTRL_PIN_GROUP(gpio38),
606 PINCTRL_PIN_GROUP(gpio39),
607 PINCTRL_PIN_GROUP(gpio40),
608 PINCTRL_PIN_GROUP(gpio41),
609 PINCTRL_PIN_GROUP(gpio42),
610 PINCTRL_PIN_GROUP(gpio43),
611 PINCTRL_PIN_GROUP(gpio44),
612 PINCTRL_PIN_GROUP(gpio45),
613 PINCTRL_PIN_GROUP(gpio46),
614 PINCTRL_PIN_GROUP(pcie_reset0),
615 PINCTRL_PIN_GROUP(pcie_reset1),
616 PINCTRL_PIN_GROUP(pcie_reset2),
617 };
618
619 static const char *const pon_groups[] = { "pon" };
620 static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
621 static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
622 static const char *const mdio_groups[] = { "mdio" };
623 static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
624 "hsuart_cts_rts", "uart4",
625 "uart5" };
626 static const char *const i2c_groups[] = { "i2c1" };
627 static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
628 static const char *const pcm_groups[] = { "pcm1", "pcm2" };
629 static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
630 static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
631 "pcm_spi_rst", "pcm_spi_cs1",
632 "pcm_spi_cs2_p156",
633 "pcm_spi_cs2_p128",
634 "pcm_spi_cs3", "pcm_spi_cs4" };
635 static const char *const i2s_groups[] = { "i2s" };
636 static const char *const emmc_groups[] = { "emmc" };
637 static const char *const pnand_groups[] = { "pnand" };
638 static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
639 "pcie_reset2" };
640 static const char *const pwm_groups[] = { "gpio0", "gpio1",
641 "gpio2", "gpio3",
642 "gpio4", "gpio5",
643 "gpio6", "gpio7",
644 "gpio8", "gpio9",
645 "gpio10", "gpio11",
646 "gpio12", "gpio13",
647 "gpio14", "gpio15",
648 "gpio16", "gpio17",
649 "gpio18", "gpio19",
650 "gpio20", "gpio21",
651 "gpio22", "gpio23",
652 "gpio24", "gpio25",
653 "gpio26", "gpio27",
654 "gpio28", "gpio29",
655 "gpio30", "gpio31",
656 "gpio36", "gpio37",
657 "gpio38", "gpio39",
658 "gpio40", "gpio41",
659 "gpio42", "gpio43",
660 "gpio44", "gpio45",
661 "gpio46", "gpio47" };
662 static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
663 "gpio35", "gpio42" };
664 static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
665 "gpio35", "gpio42" };
666 static const char *const phy3_led0_groups[] = { "gpio33", "gpio34",
667 "gpio35", "gpio42" };
668 static const char *const phy4_led0_groups[] = { "gpio33", "gpio34",
669 "gpio35", "gpio42" };
670 static const char *const phy1_led1_groups[] = { "gpio43", "gpio44",
671 "gpio45", "gpio46" };
672 static const char *const phy2_led1_groups[] = { "gpio43", "gpio44",
673 "gpio45", "gpio46" };
674 static const char *const phy3_led1_groups[] = { "gpio43", "gpio44",
675 "gpio45", "gpio46" };
676 static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
677 "gpio45", "gpio46" };
678
679 static const struct airoha_pinctrl_func_group pon_func_group[] = {
680 {
681 .name = "pon",
682 .regmap[0] = {
683 AIROHA_FUNC_MUX,
684 REG_GPIO_PON_MODE,
685 GPIO_PON_MODE_MASK,
686 GPIO_PON_MODE_MASK
687 },
688 .regmap_size = 1,
689 },
690 };
691
692 static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
693 {
694 .name = "pon_tod_1pps",
695 .regmap[0] = {
696 AIROHA_FUNC_MUX,
697 REG_GPIO_2ND_I2C_MODE,
698 PON_TOD_1PPS_MODE_MASK,
699 PON_TOD_1PPS_MODE_MASK
700 },
701 .regmap_size = 1,
702 }, {
703 .name = "gsw_tod_1pps",
704 .regmap[0] = {
705 AIROHA_FUNC_MUX,
706 REG_GPIO_2ND_I2C_MODE,
707 GSW_TOD_1PPS_MODE_MASK,
708 GSW_TOD_1PPS_MODE_MASK
709 },
710 .regmap_size = 1,
711 },
712 };
713
714 static const struct airoha_pinctrl_func_group sipo_func_group[] = {
715 {
716 .name = "sipo",
717 .regmap[0] = {
718 AIROHA_FUNC_MUX,
719 REG_GPIO_PON_MODE,
720 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
721 GPIO_SIPO_MODE_MASK
722 },
723 .regmap_size = 1,
724 }, {
725 .name = "sipo_rclk",
726 .regmap[0] = {
727 AIROHA_FUNC_MUX,
728 REG_GPIO_PON_MODE,
729 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
730 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
731 },
732 .regmap_size = 1,
733 },
734 };
735
736 static const struct airoha_pinctrl_func_group mdio_func_group[] = {
737 {
738 .name = "mdio",
739 .regmap[0] = {
740 AIROHA_FUNC_MUX,
741 REG_GPIO_PON_MODE,
742 GPIO_SGMII_MDIO_MODE_MASK,
743 GPIO_SGMII_MDIO_MODE_MASK
744 },
745 .regmap[1] = {
746 AIROHA_FUNC_MUX,
747 REG_GPIO_2ND_I2C_MODE,
748 GPIO_MDC_IO_MASTER_MODE_MODE,
749 GPIO_MDC_IO_MASTER_MODE_MODE
750 },
751 .regmap_size = 2,
752 },
753 };
754
755 static const struct airoha_pinctrl_func_group uart_func_group[] = {
756 {
757 .name = "uart2",
758 .regmap[0] = {
759 AIROHA_FUNC_MUX,
760 REG_GPIO_PON_MODE,
761 GPIO_UART2_MODE_MASK,
762 GPIO_UART2_MODE_MASK
763 },
764 .regmap_size = 1,
765 }, {
766 .name = "uart2_cts_rts",
767 .regmap[0] = {
768 AIROHA_FUNC_MUX,
769 REG_GPIO_PON_MODE,
770 GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
771 GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
772 },
773 .regmap_size = 1,
774 }, {
775 .name = "hsuart",
776 .regmap[0] = {
777 AIROHA_FUNC_MUX,
778 REG_GPIO_PON_MODE,
779 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
780 GPIO_HSUART_MODE_MASK
781 },
782 .regmap_size = 1,
783 },
784 {
785 .name = "hsuart_cts_rts",
786 .regmap[0] = {
787 AIROHA_FUNC_MUX,
788 REG_GPIO_PON_MODE,
789 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
790 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
791 },
792 .regmap_size = 1,
793 }, {
794 .name = "uart4",
795 .regmap[0] = {
796 AIROHA_FUNC_MUX,
797 REG_GPIO_PON_MODE,
798 GPIO_UART4_MODE_MASK,
799 GPIO_UART4_MODE_MASK
800 },
801 .regmap_size = 1,
802 }, {
803 .name = "uart5",
804 .regmap[0] = {
805 AIROHA_FUNC_MUX,
806 REG_GPIO_PON_MODE,
807 GPIO_UART5_MODE_MASK,
808 GPIO_UART5_MODE_MASK
809 },
810 .regmap_size = 1,
811 },
812 };
813
814 static const struct airoha_pinctrl_func_group i2c_func_group[] = {
815 {
816 .name = "i2c1",
817 .regmap[0] = {
818 AIROHA_FUNC_MUX,
819 REG_GPIO_2ND_I2C_MODE,
820 GPIO_2ND_I2C_MODE_MASK,
821 GPIO_2ND_I2C_MODE_MASK
822 },
823 .regmap_size = 1,
824 },
825 };
826
827 static const struct airoha_pinctrl_func_group jtag_func_group[] = {
828 {
829 .name = "jtag_udi",
830 .regmap[0] = {
831 AIROHA_FUNC_MUX,
832 REG_NPU_UART_EN,
833 JTAG_UDI_EN_MASK,
834 JTAG_UDI_EN_MASK
835 },
836 .regmap_size = 1,
837 }, {
838 .name = "jtag_dfd",
839 .regmap[0] = {
840 AIROHA_FUNC_MUX,
841 REG_NPU_UART_EN,
842 JTAG_DFD_EN_MASK,
843 JTAG_DFD_EN_MASK
844 },
845 .regmap_size = 1,
846 },
847 };
848
849 static const struct airoha_pinctrl_func_group pcm_func_group[] = {
850 {
851 .name = "pcm1",
852 .regmap[0] = {
853 AIROHA_FUNC_MUX,
854 REG_GPIO_SPI_CS1_MODE,
855 GPIO_PCM1_MODE_MASK,
856 GPIO_PCM1_MODE_MASK
857 },
858 .regmap_size = 1,
859 }, {
860 .name = "pcm2",
861 .regmap[0] = {
862 AIROHA_FUNC_MUX,
863 REG_GPIO_SPI_CS1_MODE,
864 GPIO_PCM2_MODE_MASK,
865 GPIO_PCM2_MODE_MASK
866 },
867 .regmap_size = 1,
868 },
869 };
870
871 static const struct airoha_pinctrl_func_group spi_func_group[] = {
872 {
873 .name = "spi_quad",
874 .regmap[0] = {
875 AIROHA_FUNC_MUX,
876 REG_GPIO_SPI_CS1_MODE,
877 GPIO_SPI_QUAD_MODE_MASK,
878 GPIO_SPI_QUAD_MODE_MASK
879 },
880 .regmap_size = 1,
881 }, {
882 .name = "spi_cs1",
883 .regmap[0] = {
884 AIROHA_FUNC_MUX,
885 REG_GPIO_SPI_CS1_MODE,
886 GPIO_SPI_CS1_MODE_MASK,
887 GPIO_SPI_CS1_MODE_MASK
888 },
889 .regmap_size = 1,
890 }, {
891 .name = "spi_cs2",
892 .regmap[0] = {
893 AIROHA_FUNC_MUX,
894 REG_GPIO_SPI_CS1_MODE,
895 GPIO_SPI_CS2_MODE_MASK,
896 GPIO_SPI_CS2_MODE_MASK
897 },
898 .regmap_size = 1,
899 }, {
900 .name = "spi_cs3",
901 .regmap[0] = {
902 AIROHA_FUNC_MUX,
903 REG_GPIO_SPI_CS1_MODE,
904 GPIO_SPI_CS3_MODE_MASK,
905 GPIO_SPI_CS3_MODE_MASK
906 },
907 .regmap_size = 1,
908 }, {
909 .name = "spi_cs4",
910 .regmap[0] = {
911 AIROHA_FUNC_MUX,
912 REG_GPIO_SPI_CS1_MODE,
913 GPIO_SPI_CS4_MODE_MASK,
914 GPIO_SPI_CS4_MODE_MASK
915 },
916 .regmap_size = 1,
917 },
918 };
919
920 static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
921 {
922 .name = "pcm_spi",
923 .regmap[0] = {
924 AIROHA_FUNC_MUX,
925 REG_GPIO_SPI_CS1_MODE,
926 GPIO_PCM_SPI_MODE_MASK,
927 GPIO_PCM_SPI_MODE_MASK
928 },
929 .regmap_size = 1,
930 }, {
931 .name = "pcm_spi_int",
932 .regmap[0] = {
933 AIROHA_FUNC_MUX,
934 REG_GPIO_SPI_CS1_MODE,
935 GPIO_PCM_INT_MODE_MASK,
936 GPIO_PCM_INT_MODE_MASK
937 },
938 .regmap_size = 1,
939 }, {
940 .name = "pcm_spi_rst",
941 .regmap[0] = {
942 AIROHA_FUNC_MUX,
943 REG_GPIO_SPI_CS1_MODE,
944 GPIO_PCM_RESET_MODE_MASK,
945 GPIO_PCM_RESET_MODE_MASK
946 },
947 .regmap_size = 1,
948 }, {
949 .name = "pcm_spi_cs1",
950 .regmap[0] = {
951 AIROHA_FUNC_MUX,
952 REG_GPIO_SPI_CS1_MODE,
953 GPIO_PCM_SPI_CS1_MODE_MASK,
954 GPIO_PCM_SPI_CS1_MODE_MASK
955 },
956 .regmap_size = 1,
957 }, {
958 .name = "pcm_spi_cs2_p128",
959 .regmap[0] = {
960 AIROHA_FUNC_MUX,
961 REG_GPIO_SPI_CS1_MODE,
962 GPIO_PCM_SPI_CS2_MODE_P128_MASK,
963 GPIO_PCM_SPI_CS2_MODE_P128_MASK
964 },
965 .regmap_size = 1,
966 }, {
967 .name = "pcm_spi_cs2_p156",
968 .regmap[0] = {
969 AIROHA_FUNC_MUX,
970 REG_GPIO_SPI_CS1_MODE,
971 GPIO_PCM_SPI_CS2_MODE_P156_MASK,
972 GPIO_PCM_SPI_CS2_MODE_P156_MASK
973 },
974 .regmap_size = 1,
975 }, {
976 .name = "pcm_spi_cs3",
977 .regmap[0] = {
978 AIROHA_FUNC_MUX,
979 REG_GPIO_SPI_CS1_MODE,
980 GPIO_PCM_SPI_CS3_MODE_MASK,
981 GPIO_PCM_SPI_CS3_MODE_MASK
982 },
983 .regmap_size = 1,
984 }, {
985 .name = "pcm_spi_cs4",
986 .regmap[0] = {
987 AIROHA_FUNC_MUX,
988 REG_GPIO_SPI_CS1_MODE,
989 GPIO_PCM_SPI_CS4_MODE_MASK,
990 GPIO_PCM_SPI_CS4_MODE_MASK
991 },
992 .regmap_size = 1,
993 },
994 };
995
996 static const struct airoha_pinctrl_func_group i2s_func_group[] = {
997 {
998 .name = "i2s",
999 .regmap[0] = {
1000 AIROHA_FUNC_MUX,
1001 REG_GPIO_2ND_I2C_MODE,
1002 GPIO_I2S_MODE_MASK,
1003 GPIO_I2S_MODE_MASK
1004 },
1005 .regmap_size = 1,
1006 },
1007 };
1008
1009 static const struct airoha_pinctrl_func_group emmc_func_group[] = {
1010 {
1011 .name = "emmc",
1012 .regmap[0] = {
1013 AIROHA_FUNC_MUX,
1014 REG_GPIO_PON_MODE,
1015 GPIO_EMMC_MODE_MASK,
1016 GPIO_EMMC_MODE_MASK
1017 },
1018 .regmap_size = 1,
1019 },
1020 };
1021
1022 static const struct airoha_pinctrl_func_group pnand_func_group[] = {
1023 {
1024 .name = "pnand",
1025 .regmap[0] = {
1026 AIROHA_FUNC_MUX,
1027 REG_GPIO_PON_MODE,
1028 GPIO_PARALLEL_NAND_MODE_MASK,
1029 GPIO_PARALLEL_NAND_MODE_MASK
1030 },
1031 .regmap_size = 1,
1032 },
1033 };
1034
1035 static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
1036 {
1037 .name = "pcie_reset0",
1038 .regmap[0] = {
1039 AIROHA_FUNC_MUX,
1040 REG_GPIO_PON_MODE,
1041 GPIO_PCIE_RESET0_MASK,
1042 GPIO_PCIE_RESET0_MASK
1043 },
1044 .regmap_size = 1,
1045 }, {
1046 .name = "pcie_reset1",
1047 .regmap[0] = {
1048 AIROHA_FUNC_MUX,
1049 REG_GPIO_PON_MODE,
1050 GPIO_PCIE_RESET1_MASK,
1051 GPIO_PCIE_RESET1_MASK
1052 },
1053 .regmap_size = 1,
1054 }, {
1055 .name = "pcie_reset2",
1056 .regmap[0] = {
1057 AIROHA_FUNC_MUX,
1058 REG_GPIO_PON_MODE,
1059 GPIO_PCIE_RESET2_MASK,
1060 GPIO_PCIE_RESET2_MASK
1061 },
1062 .regmap_size = 1,
1063 },
1064 };
1065
1066 /* PWM */
1067 static const struct airoha_pinctrl_func_group pwm_func_group[] = {
1068 {
1069 .name = "gpio0",
1070 .regmap[0] = {
1071 AIROHA_FUNC_PWM_MUX,
1072 REG_GPIO_FLASH_MODE_CFG,
1073 GPIO0_FLASH_MODE_CFG,
1074 GPIO0_FLASH_MODE_CFG
1075 },
1076 .regmap_size = 1,
1077 }, {
1078 .name = "gpio1",
1079 .regmap[0] = {
1080 AIROHA_FUNC_PWM_MUX,
1081 REG_GPIO_FLASH_MODE_CFG,
1082 GPIO1_FLASH_MODE_CFG,
1083 GPIO1_FLASH_MODE_CFG
1084 },
1085 .regmap_size = 1,
1086 }, {
1087 .name = "gpio2",
1088 .regmap[0] = {
1089 AIROHA_FUNC_PWM_MUX,
1090 REG_GPIO_FLASH_MODE_CFG,
1091 GPIO2_FLASH_MODE_CFG,
1092 GPIO2_FLASH_MODE_CFG
1093 },
1094 .regmap_size = 1,
1095 }, {
1096 .name = "gpio3",
1097 .regmap[0] = {
1098 AIROHA_FUNC_PWM_MUX,
1099 REG_GPIO_FLASH_MODE_CFG,
1100 GPIO3_FLASH_MODE_CFG,
1101 GPIO3_FLASH_MODE_CFG
1102 },
1103 .regmap_size = 1,
1104 }, {
1105 .name = "gpio4",
1106 .regmap[0] = {
1107 AIROHA_FUNC_PWM_MUX,
1108 REG_GPIO_FLASH_MODE_CFG,
1109 GPIO4_FLASH_MODE_CFG,
1110 GPIO4_FLASH_MODE_CFG
1111 },
1112 .regmap_size = 1,
1113 }, {
1114 .name = "gpio5",
1115 .regmap[0] = {
1116 AIROHA_FUNC_PWM_MUX,
1117 REG_GPIO_FLASH_MODE_CFG,
1118 GPIO5_FLASH_MODE_CFG,
1119 GPIO5_FLASH_MODE_CFG
1120 },
1121 .regmap_size = 1,
1122 }, {
1123 .name = "gpio6",
1124 .regmap[0] = {
1125 AIROHA_FUNC_PWM_MUX,
1126 REG_GPIO_FLASH_MODE_CFG,
1127 GPIO6_FLASH_MODE_CFG,
1128 GPIO6_FLASH_MODE_CFG
1129 },
1130 .regmap_size = 1,
1131 }, {
1132 .name = "gpio7",
1133 .regmap[0] = {
1134 AIROHA_FUNC_PWM_MUX,
1135 REG_GPIO_FLASH_MODE_CFG,
1136 GPIO7_FLASH_MODE_CFG,
1137 GPIO7_FLASH_MODE_CFG
1138 },
1139 .regmap_size = 1,
1140 }, {
1141 .name = "gpio8",
1142 .regmap[0] = {
1143 AIROHA_FUNC_PWM_MUX,
1144 REG_GPIO_FLASH_MODE_CFG,
1145 GPIO8_FLASH_MODE_CFG,
1146 GPIO8_FLASH_MODE_CFG
1147 },
1148 .regmap_size = 1,
1149 }, {
1150 .name = "gpio9",
1151 .regmap[0] = {
1152 AIROHA_FUNC_PWM_MUX,
1153 REG_GPIO_FLASH_MODE_CFG,
1154 GPIO9_FLASH_MODE_CFG,
1155 GPIO9_FLASH_MODE_CFG
1156 },
1157 .regmap_size = 1,
1158 }, {
1159 .name = "gpio10",
1160 .regmap[0] = {
1161 AIROHA_FUNC_PWM_MUX,
1162 REG_GPIO_FLASH_MODE_CFG,
1163 GPIO10_FLASH_MODE_CFG,
1164 GPIO10_FLASH_MODE_CFG
1165 },
1166 .regmap_size = 1,
1167 }, {
1168 .name = "gpio11",
1169 .regmap[0] = {
1170 AIROHA_FUNC_PWM_MUX,
1171 REG_GPIO_FLASH_MODE_CFG,
1172 GPIO11_FLASH_MODE_CFG,
1173 GPIO11_FLASH_MODE_CFG
1174 },
1175 .regmap_size = 1,
1176 }, {
1177 .name = "gpio12",
1178 .regmap[0] = {
1179 AIROHA_FUNC_PWM_MUX,
1180 REG_GPIO_FLASH_MODE_CFG,
1181 GPIO12_FLASH_MODE_CFG,
1182 GPIO12_FLASH_MODE_CFG
1183 },
1184 .regmap_size = 1,
1185 }, {
1186 .name = "gpio13",
1187 .regmap[0] = {
1188 AIROHA_FUNC_PWM_MUX,
1189 REG_GPIO_FLASH_MODE_CFG,
1190 GPIO13_FLASH_MODE_CFG,
1191 GPIO13_FLASH_MODE_CFG
1192 },
1193 .regmap_size = 1,
1194 }, {
1195 .name = "gpio14",
1196 .regmap[0] = {
1197 AIROHA_FUNC_PWM_MUX,
1198 REG_GPIO_FLASH_MODE_CFG,
1199 GPIO14_FLASH_MODE_CFG,
1200 GPIO14_FLASH_MODE_CFG
1201 },
1202 .regmap_size = 1,
1203 }, {
1204 .name = "gpio15",
1205 .regmap[0] = {
1206 AIROHA_FUNC_PWM_MUX,
1207 REG_GPIO_FLASH_MODE_CFG,
1208 GPIO15_FLASH_MODE_CFG,
1209 GPIO15_FLASH_MODE_CFG
1210 },
1211 .regmap_size = 1,
1212 }, {
1213 .name = "gpio16",
1214 .regmap[0] = {
1215 AIROHA_FUNC_PWM_EXT_MUX,
1216 REG_GPIO_FLASH_MODE_CFG_EXT,
1217 GPIO16_FLASH_MODE_CFG,
1218 GPIO16_FLASH_MODE_CFG
1219 },
1220 .regmap_size = 1,
1221 }, {
1222 .name = "gpio17",
1223 .regmap[0] = {
1224 AIROHA_FUNC_PWM_EXT_MUX,
1225 REG_GPIO_FLASH_MODE_CFG_EXT,
1226 GPIO17_FLASH_MODE_CFG,
1227 GPIO17_FLASH_MODE_CFG
1228 },
1229 .regmap_size = 1,
1230 }, {
1231 .name = "gpio18",
1232 .regmap[0] = {
1233 AIROHA_FUNC_PWM_EXT_MUX,
1234 REG_GPIO_FLASH_MODE_CFG_EXT,
1235 GPIO18_FLASH_MODE_CFG,
1236 GPIO18_FLASH_MODE_CFG
1237 },
1238 .regmap_size = 1,
1239 }, {
1240 .name = "gpio19",
1241 .regmap[0] = {
1242 AIROHA_FUNC_PWM_EXT_MUX,
1243 REG_GPIO_FLASH_MODE_CFG_EXT,
1244 GPIO19_FLASH_MODE_CFG,
1245 GPIO19_FLASH_MODE_CFG
1246 },
1247 .regmap_size = 1,
1248 }, {
1249 .name = "gpio20",
1250 .regmap[0] = {
1251 AIROHA_FUNC_PWM_EXT_MUX,
1252 REG_GPIO_FLASH_MODE_CFG_EXT,
1253 GPIO20_FLASH_MODE_CFG,
1254 GPIO20_FLASH_MODE_CFG
1255 },
1256 .regmap_size = 1,
1257 }, {
1258 .name = "gpio21",
1259 .regmap[0] = {
1260 AIROHA_FUNC_PWM_EXT_MUX,
1261 REG_GPIO_FLASH_MODE_CFG_EXT,
1262 GPIO21_FLASH_MODE_CFG,
1263 GPIO21_FLASH_MODE_CFG
1264 },
1265 .regmap_size = 1,
1266 }, {
1267 .name = "gpio22",
1268 .regmap[0] = {
1269 AIROHA_FUNC_PWM_EXT_MUX,
1270 REG_GPIO_FLASH_MODE_CFG_EXT,
1271 GPIO22_FLASH_MODE_CFG,
1272 GPIO22_FLASH_MODE_CFG
1273 },
1274 .regmap_size = 1,
1275 }, {
1276 .name = "gpio23",
1277 .regmap[0] = {
1278 AIROHA_FUNC_PWM_EXT_MUX,
1279 REG_GPIO_FLASH_MODE_CFG_EXT,
1280 GPIO23_FLASH_MODE_CFG,
1281 GPIO23_FLASH_MODE_CFG
1282 },
1283 .regmap_size = 1,
1284 }, {
1285 .name = "gpio24",
1286 .regmap[0] = {
1287 AIROHA_FUNC_PWM_EXT_MUX,
1288 REG_GPIO_FLASH_MODE_CFG_EXT,
1289 GPIO24_FLASH_MODE_CFG,
1290 GPIO24_FLASH_MODE_CFG
1291 },
1292 .regmap_size = 1,
1293 }, {
1294 .name = "gpio25",
1295 .regmap[0] = {
1296 AIROHA_FUNC_PWM_EXT_MUX,
1297 REG_GPIO_FLASH_MODE_CFG_EXT,
1298 GPIO25_FLASH_MODE_CFG,
1299 GPIO25_FLASH_MODE_CFG
1300 },
1301 .regmap_size = 1,
1302 }, {
1303 .name = "gpio26",
1304 .regmap[0] = {
1305 AIROHA_FUNC_PWM_EXT_MUX,
1306 REG_GPIO_FLASH_MODE_CFG_EXT,
1307 GPIO26_FLASH_MODE_CFG,
1308 GPIO26_FLASH_MODE_CFG
1309 },
1310 .regmap_size = 1,
1311 }, {
1312 .name = "gpio27",
1313 .regmap[0] = {
1314 AIROHA_FUNC_PWM_EXT_MUX,
1315 REG_GPIO_FLASH_MODE_CFG_EXT,
1316 GPIO27_FLASH_MODE_CFG,
1317 GPIO27_FLASH_MODE_CFG
1318 },
1319 .regmap_size = 1,
1320 }, {
1321 .name = "gpio28",
1322 .regmap[0] = {
1323 AIROHA_FUNC_PWM_EXT_MUX,
1324 REG_GPIO_FLASH_MODE_CFG_EXT,
1325 GPIO28_FLASH_MODE_CFG,
1326 GPIO28_FLASH_MODE_CFG
1327 },
1328 .regmap_size = 1,
1329 }, {
1330 .name = "gpio29",
1331 .regmap[0] = {
1332 AIROHA_FUNC_PWM_EXT_MUX,
1333 REG_GPIO_FLASH_MODE_CFG_EXT,
1334 GPIO29_FLASH_MODE_CFG,
1335 GPIO29_FLASH_MODE_CFG
1336 },
1337 .regmap_size = 1,
1338 }, {
1339 .name = "gpio30",
1340 .regmap[0] = {
1341 AIROHA_FUNC_PWM_EXT_MUX,
1342 REG_GPIO_FLASH_MODE_CFG_EXT,
1343 GPIO30_FLASH_MODE_CFG,
1344 GPIO30_FLASH_MODE_CFG
1345 },
1346 .regmap_size = 1,
1347 }, {
1348 .name = "gpio31",
1349 .regmap[0] = {
1350 AIROHA_FUNC_PWM_EXT_MUX,
1351 REG_GPIO_FLASH_MODE_CFG_EXT,
1352 GPIO31_FLASH_MODE_CFG,
1353 GPIO31_FLASH_MODE_CFG
1354 },
1355 .regmap_size = 1,
1356 }, {
1357 .name = "gpio36",
1358 .regmap[0] = {
1359 AIROHA_FUNC_PWM_EXT_MUX,
1360 REG_GPIO_FLASH_MODE_CFG_EXT,
1361 GPIO36_FLASH_MODE_CFG,
1362 GPIO36_FLASH_MODE_CFG
1363 },
1364 .regmap_size = 1,
1365 }, {
1366 .name = "gpio37",
1367 .regmap[0] = {
1368 AIROHA_FUNC_PWM_EXT_MUX,
1369 REG_GPIO_FLASH_MODE_CFG_EXT,
1370 GPIO37_FLASH_MODE_CFG,
1371 GPIO37_FLASH_MODE_CFG
1372 },
1373 .regmap_size = 1,
1374 }, {
1375 .name = "gpio38",
1376 .regmap[0] = {
1377 AIROHA_FUNC_PWM_EXT_MUX,
1378 REG_GPIO_FLASH_MODE_CFG_EXT,
1379 GPIO38_FLASH_MODE_CFG,
1380 GPIO38_FLASH_MODE_CFG
1381 },
1382 .regmap_size = 1,
1383 }, {
1384 .name = "gpio39",
1385 .regmap[0] = {
1386 AIROHA_FUNC_PWM_EXT_MUX,
1387 REG_GPIO_FLASH_MODE_CFG_EXT,
1388 GPIO39_FLASH_MODE_CFG,
1389 GPIO39_FLASH_MODE_CFG
1390 },
1391 .regmap_size = 1,
1392 }, {
1393 .name = "gpio40",
1394 .regmap[0] = {
1395 AIROHA_FUNC_PWM_EXT_MUX,
1396 REG_GPIO_FLASH_MODE_CFG_EXT,
1397 GPIO40_FLASH_MODE_CFG,
1398 GPIO40_FLASH_MODE_CFG
1399 },
1400 .regmap_size = 1,
1401 }, {
1402 .name = "gpio41",
1403 .regmap[0] = {
1404 AIROHA_FUNC_PWM_EXT_MUX,
1405 REG_GPIO_FLASH_MODE_CFG_EXT,
1406 GPIO41_FLASH_MODE_CFG,
1407 GPIO41_FLASH_MODE_CFG
1408 },
1409 .regmap_size = 1,
1410 }, {
1411 .name = "gpio42",
1412 .regmap[0] = {
1413 AIROHA_FUNC_PWM_EXT_MUX,
1414 REG_GPIO_FLASH_MODE_CFG_EXT,
1415 GPIO42_FLASH_MODE_CFG,
1416 GPIO42_FLASH_MODE_CFG
1417 },
1418 .regmap_size = 1,
1419 }, {
1420 .name = "gpio43",
1421 .regmap[0] = {
1422 AIROHA_FUNC_PWM_EXT_MUX,
1423 REG_GPIO_FLASH_MODE_CFG_EXT,
1424 GPIO43_FLASH_MODE_CFG,
1425 GPIO43_FLASH_MODE_CFG
1426 },
1427 .regmap_size = 1,
1428 }, {
1429 .name = "gpio44",
1430 .regmap[0] = {
1431 AIROHA_FUNC_PWM_EXT_MUX,
1432 REG_GPIO_FLASH_MODE_CFG_EXT,
1433 GPIO44_FLASH_MODE_CFG,
1434 GPIO44_FLASH_MODE_CFG
1435 },
1436 .regmap_size = 1,
1437 }, {
1438 .name = "gpio45",
1439 .regmap[0] = {
1440 AIROHA_FUNC_PWM_EXT_MUX,
1441 REG_GPIO_FLASH_MODE_CFG_EXT,
1442 GPIO45_FLASH_MODE_CFG,
1443 GPIO45_FLASH_MODE_CFG
1444 },
1445 .regmap_size = 1,
1446 }, {
1447 .name = "gpio46",
1448 .regmap[0] = {
1449 AIROHA_FUNC_PWM_EXT_MUX,
1450 REG_GPIO_FLASH_MODE_CFG_EXT,
1451 GPIO46_FLASH_MODE_CFG,
1452 GPIO46_FLASH_MODE_CFG
1453 },
1454 .regmap_size = 1,
1455 }, {
1456 .name = "gpio47",
1457 .regmap[0] = {
1458 AIROHA_FUNC_PWM_EXT_MUX,
1459 REG_GPIO_FLASH_MODE_CFG_EXT,
1460 GPIO47_FLASH_MODE_CFG,
1461 GPIO47_FLASH_MODE_CFG
1462 },
1463 .regmap_size = 1,
1464 },
1465 };
1466
1467 static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
1468 {
1469 .name = "gpio33",
1470 .regmap[0] = {
1471 AIROHA_FUNC_MUX,
1472 REG_GPIO_2ND_I2C_MODE,
1473 GPIO_LAN0_LED0_MODE_MASK,
1474 GPIO_LAN0_LED0_MODE_MASK
1475 },
1476 .regmap[1] = {
1477 AIROHA_FUNC_MUX,
1478 REG_LAN_LED0_MAPPING,
1479 LAN1_LED_MAPPING_MASK,
1480 LAN1_PHY1_LED_MAP
1481 },
1482 .regmap_size = 2,
1483 }, {
1484 .name = "gpio34",
1485 .regmap[0] = {
1486 AIROHA_FUNC_MUX,
1487 REG_GPIO_2ND_I2C_MODE,
1488 GPIO_LAN1_LED0_MODE_MASK,
1489 GPIO_LAN1_LED0_MODE_MASK
1490 },
1491 .regmap[1] = {
1492 AIROHA_FUNC_MUX,
1493 REG_LAN_LED0_MAPPING,
1494 LAN2_LED_MAPPING_MASK,
1495 LAN2_PHY1_LED_MAP
1496 },
1497 .regmap_size = 2,
1498 }, {
1499 .name = "gpio35",
1500 .regmap[0] = {
1501 AIROHA_FUNC_MUX,
1502 REG_GPIO_2ND_I2C_MODE,
1503 GPIO_LAN2_LED0_MODE_MASK,
1504 GPIO_LAN2_LED0_MODE_MASK
1505 },
1506 .regmap[1] = {
1507 AIROHA_FUNC_MUX,
1508 REG_LAN_LED0_MAPPING,
1509 LAN3_LED_MAPPING_MASK,
1510 LAN3_PHY1_LED_MAP
1511 },
1512 .regmap_size = 2,
1513 }, {
1514 .name = "gpio42",
1515 .regmap[0] = {
1516 AIROHA_FUNC_MUX,
1517 REG_GPIO_2ND_I2C_MODE,
1518 GPIO_LAN3_LED0_MODE_MASK,
1519 GPIO_LAN3_LED0_MODE_MASK
1520 },
1521 .regmap[1] = {
1522 AIROHA_FUNC_MUX,
1523 REG_LAN_LED0_MAPPING,
1524 LAN4_LED_MAPPING_MASK,
1525 LAN4_PHY1_LED_MAP
1526 },
1527 .regmap_size = 2,
1528 },
1529 };
1530
1531 static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
1532 {
1533 .name = "gpio33",
1534 .regmap[0] = {
1535 AIROHA_FUNC_MUX,
1536 REG_GPIO_2ND_I2C_MODE,
1537 GPIO_LAN0_LED0_MODE_MASK,
1538 GPIO_LAN0_LED0_MODE_MASK
1539 },
1540 .regmap[1] = {
1541 AIROHA_FUNC_MUX,
1542 REG_LAN_LED0_MAPPING,
1543 LAN1_LED_MAPPING_MASK,
1544 LAN1_PHY2_LED_MAP
1545 },
1546 .regmap_size = 2,
1547 }, {
1548 .name = "gpio34",
1549 .regmap[0] = {
1550 AIROHA_FUNC_MUX,
1551 REG_GPIO_2ND_I2C_MODE,
1552 GPIO_LAN1_LED0_MODE_MASK,
1553 GPIO_LAN1_LED0_MODE_MASK
1554 },
1555 .regmap[1] = {
1556 AIROHA_FUNC_MUX,
1557 REG_LAN_LED0_MAPPING,
1558 LAN2_LED_MAPPING_MASK,
1559 LAN2_PHY2_LED_MAP
1560 },
1561 .regmap_size = 2,
1562 }, {
1563 .name = "gpio35",
1564 .regmap[0] = {
1565 AIROHA_FUNC_MUX,
1566 REG_GPIO_2ND_I2C_MODE,
1567 GPIO_LAN2_LED0_MODE_MASK,
1568 GPIO_LAN2_LED0_MODE_MASK
1569 },
1570 .regmap[1] = {
1571 AIROHA_FUNC_MUX,
1572 REG_LAN_LED0_MAPPING,
1573 LAN3_LED_MAPPING_MASK,
1574 LAN3_PHY2_LED_MAP
1575 },
1576 .regmap_size = 2,
1577 }, {
1578 .name = "gpio42",
1579 .regmap[0] = {
1580 AIROHA_FUNC_MUX,
1581 REG_GPIO_2ND_I2C_MODE,
1582 GPIO_LAN3_LED0_MODE_MASK,
1583 GPIO_LAN3_LED0_MODE_MASK
1584 },
1585 .regmap[1] = {
1586 AIROHA_FUNC_MUX,
1587 REG_LAN_LED0_MAPPING,
1588 LAN4_LED_MAPPING_MASK,
1589 LAN4_PHY2_LED_MAP
1590 },
1591 .regmap_size = 2,
1592 },
1593 };
1594
1595 static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
1596 {
1597 .name = "gpio33",
1598 .regmap[0] = {
1599 AIROHA_FUNC_MUX,
1600 REG_GPIO_2ND_I2C_MODE,
1601 GPIO_LAN0_LED0_MODE_MASK,
1602 GPIO_LAN0_LED0_MODE_MASK
1603 },
1604 .regmap[1] = {
1605 AIROHA_FUNC_MUX,
1606 REG_LAN_LED0_MAPPING,
1607 LAN1_LED_MAPPING_MASK,
1608 LAN1_PHY3_LED_MAP
1609 },
1610 .regmap_size = 2,
1611 }, {
1612 .name = "gpio34",
1613 .regmap[0] = {
1614 AIROHA_FUNC_MUX,
1615 REG_GPIO_2ND_I2C_MODE,
1616 GPIO_LAN1_LED0_MODE_MASK,
1617 GPIO_LAN1_LED0_MODE_MASK
1618 },
1619 .regmap[1] = {
1620 AIROHA_FUNC_MUX,
1621 REG_LAN_LED0_MAPPING,
1622 LAN2_LED_MAPPING_MASK,
1623 LAN2_PHY3_LED_MAP
1624 },
1625 .regmap_size = 2,
1626 }, {
1627 .name = "gpio35",
1628 .regmap[0] = {
1629 AIROHA_FUNC_MUX,
1630 REG_GPIO_2ND_I2C_MODE,
1631 GPIO_LAN2_LED0_MODE_MASK,
1632 GPIO_LAN2_LED0_MODE_MASK
1633 },
1634 .regmap[1] = {
1635 AIROHA_FUNC_MUX,
1636 REG_LAN_LED0_MAPPING,
1637 LAN3_LED_MAPPING_MASK,
1638 LAN3_PHY3_LED_MAP
1639 },
1640 .regmap_size = 2,
1641 }, {
1642 .name = "gpio42",
1643 .regmap[0] = {
1644 AIROHA_FUNC_MUX,
1645 REG_GPIO_2ND_I2C_MODE,
1646 GPIO_LAN3_LED0_MODE_MASK,
1647 GPIO_LAN3_LED0_MODE_MASK
1648 },
1649 .regmap[1] = {
1650 AIROHA_FUNC_MUX,
1651 REG_LAN_LED0_MAPPING,
1652 LAN4_LED_MAPPING_MASK,
1653 LAN4_PHY3_LED_MAP
1654 },
1655 .regmap_size = 2,
1656 },
1657 };
1658
1659 static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
1660 {
1661 .name = "gpio33",
1662 .regmap[0] = {
1663 AIROHA_FUNC_MUX,
1664 REG_GPIO_2ND_I2C_MODE,
1665 GPIO_LAN0_LED0_MODE_MASK,
1666 GPIO_LAN0_LED0_MODE_MASK
1667 },
1668 .regmap[1] = {
1669 AIROHA_FUNC_MUX,
1670 REG_LAN_LED0_MAPPING,
1671 LAN1_LED_MAPPING_MASK,
1672 LAN1_PHY4_LED_MAP
1673 },
1674 .regmap_size = 2,
1675 }, {
1676 .name = "gpio34",
1677 .regmap[0] = {
1678 AIROHA_FUNC_MUX,
1679 REG_GPIO_2ND_I2C_MODE,
1680 GPIO_LAN1_LED0_MODE_MASK,
1681 GPIO_LAN1_LED0_MODE_MASK
1682 },
1683 .regmap[1] = {
1684 AIROHA_FUNC_MUX,
1685 REG_LAN_LED0_MAPPING,
1686 LAN2_LED_MAPPING_MASK,
1687 LAN2_PHY4_LED_MAP
1688 },
1689 .regmap_size = 2,
1690 }, {
1691 .name = "gpio35",
1692 .regmap[0] = {
1693 AIROHA_FUNC_MUX,
1694 REG_GPIO_2ND_I2C_MODE,
1695 GPIO_LAN2_LED0_MODE_MASK,
1696 GPIO_LAN2_LED0_MODE_MASK
1697 },
1698 .regmap[1] = {
1699 AIROHA_FUNC_MUX,
1700 REG_LAN_LED0_MAPPING,
1701 LAN3_LED_MAPPING_MASK,
1702 LAN3_PHY4_LED_MAP
1703 },
1704 .regmap_size = 2,
1705 }, {
1706 .name = "gpio42",
1707 .regmap[0] = {
1708 AIROHA_FUNC_MUX,
1709 REG_GPIO_2ND_I2C_MODE,
1710 GPIO_LAN3_LED0_MODE_MASK,
1711 GPIO_LAN3_LED0_MODE_MASK
1712 },
1713 .regmap[1] = {
1714 AIROHA_FUNC_MUX,
1715 REG_LAN_LED0_MAPPING,
1716 LAN4_LED_MAPPING_MASK,
1717 LAN4_PHY4_LED_MAP
1718 },
1719 .regmap_size = 2,
1720 },
1721 };
1722
1723 static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
1724 {
1725 .name = "gpio43",
1726 .regmap[0] = {
1727 AIROHA_FUNC_MUX,
1728 REG_GPIO_2ND_I2C_MODE,
1729 GPIO_LAN0_LED1_MODE_MASK,
1730 GPIO_LAN0_LED1_MODE_MASK
1731 },
1732 .regmap[1] = {
1733 AIROHA_FUNC_MUX,
1734 REG_LAN_LED1_MAPPING,
1735 LAN1_LED_MAPPING_MASK,
1736 LAN1_PHY1_LED_MAP
1737 },
1738 .regmap_size = 2,
1739 }, {
1740 .name = "gpio44",
1741 .regmap[0] = {
1742 AIROHA_FUNC_MUX,
1743 REG_GPIO_2ND_I2C_MODE,
1744 GPIO_LAN1_LED1_MODE_MASK,
1745 GPIO_LAN1_LED1_MODE_MASK
1746 },
1747 .regmap[1] = {
1748 AIROHA_FUNC_MUX,
1749 REG_LAN_LED1_MAPPING,
1750 LAN2_LED_MAPPING_MASK,
1751 LAN2_PHY1_LED_MAP
1752 },
1753 .regmap_size = 2,
1754 }, {
1755 .name = "gpio45",
1756 .regmap[0] = {
1757 AIROHA_FUNC_MUX,
1758 REG_GPIO_2ND_I2C_MODE,
1759 GPIO_LAN2_LED1_MODE_MASK,
1760 GPIO_LAN2_LED1_MODE_MASK
1761 },
1762 .regmap[1] = {
1763 AIROHA_FUNC_MUX,
1764 REG_LAN_LED1_MAPPING,
1765 LAN3_LED_MAPPING_MASK,
1766 LAN3_PHY1_LED_MAP
1767 },
1768 .regmap_size = 2,
1769 }, {
1770 .name = "gpio46",
1771 .regmap[0] = {
1772 AIROHA_FUNC_MUX,
1773 REG_GPIO_2ND_I2C_MODE,
1774 GPIO_LAN3_LED0_MODE_MASK,
1775 GPIO_LAN3_LED0_MODE_MASK
1776 },
1777 .regmap[1] = {
1778 AIROHA_FUNC_MUX,
1779 REG_LAN_LED1_MAPPING,
1780 LAN4_LED_MAPPING_MASK,
1781 LAN4_PHY1_LED_MAP
1782 },
1783 .regmap_size = 2,
1784 },
1785 };
1786
1787 static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
1788 {
1789 .name = "gpio43",
1790 .regmap[0] = {
1791 AIROHA_FUNC_MUX,
1792 REG_GPIO_2ND_I2C_MODE,
1793 GPIO_LAN0_LED1_MODE_MASK,
1794 GPIO_LAN0_LED1_MODE_MASK
1795 },
1796 .regmap[1] = {
1797 AIROHA_FUNC_MUX,
1798 REG_LAN_LED1_MAPPING,
1799 LAN1_LED_MAPPING_MASK,
1800 LAN1_PHY2_LED_MAP
1801 },
1802 .regmap_size = 2,
1803 }, {
1804 .name = "gpio44",
1805 .regmap[0] = {
1806 AIROHA_FUNC_MUX,
1807 REG_GPIO_2ND_I2C_MODE,
1808 GPIO_LAN1_LED1_MODE_MASK,
1809 GPIO_LAN1_LED1_MODE_MASK
1810 },
1811 .regmap[1] = {
1812 AIROHA_FUNC_MUX,
1813 REG_LAN_LED1_MAPPING,
1814 LAN2_LED_MAPPING_MASK,
1815 LAN2_PHY2_LED_MAP
1816 },
1817 .regmap_size = 2,
1818 }, {
1819 .name = "gpio45",
1820 .regmap[0] = {
1821 AIROHA_FUNC_MUX,
1822 REG_GPIO_2ND_I2C_MODE,
1823 GPIO_LAN2_LED1_MODE_MASK,
1824 GPIO_LAN2_LED1_MODE_MASK
1825 },
1826 .regmap[1] = {
1827 AIROHA_FUNC_MUX,
1828 REG_LAN_LED1_MAPPING,
1829 LAN3_LED_MAPPING_MASK,
1830 LAN3_PHY2_LED_MAP
1831 },
1832 .regmap_size = 2,
1833 }, {
1834 .name = "gpio46",
1835 .regmap[0] = {
1836 AIROHA_FUNC_MUX,
1837 REG_GPIO_2ND_I2C_MODE,
1838 GPIO_LAN3_LED0_MODE_MASK,
1839 GPIO_LAN3_LED0_MODE_MASK
1840 },
1841 .regmap[1] = {
1842 AIROHA_FUNC_MUX,
1843 REG_LAN_LED1_MAPPING,
1844 LAN4_LED_MAPPING_MASK,
1845 LAN4_PHY2_LED_MAP
1846 },
1847 .regmap_size = 2,
1848 },
1849 };
1850
1851 static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
1852 {
1853 .name = "gpio43",
1854 .regmap[0] = {
1855 AIROHA_FUNC_MUX,
1856 REG_GPIO_2ND_I2C_MODE,
1857 GPIO_LAN0_LED1_MODE_MASK,
1858 GPIO_LAN0_LED1_MODE_MASK
1859 },
1860 .regmap[1] = {
1861 AIROHA_FUNC_MUX,
1862 REG_LAN_LED1_MAPPING,
1863 LAN1_LED_MAPPING_MASK,
1864 LAN1_PHY3_LED_MAP
1865 },
1866 .regmap_size = 2,
1867 }, {
1868 .name = "gpio44",
1869 .regmap[0] = {
1870 AIROHA_FUNC_MUX,
1871 REG_GPIO_2ND_I2C_MODE,
1872 GPIO_LAN1_LED1_MODE_MASK,
1873 GPIO_LAN1_LED1_MODE_MASK
1874 },
1875 .regmap[1] = {
1876 AIROHA_FUNC_MUX,
1877 REG_LAN_LED1_MAPPING,
1878 LAN2_LED_MAPPING_MASK,
1879 LAN2_PHY3_LED_MAP
1880 },
1881 .regmap_size = 2,
1882 }, {
1883 .name = "gpio45",
1884 .regmap[0] = {
1885 AIROHA_FUNC_MUX,
1886 REG_GPIO_2ND_I2C_MODE,
1887 GPIO_LAN2_LED1_MODE_MASK,
1888 GPIO_LAN2_LED1_MODE_MASK
1889 },
1890 .regmap[1] = {
1891 AIROHA_FUNC_MUX,
1892 REG_LAN_LED1_MAPPING,
1893 LAN3_LED_MAPPING_MASK,
1894 LAN3_PHY3_LED_MAP
1895 },
1896 .regmap_size = 2,
1897 }, {
1898 .name = "gpio46",
1899 .regmap[0] = {
1900 AIROHA_FUNC_MUX,
1901 REG_GPIO_2ND_I2C_MODE,
1902 GPIO_LAN3_LED0_MODE_MASK,
1903 GPIO_LAN3_LED0_MODE_MASK
1904 },
1905 .regmap[1] = {
1906 AIROHA_FUNC_MUX,
1907 REG_LAN_LED1_MAPPING,
1908 LAN4_LED_MAPPING_MASK,
1909 LAN4_PHY3_LED_MAP
1910 },
1911 .regmap_size = 2,
1912 },
1913 };
1914
1915 static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
1916 {
1917 .name = "gpio43",
1918 .regmap[0] = {
1919 AIROHA_FUNC_MUX,
1920 REG_GPIO_2ND_I2C_MODE,
1921 GPIO_LAN0_LED1_MODE_MASK,
1922 GPIO_LAN0_LED1_MODE_MASK
1923 },
1924 .regmap[1] = {
1925 AIROHA_FUNC_MUX,
1926 REG_LAN_LED1_MAPPING,
1927 LAN1_LED_MAPPING_MASK,
1928 LAN1_PHY4_LED_MAP
1929 },
1930 .regmap_size = 2,
1931 }, {
1932 .name = "gpio44",
1933 .regmap[0] = {
1934 AIROHA_FUNC_MUX,
1935 REG_GPIO_2ND_I2C_MODE,
1936 GPIO_LAN1_LED1_MODE_MASK,
1937 GPIO_LAN1_LED1_MODE_MASK
1938 },
1939 .regmap[1] = {
1940 AIROHA_FUNC_MUX,
1941 REG_LAN_LED1_MAPPING,
1942 LAN2_LED_MAPPING_MASK,
1943 LAN2_PHY4_LED_MAP
1944 },
1945 .regmap_size = 2,
1946 }, {
1947 .name = "gpio45",
1948 .regmap[0] = {
1949 AIROHA_FUNC_MUX,
1950 REG_GPIO_2ND_I2C_MODE,
1951 GPIO_LAN2_LED1_MODE_MASK,
1952 GPIO_LAN2_LED1_MODE_MASK
1953 },
1954 .regmap[1] = {
1955 AIROHA_FUNC_MUX,
1956 REG_LAN_LED1_MAPPING,
1957 LAN3_LED_MAPPING_MASK,
1958 LAN3_PHY4_LED_MAP
1959 },
1960 .regmap_size = 2,
1961 }, {
1962 .name = "gpio46",
1963 .regmap[0] = {
1964 AIROHA_FUNC_MUX,
1965 REG_GPIO_2ND_I2C_MODE,
1966 GPIO_LAN3_LED0_MODE_MASK,
1967 GPIO_LAN3_LED0_MODE_MASK
1968 },
1969 .regmap[1] = {
1970 AIROHA_FUNC_MUX,
1971 REG_LAN_LED1_MAPPING,
1972 LAN4_LED_MAPPING_MASK,
1973 LAN4_PHY4_LED_MAP
1974 },
1975 .regmap_size = 2,
1976 },
1977 };
1978
1979 static const struct airoha_pinctrl_func airoha_pinctrl_funcs[] = {
1980 PINCTRL_FUNC_DESC(pon),
1981 PINCTRL_FUNC_DESC(tod_1pps),
1982 PINCTRL_FUNC_DESC(sipo),
1983 PINCTRL_FUNC_DESC(mdio),
1984 PINCTRL_FUNC_DESC(uart),
1985 PINCTRL_FUNC_DESC(i2c),
1986 PINCTRL_FUNC_DESC(jtag),
1987 PINCTRL_FUNC_DESC(pcm),
1988 PINCTRL_FUNC_DESC(spi),
1989 PINCTRL_FUNC_DESC(pcm_spi),
1990 PINCTRL_FUNC_DESC(i2s),
1991 PINCTRL_FUNC_DESC(emmc),
1992 PINCTRL_FUNC_DESC(pnand),
1993 PINCTRL_FUNC_DESC(pcie_reset),
1994 PINCTRL_FUNC_DESC(pwm),
1995 PINCTRL_FUNC_DESC(phy1_led0),
1996 PINCTRL_FUNC_DESC(phy2_led0),
1997 PINCTRL_FUNC_DESC(phy3_led0),
1998 PINCTRL_FUNC_DESC(phy4_led0),
1999 PINCTRL_FUNC_DESC(phy1_led1),
2000 PINCTRL_FUNC_DESC(phy2_led1),
2001 PINCTRL_FUNC_DESC(phy3_led1),
2002 PINCTRL_FUNC_DESC(phy4_led1),
2003 };
2004
2005 static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = {
2006 PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
2007 PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
2008 PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
2009 PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
2010 PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
2011 PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
2012 PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
2013 PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
2014 PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
2015 PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
2016 PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
2017 PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
2018 PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
2019 PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
2020 PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
2021 PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
2022 PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
2023 PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
2024 PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
2025 PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
2026 PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
2027 PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
2028 PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
2029 PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
2030 PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
2031 PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
2032 PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
2033 PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(18)),
2034 PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
2035 PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
2036 PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
2037 PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
2038 PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
2039 PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
2040 PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
2041 PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
2042 PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
2043 PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
2044 PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
2045 PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
2046 PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
2047 PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
2048 PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
2049 PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
2050 PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
2051 PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
2052 PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
2053 PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
2054 PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
2055 PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
2056 PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
2057 PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
2058 PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
2059 PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
2060 PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
2061 PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
2062 PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
2063 PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
2064 };
2065
2066 static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = {
2067 PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
2068 PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
2069 PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
2070 PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
2071 PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
2072 PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
2073 PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
2074 PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
2075 PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
2076 PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
2077 PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
2078 PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
2079 PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
2080 PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
2081 PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
2082 PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
2083 PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
2084 PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
2085 PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
2086 PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
2087 PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
2088 PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
2089 PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
2090 PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
2091 PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
2092 PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
2093 PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
2094 PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(18)),
2095 PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
2096 PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
2097 PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
2098 PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
2099 PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
2100 PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
2101 PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
2102 PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
2103 PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
2104 PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
2105 PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
2106 PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
2107 PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
2108 PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
2109 PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
2110 PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
2111 PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
2112 PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
2113 PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
2114 PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
2115 PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
2116 PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
2117 PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
2118 PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
2119 PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
2120 PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
2121 PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
2122 PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
2123 PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
2124 PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
2125 };
2126
2127 static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = {
2128 PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
2129 PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
2130 PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
2131 PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
2132 PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
2133 PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
2134 PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
2135 PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
2136 PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
2137 PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
2138 PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
2139 PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
2140 PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
2141 PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
2142 PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
2143 PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
2144 PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
2145 PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
2146 PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
2147 PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
2148 PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
2149 PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
2150 PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
2151 PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
2152 PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
2153 PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
2154 PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
2155 PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(18)),
2156 PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
2157 PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
2158 PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
2159 PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
2160 PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
2161 PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
2162 PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
2163 PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
2164 PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
2165 PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
2166 PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
2167 PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
2168 PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
2169 PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
2170 PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
2171 PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
2172 PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
2173 PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
2174 PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
2175 PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
2176 PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
2177 PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
2178 PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
2179 PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
2180 PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
2181 PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
2182 PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
2183 PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
2184 PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
2185 PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
2186 };
2187
2188 static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = {
2189 PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
2190 PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
2191 PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
2192 PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
2193 PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
2194 PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
2195 PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
2196 PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
2197 PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
2198 PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
2199 PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
2200 PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
2201 PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
2202 PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
2203 PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
2204 PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
2205 PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
2206 PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
2207 PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
2208 PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
2209 PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
2210 PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
2211 PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
2212 PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
2213 PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
2214 PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
2215 PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
2216 PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(18)),
2217 PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
2218 PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
2219 PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
2220 PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
2221 PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
2222 PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
2223 PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
2224 PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
2225 PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
2226 PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
2227 PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
2228 PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
2229 PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
2230 PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
2231 PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
2232 PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
2233 PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
2234 PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
2235 PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
2236 PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
2237 PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
2238 PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
2239 PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
2240 PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
2241 PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
2242 PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
2243 PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
2244 PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
2245 PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
2246 PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
2247 };
2248
2249 static const struct airoha_pinctrl_conf airoha_pinctrl_pcie_rst_od_conf[] = {
2250 PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
2251 PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
2252 PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
2253 };
2254
2255 static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
2256 struct pinctrl_gpio_range *range,
2257 int pin)
2258 {
2259 if (!range)
2260 range = pinctrl_find_gpio_range_from_pin_nolock(pctrl_dev,
2261 pin);
2262 if (!range)
2263 return -EINVAL;
2264
2265 return pin - range->pin_base;
2266 }
2267
2268 /* gpio callbacks */
2269 static void airoha_gpio_set(struct gpio_chip *chip, unsigned int gpio,
2270 int value)
2271 {
2272 struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);
2273 u32 offset = gpio % AIROHA_PIN_BANK_SIZE;
2274 u8 index = gpio / AIROHA_PIN_BANK_SIZE;
2275
2276 regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.data[index],
2277 BIT(offset), value ? BIT(offset) : 0);
2278 }
2279
2280 static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio)
2281 {
2282 struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);
2283 u32 val, pin = gpio % AIROHA_PIN_BANK_SIZE;
2284 u8 index = gpio / AIROHA_PIN_BANK_SIZE;
2285 int err;
2286
2287 err = regmap_read(pinctrl->regmap,
2288 pinctrl->gpiochip.data[index], &val);
2289
2290 return err ? err : !!(val & BIT(pin));
2291 }
2292
2293 static int airoha_gpio_direction_output(struct gpio_chip *chip,
2294 unsigned int gpio, int value)
2295 {
2296 int err;
2297
2298 err = pinctrl_gpio_direction_output(chip, gpio);
2299 if (err)
2300 return err;
2301
2302 airoha_gpio_set(chip, gpio, value);
2303
2304 return 0;
2305 }
2306
2307 /* irq callbacks */
2308 static void airoha_irq_unmask(struct irq_data *data)
2309 {
2310 u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;
2311 u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
2312 u32 mask = GENMASK(2 * offset + 1, 2 * offset);
2313 struct airoha_pinctrl_gpiochip *gpiochip;
2314 struct airoha_pinctrl *pinctrl;
2315 u32 val = BIT(2 * offset);
2316
2317 gpiochip = irq_data_get_irq_chip_data(data);
2318 if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)))
2319 return;
2320
2321 pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);
2322 switch (gpiochip->irq_type[data->hwirq]) {
2323 case IRQ_TYPE_LEVEL_LOW:
2324 val = val << 1;
2325 fallthrough;
2326 case IRQ_TYPE_LEVEL_HIGH:
2327 regmap_update_bits(pinctrl->regmap, gpiochip->level[index],
2328 mask, val);
2329 break;
2330 case IRQ_TYPE_EDGE_FALLING:
2331 val = val << 1;
2332 fallthrough;
2333 case IRQ_TYPE_EDGE_RISING:
2334 regmap_update_bits(pinctrl->regmap, gpiochip->edge[index],
2335 mask, val);
2336 break;
2337 case IRQ_TYPE_EDGE_BOTH:
2338 regmap_set_bits(pinctrl->regmap, gpiochip->edge[index], mask);
2339 break;
2340 default:
2341 break;
2342 }
2343 }
2344
2345 static void airoha_irq_mask(struct irq_data *data)
2346 {
2347 u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;
2348 u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
2349 u32 mask = GENMASK(2 * offset + 1, 2 * offset);
2350 struct airoha_pinctrl_gpiochip *gpiochip;
2351 struct airoha_pinctrl *pinctrl;
2352
2353 gpiochip = irq_data_get_irq_chip_data(data);
2354 pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);
2355
2356 regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
2357 regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
2358 }
2359
2360 static int airoha_irq_type(struct irq_data *data, unsigned int type)
2361 {
2362 struct airoha_pinctrl_gpiochip *gpiochip;
2363
2364 gpiochip = irq_data_get_irq_chip_data(data);
2365 if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
2366 return -EINVAL;
2367
2368 if (type == IRQ_TYPE_PROBE) {
2369 if (gpiochip->irq_type[data->hwirq])
2370 return 0;
2371
2372 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
2373 }
2374 gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK;
2375
2376 return 0;
2377 }
2378
2379 static irqreturn_t airoha_irq_handler(int irq, void *data)
2380 {
2381 struct airoha_pinctrl *pinctrl = data;
2382 bool handled = false;
2383 int i;
2384
2385 for (i = 0; i < ARRAY_SIZE(irq_status_regs); i++) {
2386 struct gpio_irq_chip *girq = &pinctrl->gpiochip.chip.irq;
2387 u32 regmap;
2388 unsigned long status;
2389 int irq;
2390
2391 if (regmap_read(pinctrl->regmap, pinctrl->gpiochip.status[i],
2392 &regmap))
2393 continue;
2394
2395 status = regmap;
2396 for_each_set_bit(irq, &status, AIROHA_PIN_BANK_SIZE) {
2397 u32 offset = irq + i * AIROHA_PIN_BANK_SIZE;
2398
2399 generic_handle_irq(irq_find_mapping(girq->domain,
2400 offset));
2401 regmap_write(pinctrl->regmap,
2402 pinctrl->gpiochip.status[i], BIT(irq));
2403 }
2404 handled |= !!status;
2405 }
2406
2407 return handled ? IRQ_HANDLED : IRQ_NONE;
2408 }
2409
2410 static const struct irq_chip airoha_gpio_irq_chip = {
2411 .name = "airoha-gpio-irq",
2412 .irq_unmask = airoha_irq_unmask,
2413 .irq_mask = airoha_irq_mask,
2414 .irq_mask_ack = airoha_irq_mask,
2415 .irq_set_type = airoha_irq_type,
2416 .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
2417 };
2418
2419 static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
2420 struct platform_device *pdev)
2421 {
2422 struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
2423 struct gpio_chip *gc = &chip->chip;
2424 struct gpio_irq_chip *girq = &gc->irq;
2425 struct device *dev = &pdev->dev;
2426 int irq, err;
2427
2428 chip->data = gpio_data_regs;
2429 chip->dir = gpio_dir_regs;
2430 chip->out = gpio_out_regs;
2431 chip->status = irq_status_regs;
2432 chip->level = irq_level_regs;
2433 chip->edge = irq_edge_regs;
2434
2435 gc->parent = dev;
2436 gc->label = dev_name(dev);
2437 gc->request = gpiochip_generic_request;
2438 gc->free = gpiochip_generic_free;
2439 gc->direction_input = pinctrl_gpio_direction_input;
2440 gc->direction_output = airoha_gpio_direction_output;
2441 gc->set = airoha_gpio_set;
2442 gc->get = airoha_gpio_get;
2443 gc->base = -1;
2444 gc->ngpio = AIROHA_NUM_PINS;
2445
2446 girq->default_type = IRQ_TYPE_NONE;
2447 girq->handler = handle_simple_irq;
2448 gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
2449
2450 irq = platform_get_irq(pdev, 0);
2451 if (irq < 0)
2452 return irq;
2453
2454 err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED,
2455 dev_name(dev), pinctrl);
2456 if (err) {
2457 dev_err(dev, "error requesting irq %d: %d\n", irq, err);
2458 return err;
2459 }
2460
2461 return devm_gpiochip_add_data(dev, gc, pinctrl);
2462 }
2463
2464 /* pinmux callbacks */
2465 static int airoha_pinmux_set_mux(struct pinctrl_dev *pctrl_dev,
2466 unsigned int selector,
2467 unsigned int group)
2468 {
2469 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
2470 const struct airoha_pinctrl_func *func;
2471 struct function_desc *desc;
2472 struct group_desc *grp;
2473 int i;
2474
2475 desc = pinmux_generic_get_function(pctrl_dev, selector);
2476 if (!desc)
2477 return -EINVAL;
2478
2479 grp = pinctrl_generic_get_group(pctrl_dev, group);
2480 if (!grp)
2481 return -EINVAL;
2482
2483 dev_dbg(pctrl_dev->dev, "enable function %s group %s\n",
2484 desc->func.name, grp->grp.name);
2485
2486 func = desc->data;
2487 for (i = 0; i < func->group_size; i++) {
2488 const struct airoha_pinctrl_func_group *group;
2489 int j;
2490
2491 group = &func->groups[i];
2492 if (strcmp(group->name, grp->grp.name))
2493 continue;
2494
2495 for (j = 0; j < group->regmap_size; j++) {
2496 switch (group->regmap[j].mux) {
2497 case AIROHA_FUNC_PWM_EXT_MUX:
2498 case AIROHA_FUNC_PWM_MUX:
2499 regmap_update_bits(pinctrl->regmap,
2500 group->regmap[j].offset,
2501 group->regmap[j].mask,
2502 group->regmap[j].val);
2503 break;
2504 default:
2505 regmap_update_bits(pinctrl->chip_scu,
2506 group->regmap[j].offset,
2507 group->regmap[j].mask,
2508 group->regmap[j].val);
2509 break;
2510 }
2511 }
2512 return 0;
2513 }
2514
2515 return -EINVAL;
2516 }
2517
2518 static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev,
2519 struct pinctrl_gpio_range *range,
2520 unsigned int p, bool input)
2521 {
2522 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
2523 u32 mask, index;
2524 int err, pin;
2525
2526 pin = airoha_convert_pin_to_reg_offset(pctrl_dev, range, p);
2527 if (pin < 0)
2528 return pin;
2529
2530 /* set output enable */
2531 mask = BIT(pin % AIROHA_PIN_BANK_SIZE);
2532 index = pin / AIROHA_PIN_BANK_SIZE;
2533 err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index],
2534 mask, !input ? mask : 0);
2535 if (err)
2536 return err;
2537
2538 /* set direction */
2539 mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
2540 index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
2541 return regmap_update_bits(pinctrl->regmap,
2542 pinctrl->gpiochip.dir[index], mask,
2543 !input ? mask : 0);
2544 }
2545
2546 static const struct pinmux_ops airoha_pmxops = {
2547 .get_functions_count = pinmux_generic_get_function_count,
2548 .get_function_name = pinmux_generic_get_function_name,
2549 .get_function_groups = pinmux_generic_get_function_groups,
2550 .gpio_set_direction = airoha_pinmux_set_direction,
2551 .set_mux = airoha_pinmux_set_mux,
2552 .strict = true,
2553 };
2554
2555 /* pinconf callbacks */
2556 static const struct airoha_pinctrl_reg *
2557 airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf,
2558 int conf_size, int pin)
2559 {
2560 int i;
2561
2562 for (i = 0; i < conf_size; i++) {
2563 if (conf[i].pin == pin)
2564 return &conf[i].reg;
2565 }
2566
2567 return NULL;
2568 }
2569
2570 static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
2571 const struct airoha_pinctrl_conf *conf,
2572 int conf_size, int pin, u32 *val)
2573 {
2574 const struct airoha_pinctrl_reg *reg;
2575
2576 reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
2577 if (!reg)
2578 return -EINVAL;
2579
2580 if (regmap_read(pinctrl->chip_scu, reg->offset, val))
2581 return -EINVAL;
2582
2583 *val = (*val & reg->mask) >> __ffs(reg->mask);
2584
2585 return 0;
2586 }
2587
2588 static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
2589 const struct airoha_pinctrl_conf *conf,
2590 int conf_size, int pin, u32 val)
2591 {
2592 const struct airoha_pinctrl_reg *reg = NULL;
2593
2594 reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
2595 if (!reg)
2596 return -EINVAL;
2597
2598
2599 if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask,
2600 val << __ffs(reg->mask)))
2601 return -EINVAL;
2602
2603 return 0;
2604 }
2605
2606 #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \
2607 airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pullup_conf, \
2608 ARRAY_SIZE(airoha_pinctrl_pullup_conf), \
2609 (pin), (val))
2610 #define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \
2611 airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pulldown_conf, \
2612 ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \
2613 (pin), (val))
2614 #define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \
2615 airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \
2616 ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \
2617 (pin), (val))
2618 #define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \
2619 airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \
2620 ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \
2621 (pin), (val))
2622 #define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \
2623 airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \
2624 ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \
2625 (pin), (val))
2626 #define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \
2627 airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pullup_conf, \
2628 ARRAY_SIZE(airoha_pinctrl_pullup_conf), \
2629 (pin), (val))
2630 #define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \
2631 airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pulldown_conf, \
2632 ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \
2633 (pin), (val))
2634 #define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \
2635 airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \
2636 ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \
2637 (pin), (val))
2638 #define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \
2639 airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \
2640 ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \
2641 (pin), (val))
2642 #define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \
2643 airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \
2644 ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \
2645 (pin), (val))
2646
2647 static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
2648 {
2649 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
2650 u32 val, mask;
2651 int err, pin;
2652 u8 index;
2653
2654 pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p);
2655 if (pin < 0)
2656 return pin;
2657
2658 index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
2659 err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val);
2660 if (err)
2661 return err;
2662
2663 mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
2664 return val & mask ? PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE;
2665 }
2666
2667 static int airoha_pinconf_get(struct pinctrl_dev *pctrl_dev,
2668 unsigned int pin, unsigned long *config)
2669 {
2670 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
2671 enum pin_config_param param = pinconf_to_config_param(*config);
2672 u32 arg;
2673
2674 switch (param) {
2675 case PIN_CONFIG_BIAS_PULL_DOWN:
2676 case PIN_CONFIG_BIAS_DISABLE:
2677 case PIN_CONFIG_BIAS_PULL_UP: {
2678 u32 pull_up, pull_down;
2679
2680 if (airoha_pinctrl_get_pullup_conf(pinctrl, pin, &pull_up) ||
2681 airoha_pinctrl_get_pulldown_conf(pinctrl, pin, &pull_down))
2682 return -EINVAL;
2683
2684 if (param == PIN_CONFIG_BIAS_PULL_UP &&
2685 !(pull_up && !pull_down))
2686 return -EINVAL;
2687 else if (param == PIN_CONFIG_BIAS_PULL_DOWN &&
2688 !(pull_down && !pull_up))
2689 return -EINVAL;
2690 else if (pull_up || pull_down)
2691 return -EINVAL;
2692
2693 arg = 1;
2694 break;
2695 }
2696 case PIN_CONFIG_DRIVE_STRENGTH: {
2697 u32 e2, e4;
2698
2699 if (airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, &e2) ||
2700 airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, &e4))
2701 return -EINVAL;
2702
2703 arg = e4 << 1 | e2;
2704 break;
2705 }
2706 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
2707 if (airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, &arg))
2708 return -EINVAL;
2709 break;
2710 case PIN_CONFIG_OUTPUT_ENABLE:
2711 case PIN_CONFIG_INPUT_ENABLE:
2712 arg = airoha_pinconf_get_direction(pctrl_dev, pin);
2713 if (arg != param)
2714 return -EINVAL;
2715
2716 arg = 1;
2717 break;
2718 default:
2719 return -EOPNOTSUPP;
2720 }
2721
2722 *config = pinconf_to_config_packed(param, arg);
2723
2724 return 0;
2725 }
2726
2727 static int airoha_pinconf_set_pin_value(struct pinctrl_dev *pctrl_dev,
2728 unsigned int p, bool value)
2729 {
2730 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
2731 int pin;
2732
2733 pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p);
2734 if (pin < 0)
2735 return pin;
2736
2737 airoha_gpio_set(&pinctrl->gpiochip.chip, pin, value);
2738
2739 return 0;
2740 }
2741
2742 static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev,
2743 unsigned int pin, unsigned long *configs,
2744 unsigned int num_configs)
2745 {
2746 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
2747 int i;
2748
2749 for (i = 0; i < num_configs; i++) {
2750 u32 param = pinconf_to_config_param(configs[i]);
2751 u32 arg = pinconf_to_config_argument(configs[i]);
2752
2753 switch (param) {
2754 case PIN_CONFIG_BIAS_DISABLE:
2755 airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0);
2756 airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0);
2757 break;
2758 case PIN_CONFIG_BIAS_PULL_UP:
2759 airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0);
2760 airoha_pinctrl_set_pullup_conf(pinctrl, pin, 1);
2761 break;
2762 case PIN_CONFIG_BIAS_PULL_DOWN:
2763 airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 1);
2764 airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0);
2765 break;
2766 case PIN_CONFIG_DRIVE_STRENGTH: {
2767 u32 e2 = 0, e4 = 0;
2768
2769 switch (arg) {
2770 case MTK_DRIVE_2mA:
2771 break;
2772 case MTK_DRIVE_4mA:
2773 e2 = 1;
2774 break;
2775 case MTK_DRIVE_6mA:
2776 e4 = 1;
2777 break;
2778 case MTK_DRIVE_8mA:
2779 e2 = 1;
2780 e4 = 1;
2781 break;
2782 default:
2783 return -EINVAL;
2784 }
2785
2786 airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, e2);
2787 airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, e4);
2788 break;
2789 }
2790 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
2791 airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, !!arg);
2792 break;
2793 case PIN_CONFIG_OUTPUT_ENABLE:
2794 case PIN_CONFIG_INPUT_ENABLE:
2795 case PIN_CONFIG_OUTPUT: {
2796 bool input = param == PIN_CONFIG_INPUT_ENABLE;
2797 int err;
2798
2799 err = airoha_pinmux_set_direction(pctrl_dev, NULL, pin,
2800 input);
2801 if (err)
2802 return err;
2803
2804 if (param == PIN_CONFIG_OUTPUT) {
2805 err = airoha_pinconf_set_pin_value(pctrl_dev,
2806 pin, !!arg);
2807 if (err)
2808 return err;
2809 }
2810 break;
2811 }
2812 default:
2813 return -EOPNOTSUPP;
2814 }
2815 }
2816
2817 return 0;
2818 }
2819
2820 static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev,
2821 unsigned int group, unsigned long *config)
2822 {
2823 u32 cur_config = 0;
2824 int i;
2825
2826 for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
2827 if (airoha_pinconf_get(pctrl_dev,
2828 airoha_pinctrl_groups[group].pins[i],
2829 config))
2830 return -EOPNOTSUPP;
2831
2832 if (i && cur_config != *config)
2833 return -EOPNOTSUPP;
2834
2835 cur_config = *config;
2836 }
2837
2838 return 0;
2839 }
2840
2841 static int airoha_pinconf_group_set(struct pinctrl_dev *pctrl_dev,
2842 unsigned int group, unsigned long *configs,
2843 unsigned int num_configs)
2844 {
2845 int i;
2846
2847 for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
2848 int err;
2849
2850 err = airoha_pinconf_set(pctrl_dev,
2851 airoha_pinctrl_groups[group].pins[i],
2852 configs, num_configs);
2853 if (err)
2854 return err;
2855 }
2856
2857 return 0;
2858 }
2859
2860 static const struct pinconf_ops airoha_confops = {
2861 .is_generic = true,
2862 .pin_config_get = airoha_pinconf_get,
2863 .pin_config_set = airoha_pinconf_set,
2864 .pin_config_group_get = airoha_pinconf_group_get,
2865 .pin_config_group_set = airoha_pinconf_group_set,
2866 .pin_config_config_dbg_show = pinconf_generic_dump_config,
2867 };
2868
2869 static const struct pinctrl_ops airoha_pctlops = {
2870 .get_groups_count = pinctrl_generic_get_group_count,
2871 .get_group_name = pinctrl_generic_get_group_name,
2872 .get_group_pins = pinctrl_generic_get_group_pins,
2873 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
2874 .dt_free_map = pinconf_generic_dt_free_map,
2875 };
2876
2877 static struct pinctrl_desc airoha_pinctrl_desc = {
2878 .name = KBUILD_MODNAME,
2879 .owner = THIS_MODULE,
2880 .pctlops = &airoha_pctlops,
2881 .pmxops = &airoha_pmxops,
2882 .confops = &airoha_confops,
2883 .pins = airoha_pinctrl_pins,
2884 .npins = ARRAY_SIZE(airoha_pinctrl_pins),
2885 };
2886
2887 static int airoha_pinctrl_probe(struct platform_device *pdev)
2888 {
2889 struct device *dev = &pdev->dev;
2890 struct airoha_pinctrl *pinctrl;
2891 struct regmap *map;
2892 int err, i;
2893
2894 pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
2895 if (!pinctrl)
2896 return -ENOMEM;
2897
2898 pinctrl->regmap = device_node_to_regmap(dev->parent->of_node);
2899 if (IS_ERR(pinctrl->regmap))
2900 return PTR_ERR(pinctrl->regmap);
2901
2902 map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
2903 if (IS_ERR(map))
2904 return PTR_ERR(map);
2905
2906 pinctrl->chip_scu = map;
2907
2908 err = devm_pinctrl_register_and_init(dev, &airoha_pinctrl_desc,
2909 pinctrl, &pinctrl->ctrl);
2910 if (err)
2911 return err;
2912
2913 /* build pin groups */
2914 for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_groups); i++) {
2915 const struct pingroup *grp = &airoha_pinctrl_groups[i];
2916
2917 err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name,
2918 grp->pins, grp->npins,
2919 (void *)grp);
2920 if (err < 0) {
2921 dev_err(&pdev->dev, "Failed to register group %s\n",
2922 grp->name);
2923 return err;
2924 }
2925 }
2926
2927 /* build functions */
2928 for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_funcs); i++) {
2929 const struct airoha_pinctrl_func *func;
2930
2931 func = &airoha_pinctrl_funcs[i];
2932 err = pinmux_generic_add_function(pinctrl->ctrl,
2933 func->desc.func.name,
2934 func->desc.func.groups,
2935 func->desc.func.ngroups,
2936 (void *)func);
2937 if (err < 0) {
2938 dev_err(dev, "Failed to register function %s\n",
2939 func->desc.func.name);
2940 return err;
2941 }
2942 }
2943
2944 err = pinctrl_enable(pinctrl->ctrl);
2945 if (err)
2946 return err;
2947
2948 /* build gpio-chip */
2949 return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
2950 }
2951
2952 static const struct of_device_id airoha_pinctrl_of_match[] = {
2953 { .compatible = "airoha,en7581-pinctrl" },
2954 { /* sentinel */ }
2955 };
2956 MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
2957
2958 static struct platform_driver airoha_pinctrl_driver = {
2959 .probe = airoha_pinctrl_probe,
2960 .driver = {
2961 .name = "pinctrl-airoha",
2962 .of_match_table = airoha_pinctrl_of_match,
2963 },
2964 };
2965 module_platform_driver(airoha_pinctrl_driver);
2966
2967 MODULE_LICENSE("GPL");
2968 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
2969 MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
2970 MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
2971 MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC");
Linux Kernel