2 * Ricoh RS5C313 RTC device/driver
3 * Copyright (C) 2007 Nobuhiro Iwamatsu
5 * 2005-09-19 modified by kogiidena
7 * Based on the old drivers/char/rs5c313_rtc.c by:
8 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
9 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
11 * Based on code written by Paul Gortmaker.
12 * Copyright (C) 1996 Paul Gortmaker
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
18 * Based on other minimal char device drivers, like Alan's
19 * watchdog, Ted's random, etc. etc.
21 * 1.07 Paul Gortmaker.
22 * 1.08 Miquel van Smoorenburg: disallow certain things on the
23 * DEC Alpha as the CMOS clock is also used for other things.
24 * 1.09 Nikita Schmidt: epoch support and some Alpha cleanup.
25 * 1.09a Pete Zaitcev: Sun SPARC
26 * 1.09b Jeff Garzik: Modularize, init cleanup
27 * 1.09c Jeff Garzik: SMP cleanup
28 * 1.10 Paul Barton-Davis: add support for async I/O
29 * 1.10a Andrea Arcangeli: Alpha updates
30 * 1.10b Andrew Morton: SMP lock fix
31 * 1.10c Cesar Barros: SMP locking fixes and cleanup
32 * 1.10d Paul Gortmaker: delete paranoia check in rtc_exit
33 * 1.10e Maciej W. Rozycki: Handle DECstation's year weirdness.
34 * 1.11 Takashi Iwai: Kernel access functions
35 * rtc_register/rtc_unregister/rtc_control
36 * 1.11a Daniele Bellucci: Audit create_proc_read_entry in rtc_init
37 * 1.12 Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer
38 * CONFIG_HPET_EMULATE_RTC
39 * 1.13 Nobuhiro Iwamatsu: Update driver.
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/module.h>
45 #include <linux/err.h>
46 #include <linux/rtc.h>
47 #include <linux/platform_device.h>
48 #include <linux/bcd.h>
49 #include <linux/delay.h>
52 #define DRV_NAME "rs5c313"
54 #ifdef CONFIG_SH_LANDISK
55 /*****************************************************/
56 /* LANDISK dependence part of RS5C313 */
57 /*****************************************************/
59 #define SCSMR1 0xFFE00000
60 #define SCSCR1 0xFFE00008
61 #define SCSMR1_CA 0x80
62 #define SCSCR1_CKE 0x03
63 #define SCSPTR1 0xFFE0001C
64 #define SCSPTR1_EIO 0x80
65 #define SCSPTR1_SPB1IO 0x08
66 #define SCSPTR1_SPB1DT 0x04
67 #define SCSPTR1_SPB0IO 0x02
68 #define SCSPTR1_SPB0DT 0x01
70 #define SDA_OEN SCSPTR1_SPB1IO
71 #define SDA SCSPTR1_SPB1DT
72 #define SCL_OEN SCSPTR1_SPB0IO
73 #define SCL SCSPTR1_SPB0DT
75 /* RICOH RS5C313 CE port */
76 #define RS5C313_CE 0xB0000003
78 /* RICOH RS5C313 CE port bit */
79 #define RS5C313_CE_RTCCE 0x02
82 unsigned char scsptr1_data
;
84 #define RS5C313_CEENABLE __raw_writeb(RS5C313_CE_RTCCE, RS5C313_CE);
85 #define RS5C313_CEDISABLE __raw_writeb(0x00, RS5C313_CE)
86 #define RS5C313_MISCOP __raw_writeb(0x02, 0xB0000008)
88 static void rs5c313_init_port(void)
90 /* Set SCK as I/O port and Initialize SCSPTR1 data & I/O port. */
91 __raw_writeb(__raw_readb(SCSMR1
) & ~SCSMR1_CA
, SCSMR1
);
92 __raw_writeb(__raw_readb(SCSCR1
) & ~SCSCR1_CKE
, SCSCR1
);
94 /* And Initialize SCL for RS5C313 clock */
95 scsptr1_data
= __raw_readb(SCSPTR1
) | SCL
; /* SCL:H */
96 __raw_writeb(scsptr1_data
, SCSPTR1
);
97 scsptr1_data
= __raw_readb(SCSPTR1
) | SCL_OEN
; /* SCL output enable */
98 __raw_writeb(scsptr1_data
, SCSPTR1
);
99 RS5C313_CEDISABLE
; /* CE:L */
102 static void rs5c313_write_data(unsigned char data
)
106 for (i
= 0; i
< 8; i
++) {
108 scsptr1_data
= (scsptr1_data
& ~SDA
) |
109 ((((0x80 >> i
) & data
) >> (7 - i
)) << 2);
110 __raw_writeb(scsptr1_data
, SCSPTR1
);
112 scsptr1_data
|= SDA_OEN
; /* SDA:output enable */
113 __raw_writeb(scsptr1_data
, SCSPTR1
);
116 scsptr1_data
&= ~SCL
; /* SCL:L */
117 __raw_writeb(scsptr1_data
, SCSPTR1
);
119 scsptr1_data
|= SCL
; /* SCL:H */
120 __raw_writeb(scsptr1_data
, SCSPTR1
);
123 scsptr1_data
&= ~SDA_OEN
; /* SDA:output disable */
124 __raw_writeb(scsptr1_data
, SCSPTR1
);
127 static unsigned char rs5c313_read_data(void)
130 unsigned char data
= 0;
132 for (i
= 0; i
< 8; i
++) {
135 data
|= ((__raw_readb(SCSPTR1
) & SDA
) >> 2) << (7 - i
);
136 scsptr1_data
&= ~SCL
; /* SCL:L */
137 __raw_writeb(scsptr1_data
, SCSPTR1
);
139 scsptr1_data
|= SCL
; /* SCL:H */
140 __raw_writeb(scsptr1_data
, SCSPTR1
);
145 #endif /* CONFIG_SH_LANDISK */
147 /*****************************************************/
148 /* machine independence part of RS5C313 */
149 /*****************************************************/
151 /* RICOH RS5C313 address */
152 #define RS5C313_ADDR_SEC 0x00
153 #define RS5C313_ADDR_SEC10 0x01
154 #define RS5C313_ADDR_MIN 0x02
155 #define RS5C313_ADDR_MIN10 0x03
156 #define RS5C313_ADDR_HOUR 0x04
157 #define RS5C313_ADDR_HOUR10 0x05
158 #define RS5C313_ADDR_WEEK 0x06
159 #define RS5C313_ADDR_INTINTVREG 0x07
160 #define RS5C313_ADDR_DAY 0x08
161 #define RS5C313_ADDR_DAY10 0x09
162 #define RS5C313_ADDR_MON 0x0A
163 #define RS5C313_ADDR_MON10 0x0B
164 #define RS5C313_ADDR_YEAR 0x0C
165 #define RS5C313_ADDR_YEAR10 0x0D
166 #define RS5C313_ADDR_CNTREG 0x0E
167 #define RS5C313_ADDR_TESTREG 0x0F
169 /* RICOH RS5C313 control register */
170 #define RS5C313_CNTREG_ADJ_BSY 0x01
171 #define RS5C313_CNTREG_WTEN_XSTP 0x02
172 #define RS5C313_CNTREG_12_24 0x04
173 #define RS5C313_CNTREG_CTFG 0x08
175 /* RICOH RS5C313 test register */
176 #define RS5C313_TESTREG_TEST 0x01
178 /* RICOH RS5C313 control bit */
179 #define RS5C313_CNTBIT_READ 0x40
180 #define RS5C313_CNTBIT_AD 0x20
181 #define RS5C313_CNTBIT_DT 0x10
183 static unsigned char rs5c313_read_reg(unsigned char addr
)
186 rs5c313_write_data(addr
| RS5C313_CNTBIT_READ
| RS5C313_CNTBIT_AD
);
187 return rs5c313_read_data();
190 static void rs5c313_write_reg(unsigned char addr
, unsigned char data
)
193 rs5c313_write_data(addr
| RS5C313_CNTBIT_AD
);
194 rs5c313_write_data(data
| RS5C313_CNTBIT_DT
);
198 static inline unsigned char rs5c313_read_cntreg(void)
200 return rs5c313_read_reg(RS5C313_ADDR_CNTREG
);
203 static inline void rs5c313_write_cntreg(unsigned char data
)
205 rs5c313_write_reg(RS5C313_ADDR_CNTREG
, data
);
208 static inline void rs5c313_write_intintvreg(unsigned char data
)
210 rs5c313_write_reg(RS5C313_ADDR_INTINTVREG
, data
);
213 static int rs5c313_rtc_read_time(struct device
*dev
, struct rtc_time
*tm
)
220 RS5C313_CEENABLE
; /* CE:H */
222 /* Initialize control reg. 24 hour */
223 rs5c313_write_cntreg(0x04);
225 if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY
))
229 ndelay(700); /* CE:L */
232 dev_err(dev
, "%s: timeout error\n", __func__
);
237 data
= rs5c313_read_reg(RS5C313_ADDR_SEC
);
238 data
|= (rs5c313_read_reg(RS5C313_ADDR_SEC10
) << 4);
239 tm
->tm_sec
= bcd2bin(data
);
241 data
= rs5c313_read_reg(RS5C313_ADDR_MIN
);
242 data
|= (rs5c313_read_reg(RS5C313_ADDR_MIN10
) << 4);
243 tm
->tm_min
= bcd2bin(data
);
245 data
= rs5c313_read_reg(RS5C313_ADDR_HOUR
);
246 data
|= (rs5c313_read_reg(RS5C313_ADDR_HOUR10
) << 4);
247 tm
->tm_hour
= bcd2bin(data
);
249 data
= rs5c313_read_reg(RS5C313_ADDR_DAY
);
250 data
|= (rs5c313_read_reg(RS5C313_ADDR_DAY10
) << 4);
251 tm
->tm_mday
= bcd2bin(data
);
253 data
= rs5c313_read_reg(RS5C313_ADDR_MON
);
254 data
|= (rs5c313_read_reg(RS5C313_ADDR_MON10
) << 4);
255 tm
->tm_mon
= bcd2bin(data
) - 1;
257 data
= rs5c313_read_reg(RS5C313_ADDR_YEAR
);
258 data
|= (rs5c313_read_reg(RS5C313_ADDR_YEAR10
) << 4);
259 tm
->tm_year
= bcd2bin(data
);
261 if (tm
->tm_year
< 70)
264 data
= rs5c313_read_reg(RS5C313_ADDR_WEEK
);
265 tm
->tm_wday
= bcd2bin(data
);
268 ndelay(700); /* CE:L */
273 static int rs5c313_rtc_set_time(struct device
*dev
, struct rtc_time
*tm
)
281 RS5C313_CEENABLE
; /* CE:H */
283 /* Initialize control reg. 24 hour */
284 rs5c313_write_cntreg(0x04);
286 if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY
))
290 ndelay(700); /* CE:L */
293 dev_err(dev
, "%s: timeout error\n", __func__
);
298 data
= bin2bcd(tm
->tm_sec
);
299 rs5c313_write_reg(RS5C313_ADDR_SEC
, data
);
300 rs5c313_write_reg(RS5C313_ADDR_SEC10
, (data
>> 4));
302 data
= bin2bcd(tm
->tm_min
);
303 rs5c313_write_reg(RS5C313_ADDR_MIN
, data
);
304 rs5c313_write_reg(RS5C313_ADDR_MIN10
, (data
>> 4));
306 data
= bin2bcd(tm
->tm_hour
);
307 rs5c313_write_reg(RS5C313_ADDR_HOUR
, data
);
308 rs5c313_write_reg(RS5C313_ADDR_HOUR10
, (data
>> 4));
310 data
= bin2bcd(tm
->tm_mday
);
311 rs5c313_write_reg(RS5C313_ADDR_DAY
, data
);
312 rs5c313_write_reg(RS5C313_ADDR_DAY10
, (data
>> 4));
314 data
= bin2bcd(tm
->tm_mon
+ 1);
315 rs5c313_write_reg(RS5C313_ADDR_MON
, data
);
316 rs5c313_write_reg(RS5C313_ADDR_MON10
, (data
>> 4));
318 data
= bin2bcd(tm
->tm_year
% 100);
319 rs5c313_write_reg(RS5C313_ADDR_YEAR
, data
);
320 rs5c313_write_reg(RS5C313_ADDR_YEAR10
, (data
>> 4));
322 data
= bin2bcd(tm
->tm_wday
);
323 rs5c313_write_reg(RS5C313_ADDR_WEEK
, data
);
325 RS5C313_CEDISABLE
; /* CE:H */
331 static void rs5c313_check_xstp_bit(void)
336 RS5C313_CEENABLE
; /* CE:H */
337 if (rs5c313_read_cntreg() & RS5C313_CNTREG_WTEN_XSTP
) {
338 /* INT interval reg. OFF */
339 rs5c313_write_intintvreg(0x00);
340 /* Initialize control reg. 24 hour & adjust */
341 rs5c313_write_cntreg(0x07);
344 for (cnt
= 0; cnt
< 100; cnt
++) {
345 if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY
))
350 memset(&tm
, 0, sizeof(struct rtc_time
));
353 tm
.tm_year
= 2000 - 1900;
355 rs5c313_rtc_set_time(NULL
, &tm
);
356 pr_err("invalid value, resetting to 1 Jan 2000\n");
359 ndelay(700); /* CE:L */
362 static const struct rtc_class_ops rs5c313_rtc_ops
= {
363 .read_time
= rs5c313_rtc_read_time
,
364 .set_time
= rs5c313_rtc_set_time
,
367 static int rs5c313_rtc_probe(struct platform_device
*pdev
)
369 struct rtc_device
*rtc
;
372 rs5c313_check_xstp_bit();
374 rtc
= devm_rtc_device_register(&pdev
->dev
, "rs5c313", &rs5c313_rtc_ops
,
377 return PTR_ERR_OR_ZERO(rtc
);
380 static struct platform_driver rs5c313_rtc_platform_driver
= {
384 .probe
= rs5c313_rtc_probe
,
387 module_platform_driver(rs5c313_rtc_platform_driver
);
389 MODULE_AUTHOR("kogiidena , Nobuhiro Iwamatsu <iwamatsu@nigauri.org>");
390 MODULE_DESCRIPTION("Ricoh RS5C313 RTC device driver");
391 MODULE_LICENSE("GPL");
392 MODULE_ALIAS("platform:" DRV_NAME
);