1 // SPDX-License-Identifier: GPL-2.0
4 * The RTC driver for Sunplus SP7021
6 * Copyright (C) 2019 Sunplus Technology Inc., All rights reseerved.
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/err.h>
13 #include <linux/ktime.h>
14 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/reset.h>
18 #include <linux/rtc.h>
20 #define RTC_REG_NAME "rtc"
23 #define TIMER_FREEZE_MASK_BIT BIT(5 + 16)
24 #define TIMER_FREEZE BIT(5)
25 #define DIS_SYS_RST_RTC_MASK_BIT BIT(4 + 16)
26 #define DIS_SYS_RST_RTC BIT(4)
27 #define RTC32K_MODE_RESET_MASK_BIT BIT(3 + 16)
28 #define RTC32K_MODE_RESET BIT(3)
29 #define ALARM_EN_OVERDUE_MASK_BIT BIT(2 + 16)
30 #define ALARM_EN_OVERDUE BIT(2)
31 #define ALARM_EN_PMC_MASK_BIT BIT(1 + 16)
32 #define ALARM_EN_PMC BIT(1)
33 #define ALARM_EN_MASK_BIT BIT(0 + 16)
34 #define ALARM_EN BIT(0)
35 #define RTC_TIMER_OUT 0x44
36 #define RTC_DIVIDER 0x48
37 #define RTC_TIMER_SET 0x4c
38 #define RTC_ALARM_SET 0x50
39 #define RTC_USER_DATA 0x54
40 #define RTC_RESET_RECORD 0x58
41 #define RTC_BATT_CHARGE_CTRL 0x5c
42 #define BAT_CHARGE_RSEL_MASK_BIT GENMASK(3 + 16, 2 + 16)
43 #define BAT_CHARGE_RSEL_MASK GENMASK(3, 2)
44 #define BAT_CHARGE_RSEL_2K_OHM FIELD_PREP(BAT_CHARGE_RSEL_MASK, 0)
45 #define BAT_CHARGE_RSEL_250_OHM FIELD_PREP(BAT_CHARGE_RSEL_MASK, 1)
46 #define BAT_CHARGE_RSEL_50_OHM FIELD_PREP(BAT_CHARGE_RSEL_MASK, 2)
47 #define BAT_CHARGE_RSEL_0_OHM FIELD_PREP(BAT_CHARGE_RSEL_MASK, 3)
48 #define BAT_CHARGE_DSEL_MASK_BIT BIT(1 + 16)
49 #define BAT_CHARGE_DSEL_MASK GENMASK(1, 1)
50 #define BAT_CHARGE_DSEL_ON FIELD_PREP(BAT_CHARGE_DSEL_MASK, 0)
51 #define BAT_CHARGE_DSEL_OFF FIELD_PREP(BAT_CHARGE_DSEL_MASK, 1)
52 #define BAT_CHARGE_EN_MASK_BIT BIT(0 + 16)
53 #define BAT_CHARGE_EN BIT(0)
54 #define RTC_TRIM_CTRL 0x60
57 struct rtc_device
*rtc
;
60 struct reset_control
*rstc
;
61 void __iomem
*reg_base
;
65 static void sp_get_seconds(struct device
*dev
, unsigned long *secs
)
67 struct sunplus_rtc
*sp_rtc
= dev_get_drvdata(dev
);
69 *secs
= (unsigned long)readl(sp_rtc
->reg_base
+ RTC_TIMER_OUT
);
72 static void sp_set_seconds(struct device
*dev
, unsigned long secs
)
74 struct sunplus_rtc
*sp_rtc
= dev_get_drvdata(dev
);
76 writel((u32
)secs
, sp_rtc
->reg_base
+ RTC_TIMER_SET
);
79 static int sp_rtc_read_time(struct device
*dev
, struct rtc_time
*tm
)
83 sp_get_seconds(dev
, &secs
);
84 rtc_time64_to_tm(secs
, tm
);
89 static int sp_rtc_set_time(struct device
*dev
, struct rtc_time
*tm
)
93 secs
= rtc_tm_to_time64(tm
);
94 dev_dbg(dev
, "%s, secs = %lu\n", __func__
, secs
);
95 sp_set_seconds(dev
, secs
);
100 static int sp_rtc_set_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
102 struct sunplus_rtc
*sp_rtc
= dev_get_drvdata(dev
);
103 unsigned long alarm_time
;
105 alarm_time
= rtc_tm_to_time64(&alrm
->time
);
106 dev_dbg(dev
, "%s, alarm_time: %u\n", __func__
, (u32
)(alarm_time
));
107 writel((u32
)alarm_time
, sp_rtc
->reg_base
+ RTC_ALARM_SET
);
112 static int sp_rtc_read_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
114 struct sunplus_rtc
*sp_rtc
= dev_get_drvdata(dev
);
115 unsigned int alarm_time
;
117 alarm_time
= readl(sp_rtc
->reg_base
+ RTC_ALARM_SET
);
118 dev_dbg(dev
, "%s, alarm_time: %u\n", __func__
, alarm_time
);
125 rtc_time64_to_tm((unsigned long)(alarm_time
), &alrm
->time
);
130 static int sp_rtc_alarm_irq_enable(struct device
*dev
, unsigned int enabled
)
132 struct sunplus_rtc
*sp_rtc
= dev_get_drvdata(dev
);
135 writel((TIMER_FREEZE_MASK_BIT
| DIS_SYS_RST_RTC_MASK_BIT
|
136 RTC32K_MODE_RESET_MASK_BIT
| ALARM_EN_OVERDUE_MASK_BIT
|
137 ALARM_EN_PMC_MASK_BIT
| ALARM_EN_MASK_BIT
) |
138 (DIS_SYS_RST_RTC
| ALARM_EN_OVERDUE
| ALARM_EN_PMC
| ALARM_EN
),
139 sp_rtc
->reg_base
+ RTC_CTRL
);
141 writel((ALARM_EN_OVERDUE_MASK_BIT
| ALARM_EN_PMC_MASK_BIT
| ALARM_EN_MASK_BIT
) |
142 0x0, sp_rtc
->reg_base
+ RTC_CTRL
);
147 static const struct rtc_class_ops sp_rtc_ops
= {
148 .read_time
= sp_rtc_read_time
,
149 .set_time
= sp_rtc_set_time
,
150 .set_alarm
= sp_rtc_set_alarm
,
151 .read_alarm
= sp_rtc_read_alarm
,
152 .alarm_irq_enable
= sp_rtc_alarm_irq_enable
,
155 static irqreturn_t
sp_rtc_irq_handler(int irq
, void *dev_id
)
157 struct platform_device
*plat_dev
= dev_id
;
158 struct sunplus_rtc
*sp_rtc
= dev_get_drvdata(&plat_dev
->dev
);
160 rtc_update_irq(sp_rtc
->rtc
, 1, RTC_IRQF
| RTC_AF
);
161 dev_dbg(&plat_dev
->dev
, "[RTC] ALARM INT\n");
167 * -------------------------------------------------------------------------------------
168 * bat_charge_rsel bat_charge_dsel bat_charge_en Remarks
170 * 0 0 1 0.86mA (2K Ohm with diode)
171 * 1 0 1 1.81mA (250 Ohm with diode)
172 * 2 0 1 2.07mA (50 Ohm with diode)
173 * 3 0 1 16.0mA (0 Ohm with diode)
174 * 0 1 1 1.36mA (2K Ohm without diode)
175 * 1 1 1 3.99mA (250 Ohm without diode)
176 * 2 1 1 4.41mA (50 Ohm without diode)
177 * 3 1 1 16.0mA (0 Ohm without diode)
178 * -------------------------------------------------------------------------------------
180 static void sp_rtc_set_trickle_charger(struct device dev
)
182 struct sunplus_rtc
*sp_rtc
= dev_get_drvdata(&dev
);
186 if (of_property_read_u32(dev
.of_node
, "trickle-resistor-ohms", &ohms
) ||
187 of_property_read_u32(dev
.of_node
, "aux-voltage-chargeable", &chargeable
)) {
188 dev_warn(&dev
, "battery charger disabled\n");
194 rsel
= BAT_CHARGE_RSEL_2K_OHM
;
197 rsel
= BAT_CHARGE_RSEL_250_OHM
;
200 rsel
= BAT_CHARGE_RSEL_50_OHM
;
203 rsel
= BAT_CHARGE_RSEL_0_OHM
;
206 dev_err(&dev
, "invalid charger resistor value (%d)\n", ohms
);
210 writel(BAT_CHARGE_RSEL_MASK_BIT
| rsel
, sp_rtc
->reg_base
+ RTC_BATT_CHARGE_CTRL
);
212 switch (chargeable
) {
214 writel(BAT_CHARGE_DSEL_MASK_BIT
| BAT_CHARGE_DSEL_OFF
,
215 sp_rtc
->reg_base
+ RTC_BATT_CHARGE_CTRL
);
218 writel(BAT_CHARGE_DSEL_MASK_BIT
| BAT_CHARGE_DSEL_ON
,
219 sp_rtc
->reg_base
+ RTC_BATT_CHARGE_CTRL
);
222 dev_err(&dev
, "invalid aux-voltage-chargeable value (%d)\n", chargeable
);
226 writel(BAT_CHARGE_EN_MASK_BIT
| BAT_CHARGE_EN
, sp_rtc
->reg_base
+ RTC_BATT_CHARGE_CTRL
);
229 static int sp_rtc_probe(struct platform_device
*plat_dev
)
231 struct sunplus_rtc
*sp_rtc
;
234 sp_rtc
= devm_kzalloc(&plat_dev
->dev
, sizeof(*sp_rtc
), GFP_KERNEL
);
238 sp_rtc
->reg_base
= devm_platform_ioremap_resource_byname(plat_dev
, RTC_REG_NAME
);
239 if (IS_ERR(sp_rtc
->reg_base
))
240 return dev_err_probe(&plat_dev
->dev
, PTR_ERR(sp_rtc
->reg_base
),
241 "%s devm_ioremap_resource fail\n", RTC_REG_NAME
);
242 dev_dbg(&plat_dev
->dev
, "res = %pR, reg_base = %p\n",
243 sp_rtc
->res
, sp_rtc
->reg_base
);
245 sp_rtc
->irq
= platform_get_irq(plat_dev
, 0);
249 ret
= devm_request_irq(&plat_dev
->dev
, sp_rtc
->irq
, sp_rtc_irq_handler
,
250 IRQF_TRIGGER_RISING
, "rtc irq", plat_dev
);
252 return dev_err_probe(&plat_dev
->dev
, ret
, "devm_request_irq failed:\n");
254 sp_rtc
->rtcclk
= devm_clk_get(&plat_dev
->dev
, NULL
);
255 if (IS_ERR(sp_rtc
->rtcclk
))
256 return dev_err_probe(&plat_dev
->dev
, PTR_ERR(sp_rtc
->rtcclk
),
257 "devm_clk_get fail\n");
259 sp_rtc
->rstc
= devm_reset_control_get_exclusive(&plat_dev
->dev
, NULL
);
260 if (IS_ERR(sp_rtc
->rstc
))
261 return dev_err_probe(&plat_dev
->dev
, PTR_ERR(sp_rtc
->rstc
),
262 "failed to retrieve reset controller\n");
264 ret
= clk_prepare_enable(sp_rtc
->rtcclk
);
268 ret
= reset_control_deassert(sp_rtc
->rstc
);
270 goto free_reset_assert
;
272 device_init_wakeup(&plat_dev
->dev
, 1);
273 dev_set_drvdata(&plat_dev
->dev
, sp_rtc
);
275 sp_rtc
->rtc
= devm_rtc_allocate_device(&plat_dev
->dev
);
276 if (IS_ERR(sp_rtc
->rtc
)) {
277 ret
= PTR_ERR(sp_rtc
->rtc
);
278 goto free_reset_assert
;
281 sp_rtc
->rtc
->range_max
= U32_MAX
;
282 sp_rtc
->rtc
->range_min
= 0;
283 sp_rtc
->rtc
->ops
= &sp_rtc_ops
;
285 ret
= devm_rtc_register_device(sp_rtc
->rtc
);
287 goto free_reset_assert
;
289 /* Setup trickle charger */
290 if (plat_dev
->dev
.of_node
)
291 sp_rtc_set_trickle_charger(plat_dev
->dev
);
293 /* Keep RTC from system reset */
294 writel(DIS_SYS_RST_RTC_MASK_BIT
| DIS_SYS_RST_RTC
, sp_rtc
->reg_base
+ RTC_CTRL
);
299 reset_control_assert(sp_rtc
->rstc
);
301 clk_disable_unprepare(sp_rtc
->rtcclk
);
306 static void sp_rtc_remove(struct platform_device
*plat_dev
)
308 struct sunplus_rtc
*sp_rtc
= dev_get_drvdata(&plat_dev
->dev
);
310 device_init_wakeup(&plat_dev
->dev
, 0);
311 reset_control_assert(sp_rtc
->rstc
);
312 clk_disable_unprepare(sp_rtc
->rtcclk
);
315 #ifdef CONFIG_PM_SLEEP
316 static int sp_rtc_suspend(struct device
*dev
)
318 struct sunplus_rtc
*sp_rtc
= dev_get_drvdata(dev
);
320 if (device_may_wakeup(dev
))
321 enable_irq_wake(sp_rtc
->irq
);
326 static int sp_rtc_resume(struct device
*dev
)
328 struct sunplus_rtc
*sp_rtc
= dev_get_drvdata(dev
);
330 if (device_may_wakeup(dev
))
331 disable_irq_wake(sp_rtc
->irq
);
337 static const struct of_device_id sp_rtc_of_match
[] = {
338 { .compatible
= "sunplus,sp7021-rtc" },
341 MODULE_DEVICE_TABLE(of
, sp_rtc_of_match
);
343 static SIMPLE_DEV_PM_OPS(sp_rtc_pm_ops
, sp_rtc_suspend
, sp_rtc_resume
);
345 static struct platform_driver sp_rtc_driver
= {
346 .probe
= sp_rtc_probe
,
347 .remove
= sp_rtc_remove
,
349 .name
= "sp7021-rtc",
350 .of_match_table
= sp_rtc_of_match
,
351 .pm
= &sp_rtc_pm_ops
,
354 module_platform_driver(sp_rtc_driver
);
356 MODULE_AUTHOR("Vincent Shih <vincent.sunplus@gmail.com>");
357 MODULE_DESCRIPTION("Sunplus RTC driver");
358 MODULE_LICENSE("GPL v2");