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Merge tag 'powerpc-6.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[linux.git] / drivers / usb / dwc3 / core.c
blobf219c82e9619d940300bda6d7cd01cca8977b578
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/of_graph.h>
27 #include <linux/acpi.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/reset.h>
30 #include <linux/bitfield.h>
31
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/of.h>
35 #include <linux/usb/otg.h>
36
37 #include "core.h"
38 #include "gadget.h"
39 #include "io.h"
40
41 #include "debug.h"
42 #include "../host/xhci-ext-caps.h"
43
44 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
45
46 /**
47 * dwc3_get_dr_mode - Validates and sets dr_mode
48 * @dwc: pointer to our context structure
49 */
50 static int dwc3_get_dr_mode(struct dwc3 *dwc)
51 {
52 enum usb_dr_mode mode;
53 struct device *dev = dwc->dev;
54 unsigned int hw_mode;
55
56 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
57 dwc->dr_mode = USB_DR_MODE_OTG;
58
59 mode = dwc->dr_mode;
60 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
61
62 switch (hw_mode) {
63 case DWC3_GHWPARAMS0_MODE_GADGET:
64 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
65 dev_err(dev,
66 "Controller does not support host mode.\n");
67 return -EINVAL;
68 }
69 mode = USB_DR_MODE_PERIPHERAL;
70 break;
71 case DWC3_GHWPARAMS0_MODE_HOST:
72 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
73 dev_err(dev,
74 "Controller does not support device mode.\n");
75 return -EINVAL;
76 }
77 mode = USB_DR_MODE_HOST;
78 break;
79 default:
80 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
81 mode = USB_DR_MODE_HOST;
82 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
83 mode = USB_DR_MODE_PERIPHERAL;
84
85 /*
86 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
87 * mode. If the controller supports DRD but the dr_mode is not
88 * specified or set to OTG, then set the mode to peripheral.
89 */
90 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
91 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
92 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
93 !DWC3_VER_IS_PRIOR(DWC3, 330A))
94 mode = USB_DR_MODE_PERIPHERAL;
95 }
96
97 if (mode != dwc->dr_mode) {
98 dev_warn(dev,
99 "Configuration mismatch. dr_mode forced to %s\n",
100 mode == USB_DR_MODE_HOST ? "host" : "gadget");
101
102 dwc->dr_mode = mode;
103 }
104
105 return 0;
106 }
107
108 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
109 {
110 u32 reg;
111 int i;
112
113 for (i = 0; i < dwc->num_usb3_ports; i++) {
114 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
115 if (enable && !dwc->dis_u3_susphy_quirk)
116 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
117 else
118 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
119
120 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
121 }
122
123 for (i = 0; i < dwc->num_usb2_ports; i++) {
124 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
125 if (enable && !dwc->dis_u2_susphy_quirk)
126 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
127 else
128 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
129
130 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
131 }
132 }
133
134 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
135 {
136 u32 reg;
137
138 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
139 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
140 reg |= DWC3_GCTL_PRTCAPDIR(mode);
141 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
142
143 dwc->current_dr_role = mode;
144 }
145
146 static void __dwc3_set_mode(struct work_struct *work)
147 {
148 struct dwc3 *dwc = work_to_dwc(work);
149 unsigned long flags;
150 int ret;
151 u32 reg;
152 u32 desired_dr_role;
153 int i;
154
155 mutex_lock(&dwc->mutex);
156 spin_lock_irqsave(&dwc->lock, flags);
157 desired_dr_role = dwc->desired_dr_role;
158 spin_unlock_irqrestore(&dwc->lock, flags);
159
160 pm_runtime_get_sync(dwc->dev);
161
162 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
163 dwc3_otg_update(dwc, 0);
164
165 if (!desired_dr_role)
166 goto out;
167
168 if (desired_dr_role == dwc->current_dr_role)
169 goto out;
170
171 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
172 goto out;
173
174 switch (dwc->current_dr_role) {
175 case DWC3_GCTL_PRTCAP_HOST:
176 dwc3_host_exit(dwc);
177 break;
178 case DWC3_GCTL_PRTCAP_DEVICE:
179 dwc3_gadget_exit(dwc);
180 dwc3_event_buffers_cleanup(dwc);
181 break;
182 case DWC3_GCTL_PRTCAP_OTG:
183 dwc3_otg_exit(dwc);
184 spin_lock_irqsave(&dwc->lock, flags);
185 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
186 spin_unlock_irqrestore(&dwc->lock, flags);
187 dwc3_otg_update(dwc, 1);
188 break;
189 default:
190 break;
191 }
192
193 /*
194 * When current_dr_role is not set, there's no role switching.
195 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
196 */
197 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
198 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
199 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
200 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
201 reg |= DWC3_GCTL_CORESOFTRESET;
202 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
203
204 /*
205 * Wait for internal clocks to synchronized. DWC_usb31 and
206 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
207 * keep it consistent across different IPs, let's wait up to
208 * 100ms before clearing GCTL.CORESOFTRESET.
209 */
210 msleep(100);
211
212 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
213 reg &= ~DWC3_GCTL_CORESOFTRESET;
214 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
215 }
216
217 spin_lock_irqsave(&dwc->lock, flags);
218
219 dwc3_set_prtcap(dwc, desired_dr_role);
220
221 spin_unlock_irqrestore(&dwc->lock, flags);
222
223 switch (desired_dr_role) {
224 case DWC3_GCTL_PRTCAP_HOST:
225 ret = dwc3_host_init(dwc);
226 if (ret) {
227 dev_err(dwc->dev, "failed to initialize host\n");
228 } else {
229 if (dwc->usb2_phy)
230 otg_set_vbus(dwc->usb2_phy->otg, true);
231
232 for (i = 0; i < dwc->num_usb2_ports; i++)
233 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
234 for (i = 0; i < dwc->num_usb3_ports; i++)
235 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
236
237 if (dwc->dis_split_quirk) {
238 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
239 reg |= DWC3_GUCTL3_SPLITDISABLE;
240 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
241 }
242 }
243 break;
244 case DWC3_GCTL_PRTCAP_DEVICE:
245 dwc3_core_soft_reset(dwc);
246
247 dwc3_event_buffers_setup(dwc);
248
249 if (dwc->usb2_phy)
250 otg_set_vbus(dwc->usb2_phy->otg, false);
251 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
252 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
253
254 ret = dwc3_gadget_init(dwc);
255 if (ret)
256 dev_err(dwc->dev, "failed to initialize peripheral\n");
257 break;
258 case DWC3_GCTL_PRTCAP_OTG:
259 dwc3_otg_init(dwc);
260 dwc3_otg_update(dwc, 0);
261 break;
262 default:
263 break;
264 }
265
266 out:
267 pm_runtime_mark_last_busy(dwc->dev);
268 pm_runtime_put_autosuspend(dwc->dev);
269 mutex_unlock(&dwc->mutex);
270 }
271
272 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
273 {
274 unsigned long flags;
275
276 if (dwc->dr_mode != USB_DR_MODE_OTG)
277 return;
278
279 spin_lock_irqsave(&dwc->lock, flags);
280 dwc->desired_dr_role = mode;
281 spin_unlock_irqrestore(&dwc->lock, flags);
282
283 queue_work(system_freezable_wq, &dwc->drd_work);
284 }
285
286 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
287 {
288 struct dwc3 *dwc = dep->dwc;
289 u32 reg;
290
291 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
292 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
293 DWC3_GDBGFIFOSPACE_TYPE(type));
294
295 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
296
297 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
298 }
299
300 /**
301 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
302 * @dwc: pointer to our context structure
303 */
304 int dwc3_core_soft_reset(struct dwc3 *dwc)
305 {
306 u32 reg;
307 int retries = 1000;
308
309 /*
310 * We're resetting only the device side because, if we're in host mode,
311 * XHCI driver will reset the host block. If dwc3 was configured for
312 * host-only mode, then we can return early.
313 */
314 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
315 return 0;
316
317 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
318 reg |= DWC3_DCTL_CSFTRST;
319 reg &= ~DWC3_DCTL_RUN_STOP;
320 dwc3_gadget_dctl_write_safe(dwc, reg);
321
322 /*
323 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
324 * is cleared only after all the clocks are synchronized. This can
325 * take a little more than 50ms. Set the polling rate at 20ms
326 * for 10 times instead.
327 */
328 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
329 retries = 10;
330
331 do {
332 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
333 if (!(reg & DWC3_DCTL_CSFTRST))
334 goto done;
335
336 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
337 msleep(20);
338 else
339 udelay(1);
340 } while (--retries);
341
342 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
343 return -ETIMEDOUT;
344
345 done:
346 /*
347 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
348 * is cleared, we must wait at least 50ms before accessing the PHY
349 * domain (synchronization delay).
350 */
351 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
352 msleep(50);
353
354 return 0;
355 }
356
357 /*
358 * dwc3_frame_length_adjustment - Adjusts frame length if required
359 * @dwc3: Pointer to our controller context structure
360 */
361 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
362 {
363 u32 reg;
364 u32 dft;
365
366 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
367 return;
368
369 if (dwc->fladj == 0)
370 return;
371
372 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
373 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
374 if (dft != dwc->fladj) {
375 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
376 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
377 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
378 }
379 }
380
381 /**
382 * dwc3_ref_clk_period - Reference clock period configuration
383 * Default reference clock period depends on hardware
384 * configuration. For systems with reference clock that differs
385 * from the default, this will set clock period in DWC3_GUCTL
386 * register.
387 * @dwc: Pointer to our controller context structure
388 */
389 static void dwc3_ref_clk_period(struct dwc3 *dwc)
390 {
391 unsigned long period;
392 unsigned long fladj;
393 unsigned long decr;
394 unsigned long rate;
395 u32 reg;
396
397 if (dwc->ref_clk) {
398 rate = clk_get_rate(dwc->ref_clk);
399 if (!rate)
400 return;
401 period = NSEC_PER_SEC / rate;
402 } else if (dwc->ref_clk_per) {
403 period = dwc->ref_clk_per;
404 rate = NSEC_PER_SEC / period;
405 } else {
406 return;
407 }
408
409 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
410 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
411 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
412 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
413
414 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
415 return;
416
417 /*
418 * The calculation below is
419 *
420 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
421 *
422 * but rearranged for fixed-point arithmetic. The division must be
423 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
424 * neither does rate * period).
425 *
426 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
427 * nanoseconds of error caused by the truncation which happened during
428 * the division when calculating rate or period (whichever one was
429 * derived from the other). We first calculate the relative error, then
430 * scale it to units of 8 ppm.
431 */
432 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
433 fladj -= 125000;
434
435 /*
436 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
437 */
438 decr = 480000000 / rate;
439
440 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
441 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
442 & ~DWC3_GFLADJ_240MHZDECR
443 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
444 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
445 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
446 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
447
448 if (dwc->gfladj_refclk_lpm_sel)
449 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
450
451 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
452 }
453
454 /**
455 * dwc3_free_one_event_buffer - Frees one event buffer
456 * @dwc: Pointer to our controller context structure
457 * @evt: Pointer to event buffer to be freed
458 */
459 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
460 struct dwc3_event_buffer *evt)
461 {
462 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
463 }
464
465 /**
466 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
467 * @dwc: Pointer to our controller context structure
468 * @length: size of the event buffer
469 *
470 * Returns a pointer to the allocated event buffer structure on success
471 * otherwise ERR_PTR(errno).
472 */
473 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
474 unsigned int length)
475 {
476 struct dwc3_event_buffer *evt;
477
478 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
479 if (!evt)
480 return ERR_PTR(-ENOMEM);
481
482 evt->dwc = dwc;
483 evt->length = length;
484 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
485 if (!evt->cache)
486 return ERR_PTR(-ENOMEM);
487
488 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
489 &evt->dma, GFP_KERNEL);
490 if (!evt->buf)
491 return ERR_PTR(-ENOMEM);
492
493 return evt;
494 }
495
496 /**
497 * dwc3_free_event_buffers - frees all allocated event buffers
498 * @dwc: Pointer to our controller context structure
499 */
500 static void dwc3_free_event_buffers(struct dwc3 *dwc)
501 {
502 struct dwc3_event_buffer *evt;
503
504 evt = dwc->ev_buf;
505 if (evt)
506 dwc3_free_one_event_buffer(dwc, evt);
507 }
508
509 /**
510 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
511 * @dwc: pointer to our controller context structure
512 * @length: size of event buffer
513 *
514 * Returns 0 on success otherwise negative errno. In the error case, dwc
515 * may contain some buffers allocated but not all which were requested.
516 */
517 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
518 {
519 struct dwc3_event_buffer *evt;
520 unsigned int hw_mode;
521
522 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
523 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
524 dwc->ev_buf = NULL;
525 return 0;
526 }
527
528 evt = dwc3_alloc_one_event_buffer(dwc, length);
529 if (IS_ERR(evt)) {
530 dev_err(dwc->dev, "can't allocate event buffer\n");
531 return PTR_ERR(evt);
532 }
533 dwc->ev_buf = evt;
534
535 return 0;
536 }
537
538 /**
539 * dwc3_event_buffers_setup - setup our allocated event buffers
540 * @dwc: pointer to our controller context structure
541 *
542 * Returns 0 on success otherwise negative errno.
543 */
544 int dwc3_event_buffers_setup(struct dwc3 *dwc)
545 {
546 struct dwc3_event_buffer *evt;
547 u32 reg;
548
549 if (!dwc->ev_buf)
550 return 0;
551
552 evt = dwc->ev_buf;
553 evt->lpos = 0;
554 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
555 lower_32_bits(evt->dma));
556 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
557 upper_32_bits(evt->dma));
558 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
559 DWC3_GEVNTSIZ_SIZE(evt->length));
560
561 /* Clear any stale event */
562 reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
563 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg);
564 return 0;
565 }
566
567 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
568 {
569 struct dwc3_event_buffer *evt;
570 u32 reg;
571
572 if (!dwc->ev_buf)
573 return;
574 /*
575 * Exynos platforms may not be able to access event buffer if the
576 * controller failed to halt on dwc3_core_exit().
577 */
578 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
579 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
580 return;
581
582 evt = dwc->ev_buf;
583
584 evt->lpos = 0;
585
586 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
587 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
588 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
589 | DWC3_GEVNTSIZ_SIZE(0));
590
591 /* Clear any stale event */
592 reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
593 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg);
594 }
595
596 static void dwc3_core_num_eps(struct dwc3 *dwc)
597 {
598 struct dwc3_hwparams *parms = &dwc->hwparams;
599
600 dwc->num_eps = DWC3_NUM_EPS(parms);
601 }
602
603 static void dwc3_cache_hwparams(struct dwc3 *dwc)
604 {
605 struct dwc3_hwparams *parms = &dwc->hwparams;
606
607 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
608 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
609 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
610 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
611 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
612 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
613 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
614 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
615 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
616
617 if (DWC3_IP_IS(DWC32))
618 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
619 }
620
621 static void dwc3_config_soc_bus(struct dwc3 *dwc)
622 {
623 if (dwc->gsbuscfg0_reqinfo != DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) {
624 u32 reg;
625
626 reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
627 reg &= ~DWC3_GSBUSCFG0_REQINFO(~0);
628 reg |= DWC3_GSBUSCFG0_REQINFO(dwc->gsbuscfg0_reqinfo);
629 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
630 }
631 }
632
633 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
634 {
635 int intf;
636 int ret = 0;
637
638 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
639
640 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
641 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
642 dwc->hsphy_interface &&
643 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
644 ret = dwc3_ulpi_init(dwc);
645
646 return ret;
647 }
648
649 static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
650 {
651 u32 reg;
652
653 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
654
655 /*
656 * Make sure UX_EXIT_PX is cleared as that causes issues with some
657 * PHYs. Also, this bit is not supposed to be used in normal operation.
658 */
659 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
660
661 /*
662 * Above DWC_usb3.0 1.94a, it is recommended to set
663 * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration.
664 * So default value will be '0' when the core is reset. Application
665 * needs to set it to '1' after the core initialization is completed.
666 *
667 * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be
668 * cleared after power-on reset, and it can be set after core
669 * initialization.
670 */
671 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
672
673 if (dwc->u2ss_inp3_quirk)
674 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
675
676 if (dwc->dis_rxdet_inp3_quirk)
677 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
678
679 if (dwc->req_p1p2p3_quirk)
680 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
681
682 if (dwc->del_p1p2p3_quirk)
683 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
684
685 if (dwc->del_phy_power_chg_quirk)
686 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
687
688 if (dwc->lfps_filter_quirk)
689 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
690
691 if (dwc->rx_detect_poll_quirk)
692 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
693
694 if (dwc->tx_de_emphasis_quirk)
695 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
696
697 if (dwc->dis_del_phy_power_chg_quirk)
698 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
699
700 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);
701
702 return 0;
703 }
704
705 static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
706 {
707 u32 reg;
708
709 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
710
711 /* Select the HS PHY interface */
712 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
713 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
714 if (dwc->hsphy_interface &&
715 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
716 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
717 break;
718 } else if (dwc->hsphy_interface &&
719 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
720 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
721 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
722 } else {
723 /* Relying on default value. */
724 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
725 break;
726 }
727 fallthrough;
728 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
729 default:
730 break;
731 }
732
733 switch (dwc->hsphy_mode) {
734 case USBPHY_INTERFACE_MODE_UTMI:
735 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
736 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
737 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
738 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
739 break;
740 case USBPHY_INTERFACE_MODE_UTMIW:
741 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
742 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
743 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
744 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
745 break;
746 default:
747 break;
748 }
749
750 /*
751 * Above DWC_usb3.0 1.94a, it is recommended to set
752 * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration.
753 * So default value will be '0' when the core is reset. Application
754 * needs to set it to '1' after the core initialization is completed.
755 *
756 * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared
757 * after power-on reset, and it can be set after core initialization.
758 */
759 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
760
761 if (dwc->dis_enblslpm_quirk)
762 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
763 else
764 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
765
766 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
767 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
768
769 /*
770 * Some ULPI USB PHY does not support internal VBUS supply, to drive
771 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
772 * bit of OTG_CTRL register. Controller configures the USB2 PHY
773 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
774 * with an external supply.
775 */
776 if (dwc->ulpi_ext_vbus_drv)
777 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
778
779 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
780
781 return 0;
782 }
783
784 /**
785 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
786 * @dwc: Pointer to our controller context structure
787 *
788 * Returns 0 on success. The USB PHY interfaces are configured but not
789 * initialized. The PHY interfaces and the PHYs get initialized together with
790 * the core in dwc3_core_init.
791 */
792 static int dwc3_phy_setup(struct dwc3 *dwc)
793 {
794 int i;
795 int ret;
796
797 for (i = 0; i < dwc->num_usb3_ports; i++) {
798 ret = dwc3_ss_phy_setup(dwc, i);
799 if (ret)
800 return ret;
801 }
802
803 for (i = 0; i < dwc->num_usb2_ports; i++) {
804 ret = dwc3_hs_phy_setup(dwc, i);
805 if (ret)
806 return ret;
807 }
808
809 return 0;
810 }
811
812 static int dwc3_phy_init(struct dwc3 *dwc)
813 {
814 int ret;
815 int i;
816 int j;
817
818 usb_phy_init(dwc->usb2_phy);
819 usb_phy_init(dwc->usb3_phy);
820
821 for (i = 0; i < dwc->num_usb2_ports; i++) {
822 ret = phy_init(dwc->usb2_generic_phy[i]);
823 if (ret < 0)
824 goto err_exit_usb2_phy;
825 }
826
827 for (j = 0; j < dwc->num_usb3_ports; j++) {
828 ret = phy_init(dwc->usb3_generic_phy[j]);
829 if (ret < 0)
830 goto err_exit_usb3_phy;
831 }
832
833 return 0;
834
835 err_exit_usb3_phy:
836 while (--j >= 0)
837 phy_exit(dwc->usb3_generic_phy[j]);
838
839 err_exit_usb2_phy:
840 while (--i >= 0)
841 phy_exit(dwc->usb2_generic_phy[i]);
842
843 usb_phy_shutdown(dwc->usb3_phy);
844 usb_phy_shutdown(dwc->usb2_phy);
845
846 return ret;
847 }
848
849 static void dwc3_phy_exit(struct dwc3 *dwc)
850 {
851 int i;
852
853 for (i = 0; i < dwc->num_usb3_ports; i++)
854 phy_exit(dwc->usb3_generic_phy[i]);
855
856 for (i = 0; i < dwc->num_usb2_ports; i++)
857 phy_exit(dwc->usb2_generic_phy[i]);
858
859 usb_phy_shutdown(dwc->usb3_phy);
860 usb_phy_shutdown(dwc->usb2_phy);
861 }
862
863 static int dwc3_phy_power_on(struct dwc3 *dwc)
864 {
865 int ret;
866 int i;
867 int j;
868
869 usb_phy_set_suspend(dwc->usb2_phy, 0);
870 usb_phy_set_suspend(dwc->usb3_phy, 0);
871
872 for (i = 0; i < dwc->num_usb2_ports; i++) {
873 ret = phy_power_on(dwc->usb2_generic_phy[i]);
874 if (ret < 0)
875 goto err_power_off_usb2_phy;
876 }
877
878 for (j = 0; j < dwc->num_usb3_ports; j++) {
879 ret = phy_power_on(dwc->usb3_generic_phy[j]);
880 if (ret < 0)
881 goto err_power_off_usb3_phy;
882 }
883
884 return 0;
885
886 err_power_off_usb3_phy:
887 while (--j >= 0)
888 phy_power_off(dwc->usb3_generic_phy[j]);
889
890 err_power_off_usb2_phy:
891 while (--i >= 0)
892 phy_power_off(dwc->usb2_generic_phy[i]);
893
894 usb_phy_set_suspend(dwc->usb3_phy, 1);
895 usb_phy_set_suspend(dwc->usb2_phy, 1);
896
897 return ret;
898 }
899
900 static void dwc3_phy_power_off(struct dwc3 *dwc)
901 {
902 int i;
903
904 for (i = 0; i < dwc->num_usb3_ports; i++)
905 phy_power_off(dwc->usb3_generic_phy[i]);
906
907 for (i = 0; i < dwc->num_usb2_ports; i++)
908 phy_power_off(dwc->usb2_generic_phy[i]);
909
910 usb_phy_set_suspend(dwc->usb3_phy, 1);
911 usb_phy_set_suspend(dwc->usb2_phy, 1);
912 }
913
914 static int dwc3_clk_enable(struct dwc3 *dwc)
915 {
916 int ret;
917
918 ret = clk_prepare_enable(dwc->bus_clk);
919 if (ret)
920 return ret;
921
922 ret = clk_prepare_enable(dwc->ref_clk);
923 if (ret)
924 goto disable_bus_clk;
925
926 ret = clk_prepare_enable(dwc->susp_clk);
927 if (ret)
928 goto disable_ref_clk;
929
930 ret = clk_prepare_enable(dwc->utmi_clk);
931 if (ret)
932 goto disable_susp_clk;
933
934 ret = clk_prepare_enable(dwc->pipe_clk);
935 if (ret)
936 goto disable_utmi_clk;
937
938 return 0;
939
940 disable_utmi_clk:
941 clk_disable_unprepare(dwc->utmi_clk);
942 disable_susp_clk:
943 clk_disable_unprepare(dwc->susp_clk);
944 disable_ref_clk:
945 clk_disable_unprepare(dwc->ref_clk);
946 disable_bus_clk:
947 clk_disable_unprepare(dwc->bus_clk);
948 return ret;
949 }
950
951 static void dwc3_clk_disable(struct dwc3 *dwc)
952 {
953 clk_disable_unprepare(dwc->pipe_clk);
954 clk_disable_unprepare(dwc->utmi_clk);
955 clk_disable_unprepare(dwc->susp_clk);
956 clk_disable_unprepare(dwc->ref_clk);
957 clk_disable_unprepare(dwc->bus_clk);
958 }
959
960 static void dwc3_core_exit(struct dwc3 *dwc)
961 {
962 dwc3_event_buffers_cleanup(dwc);
963 dwc3_phy_power_off(dwc);
964 dwc3_phy_exit(dwc);
965 dwc3_clk_disable(dwc);
966 reset_control_assert(dwc->reset);
967 }
968
969 static bool dwc3_core_is_valid(struct dwc3 *dwc)
970 {
971 u32 reg;
972
973 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
974 dwc->ip = DWC3_GSNPS_ID(reg);
975
976 /* This should read as U3 followed by revision number */
977 if (DWC3_IP_IS(DWC3)) {
978 dwc->revision = reg;
979 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
980 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
981 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
982 } else {
983 return false;
984 }
985
986 return true;
987 }
988
989 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
990 {
991 unsigned int power_opt;
992 unsigned int hw_mode;
993 u32 reg;
994
995 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
996 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
997 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
998 power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
999
1000 switch (power_opt) {
1001 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
1002 /**
1003 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
1004 * issue which would cause xHCI compliance tests to fail.
1005 *
1006 * Because of that we cannot enable clock gating on such
1007 * configurations.
1008 *
1009 * Refers to:
1010 *
1011 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
1012 * SOF/ITP Mode Used
1013 */
1014 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
1015 dwc->dr_mode == USB_DR_MODE_OTG) &&
1016 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
1017 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
1018 else
1019 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
1020 break;
1021 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
1022 /*
1023 * REVISIT Enabling this bit so that host-mode hibernation
1024 * will work. Device-mode hibernation is not yet implemented.
1025 */
1026 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
1027 break;
1028 default:
1029 /* nothing */
1030 break;
1031 }
1032
1033 /*
1034 * This is a workaround for STAR#4846132, which only affects
1035 * DWC_usb31 version2.00a operating in host mode.
1036 *
1037 * There is a problem in DWC_usb31 version 2.00a operating
1038 * in host mode that would cause a CSR read timeout When CSR
1039 * read coincides with RAM Clock Gating Entry. By disable
1040 * Clock Gating, sacrificing power consumption for normal
1041 * operation.
1042 */
1043 if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO &&
1044 hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A))
1045 reg |= DWC3_GCTL_DSBLCLKGTNG;
1046
1047 /* check if current dwc3 is on simulation board */
1048 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
1049 dev_info(dwc->dev, "Running with FPGA optimizations\n");
1050 dwc->is_fpga = true;
1051 }
1052
1053 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
1054 "disable_scramble cannot be used on non-FPGA builds\n");
1055
1056 if (dwc->disable_scramble_quirk && dwc->is_fpga)
1057 reg |= DWC3_GCTL_DISSCRAMBLE;
1058 else
1059 reg &= ~DWC3_GCTL_DISSCRAMBLE;
1060
1061 if (dwc->u2exit_lfps_quirk)
1062 reg |= DWC3_GCTL_U2EXIT_LFPS;
1063
1064 /*
1065 * WORKAROUND: DWC3 revisions <1.90a have a bug
1066 * where the device can fail to connect at SuperSpeed
1067 * and falls back to high-speed mode which causes
1068 * the device to enter a Connect/Disconnect loop
1069 */
1070 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
1071 reg |= DWC3_GCTL_U2RSTECN;
1072
1073 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1074 }
1075
1076 static int dwc3_core_get_phy(struct dwc3 *dwc);
1077 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
1078
1079 /* set global incr burst type configuration registers */
1080 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
1081 {
1082 struct device *dev = dwc->dev;
1083 /* incrx_mode : for INCR burst type. */
1084 bool incrx_mode;
1085 /* incrx_size : for size of INCRX burst. */
1086 u32 incrx_size;
1087 u32 *vals;
1088 u32 cfg;
1089 int ntype;
1090 int ret;
1091 int i;
1092
1093 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
1094
1095 /*
1096 * Handle property "snps,incr-burst-type-adjustment".
1097 * Get the number of value from this property:
1098 * result <= 0, means this property is not supported.
1099 * result = 1, means INCRx burst mode supported.
1100 * result > 1, means undefined length burst mode supported.
1101 */
1102 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
1103 if (ntype <= 0)
1104 return;
1105
1106 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
1107 if (!vals)
1108 return;
1109
1110 /* Get INCR burst type, and parse it */
1111 ret = device_property_read_u32_array(dev,
1112 "snps,incr-burst-type-adjustment", vals, ntype);
1113 if (ret) {
1114 kfree(vals);
1115 dev_err(dev, "Error to get property\n");
1116 return;
1117 }
1118
1119 incrx_size = *vals;
1120
1121 if (ntype > 1) {
1122 /* INCRX (undefined length) burst mode */
1123 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
1124 for (i = 1; i < ntype; i++) {
1125 if (vals[i] > incrx_size)
1126 incrx_size = vals[i];
1127 }
1128 } else {
1129 /* INCRX burst mode */
1130 incrx_mode = INCRX_BURST_MODE;
1131 }
1132
1133 kfree(vals);
1134
1135 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1136 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1137 if (incrx_mode)
1138 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1139 switch (incrx_size) {
1140 case 256:
1141 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1142 break;
1143 case 128:
1144 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1145 break;
1146 case 64:
1147 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1148 break;
1149 case 32:
1150 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1151 break;
1152 case 16:
1153 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1154 break;
1155 case 8:
1156 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1157 break;
1158 case 4:
1159 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1160 break;
1161 case 1:
1162 break;
1163 default:
1164 dev_err(dev, "Invalid property\n");
1165 break;
1166 }
1167
1168 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1169 }
1170
1171 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1172 {
1173 u32 scale;
1174 u32 reg;
1175
1176 if (!dwc->susp_clk)
1177 return;
1178
1179 /*
1180 * The power down scale field specifies how many suspend_clk
1181 * periods fit into a 16KHz clock period. When performing
1182 * the division, round up the remainder.
1183 *
1184 * The power down scale value is calculated using the fastest
1185 * frequency of the suspend_clk. If it isn't fixed (but within
1186 * the accuracy requirement), the driver may not know the max
1187 * rate of the suspend_clk, so only update the power down scale
1188 * if the default is less than the calculated value from
1189 * clk_get_rate() or if the default is questionably high
1190 * (3x or more) to be within the requirement.
1191 */
1192 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1193 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1194 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1195 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1196 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1197 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1198 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1199 }
1200 }
1201
1202 static void dwc3_config_threshold(struct dwc3 *dwc)
1203 {
1204 u32 reg;
1205 u8 rx_thr_num;
1206 u8 rx_maxburst;
1207 u8 tx_thr_num;
1208 u8 tx_maxburst;
1209
1210 /*
1211 * Must config both number of packets and max burst settings to enable
1212 * RX and/or TX threshold.
1213 */
1214 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1215 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1216 rx_maxburst = dwc->rx_max_burst_prd;
1217 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1218 tx_maxburst = dwc->tx_max_burst_prd;
1219
1220 if (rx_thr_num && rx_maxburst) {
1221 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1222 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1223
1224 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1225 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1226
1227 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1228 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1229
1230 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1231 }
1232
1233 if (tx_thr_num && tx_maxburst) {
1234 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1235 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1236
1237 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1238 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1239
1240 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1241 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1242
1243 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1244 }
1245 }
1246
1247 rx_thr_num = dwc->rx_thr_num_pkt;
1248 rx_maxburst = dwc->rx_max_burst;
1249 tx_thr_num = dwc->tx_thr_num_pkt;
1250 tx_maxburst = dwc->tx_max_burst;
1251
1252 if (DWC3_IP_IS(DWC3)) {
1253 if (rx_thr_num && rx_maxburst) {
1254 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1255 reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
1256
1257 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
1258 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1259
1260 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1261 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1262
1263 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1264 }
1265
1266 if (tx_thr_num && tx_maxburst) {
1267 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1268 reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
1269
1270 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
1271 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1272
1273 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1274 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1275
1276 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1277 }
1278 } else {
1279 if (rx_thr_num && rx_maxburst) {
1280 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1281 reg |= DWC31_GRXTHRCFG_PKTCNTSEL;
1282
1283 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
1284 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1285
1286 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1287 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1288
1289 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1290 }
1291
1292 if (tx_thr_num && tx_maxburst) {
1293 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1294 reg |= DWC31_GTXTHRCFG_PKTCNTSEL;
1295
1296 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
1297 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1298
1299 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1300 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1301
1302 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1303 }
1304 }
1305 }
1306
1307 /**
1308 * dwc3_core_init - Low-level initialization of DWC3 Core
1309 * @dwc: Pointer to our controller context structure
1310 *
1311 * Returns 0 on success otherwise negative errno.
1312 */
1313 static int dwc3_core_init(struct dwc3 *dwc)
1314 {
1315 unsigned int hw_mode;
1316 u32 reg;
1317 int ret;
1318
1319 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1320
1321 /*
1322 * Write Linux Version Code to our GUID register so it's easy to figure
1323 * out which kernel version a bug was found.
1324 */
1325 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1326
1327 ret = dwc3_phy_setup(dwc);
1328 if (ret)
1329 return ret;
1330
1331 if (!dwc->ulpi_ready) {
1332 ret = dwc3_core_ulpi_init(dwc);
1333 if (ret) {
1334 if (ret == -ETIMEDOUT) {
1335 dwc3_core_soft_reset(dwc);
1336 ret = -EPROBE_DEFER;
1337 }
1338 return ret;
1339 }
1340 dwc->ulpi_ready = true;
1341 }
1342
1343 if (!dwc->phys_ready) {
1344 ret = dwc3_core_get_phy(dwc);
1345 if (ret)
1346 goto err_exit_ulpi;
1347 dwc->phys_ready = true;
1348 }
1349
1350 ret = dwc3_phy_init(dwc);
1351 if (ret)
1352 goto err_exit_ulpi;
1353
1354 ret = dwc3_core_soft_reset(dwc);
1355 if (ret)
1356 goto err_exit_phy;
1357
1358 dwc3_core_setup_global_control(dwc);
1359 dwc3_core_num_eps(dwc);
1360
1361 /* Set power down scale of suspend_clk */
1362 dwc3_set_power_down_clk_scale(dwc);
1363
1364 /* Adjust Frame Length */
1365 dwc3_frame_length_adjustment(dwc);
1366
1367 /* Adjust Reference Clock Period */
1368 dwc3_ref_clk_period(dwc);
1369
1370 dwc3_set_incr_burst_type(dwc);
1371
1372 dwc3_config_soc_bus(dwc);
1373
1374 ret = dwc3_phy_power_on(dwc);
1375 if (ret)
1376 goto err_exit_phy;
1377
1378 ret = dwc3_event_buffers_setup(dwc);
1379 if (ret) {
1380 dev_err(dwc->dev, "failed to setup event buffers\n");
1381 goto err_power_off_phy;
1382 }
1383
1384 /*
1385 * ENDXFER polling is available on version 3.10a and later of
1386 * the DWC_usb3 controller. It is NOT available in the
1387 * DWC_usb31 controller.
1388 */
1389 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1390 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1391 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1392 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1393 }
1394
1395 /*
1396 * STAR 9001285599: This issue affects DWC_usb3 version 3.20a
1397 * only. If the PM TIMER ECM is enabled through GUCTL2[19], the
1398 * link compliance test (TD7.21) may fail. If the ECN is not
1399 * enabled (GUCTL2[19] = 0), the controller will use the old timer
1400 * value (5us), which is still acceptable for the link compliance
1401 * test. Therefore, do not enable PM TIMER ECM in 3.20a by
1402 * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0.
1403 */
1404 if (DWC3_VER_IS(DWC3, 320A)) {
1405 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1406 reg &= ~DWC3_GUCTL2_LC_TIMER;
1407 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1408 }
1409
1410 /*
1411 * When configured in HOST mode, after issuing U3/L2 exit controller
1412 * fails to send proper CRC checksum in CRC5 field. Because of this
1413 * behaviour Transaction Error is generated, resulting in reset and
1414 * re-enumeration of usb device attached. All the termsel, xcvrsel,
1415 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1416 * will correct this problem. This option is to support certain
1417 * legacy ULPI PHYs.
1418 */
1419 if (dwc->resume_hs_terminations) {
1420 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1421 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1422 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1423 }
1424
1425 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1426 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1427
1428 /*
1429 * Enable hardware control of sending remote wakeup
1430 * in HS when the device is in the L1 state.
1431 */
1432 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1433 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1434
1435 /*
1436 * Decouple USB 2.0 L1 & L2 events which will allow for
1437 * gadget driver to only receive U3/L2 suspend & wakeup
1438 * events and prevent the more frequent L1 LPM transitions
1439 * from interrupting the driver.
1440 */
1441 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1442 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1443
1444 if (dwc->dis_tx_ipgap_linecheck_quirk)
1445 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1446
1447 if (dwc->parkmode_disable_ss_quirk)
1448 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1449
1450 if (dwc->parkmode_disable_hs_quirk)
1451 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1452
1453 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)) {
1454 if (dwc->maximum_speed == USB_SPEED_FULL ||
1455 dwc->maximum_speed == USB_SPEED_HIGH)
1456 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1457 else
1458 reg &= ~DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1459 }
1460
1461 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1462 }
1463
1464 dwc3_config_threshold(dwc);
1465
1466 /*
1467 * Modify this for all supported Super Speed ports when
1468 * multiport support is added.
1469 */
1470 if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET &&
1471 (DWC3_IP_IS(DWC31)) &&
1472 dwc->maximum_speed == USB_SPEED_SUPER) {
1473 int i;
1474
1475 for (i = 0; i < dwc->num_usb3_ports; i++) {
1476 reg = dwc3_readl(dwc->regs, DWC3_LLUCTL(i));
1477 reg |= DWC3_LLUCTL_FORCE_GEN1;
1478 dwc3_writel(dwc->regs, DWC3_LLUCTL(i), reg);
1479 }
1480 }
1481
1482 return 0;
1483
1484 err_power_off_phy:
1485 dwc3_phy_power_off(dwc);
1486 err_exit_phy:
1487 dwc3_phy_exit(dwc);
1488 err_exit_ulpi:
1489 dwc3_ulpi_exit(dwc);
1490
1491 return ret;
1492 }
1493
1494 static int dwc3_core_get_phy(struct dwc3 *dwc)
1495 {
1496 struct device *dev = dwc->dev;
1497 struct device_node *node = dev->of_node;
1498 char phy_name[9];
1499 int ret;
1500 u8 i;
1501
1502 if (node) {
1503 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1504 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1505 } else {
1506 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1507 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1508 }
1509
1510 if (IS_ERR(dwc->usb2_phy)) {
1511 ret = PTR_ERR(dwc->usb2_phy);
1512 if (ret == -ENXIO || ret == -ENODEV)
1513 dwc->usb2_phy = NULL;
1514 else
1515 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1516 }
1517
1518 if (IS_ERR(dwc->usb3_phy)) {
1519 ret = PTR_ERR(dwc->usb3_phy);
1520 if (ret == -ENXIO || ret == -ENODEV)
1521 dwc->usb3_phy = NULL;
1522 else
1523 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1524 }
1525
1526 for (i = 0; i < dwc->num_usb2_ports; i++) {
1527 if (dwc->num_usb2_ports == 1)
1528 snprintf(phy_name, sizeof(phy_name), "usb2-phy");
1529 else
1530 snprintf(phy_name, sizeof(phy_name), "usb2-%u", i);
1531
1532 dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
1533 if (IS_ERR(dwc->usb2_generic_phy[i])) {
1534 ret = PTR_ERR(dwc->usb2_generic_phy[i]);
1535 if (ret == -ENOSYS || ret == -ENODEV)
1536 dwc->usb2_generic_phy[i] = NULL;
1537 else
1538 return dev_err_probe(dev, ret, "failed to lookup phy %s\n",
1539 phy_name);
1540 }
1541 }
1542
1543 for (i = 0; i < dwc->num_usb3_ports; i++) {
1544 if (dwc->num_usb3_ports == 1)
1545 snprintf(phy_name, sizeof(phy_name), "usb3-phy");
1546 else
1547 snprintf(phy_name, sizeof(phy_name), "usb3-%u", i);
1548
1549 dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
1550 if (IS_ERR(dwc->usb3_generic_phy[i])) {
1551 ret = PTR_ERR(dwc->usb3_generic_phy[i]);
1552 if (ret == -ENOSYS || ret == -ENODEV)
1553 dwc->usb3_generic_phy[i] = NULL;
1554 else
1555 return dev_err_probe(dev, ret, "failed to lookup phy %s\n",
1556 phy_name);
1557 }
1558 }
1559
1560 return 0;
1561 }
1562
1563 static int dwc3_core_init_mode(struct dwc3 *dwc)
1564 {
1565 struct device *dev = dwc->dev;
1566 int ret;
1567 int i;
1568
1569 switch (dwc->dr_mode) {
1570 case USB_DR_MODE_PERIPHERAL:
1571 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1572
1573 if (dwc->usb2_phy)
1574 otg_set_vbus(dwc->usb2_phy->otg, false);
1575 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
1576 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
1577
1578 ret = dwc3_gadget_init(dwc);
1579 if (ret)
1580 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1581 break;
1582 case USB_DR_MODE_HOST:
1583 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1584
1585 if (dwc->usb2_phy)
1586 otg_set_vbus(dwc->usb2_phy->otg, true);
1587 for (i = 0; i < dwc->num_usb2_ports; i++)
1588 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
1589 for (i = 0; i < dwc->num_usb3_ports; i++)
1590 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
1591
1592 ret = dwc3_host_init(dwc);
1593 if (ret)
1594 return dev_err_probe(dev, ret, "failed to initialize host\n");
1595 break;
1596 case USB_DR_MODE_OTG:
1597 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1598 ret = dwc3_drd_init(dwc);
1599 if (ret)
1600 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1601 break;
1602 default:
1603 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1604 return -EINVAL;
1605 }
1606
1607 return 0;
1608 }
1609
1610 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1611 {
1612 switch (dwc->dr_mode) {
1613 case USB_DR_MODE_PERIPHERAL:
1614 dwc3_gadget_exit(dwc);
1615 break;
1616 case USB_DR_MODE_HOST:
1617 dwc3_host_exit(dwc);
1618 break;
1619 case USB_DR_MODE_OTG:
1620 dwc3_drd_exit(dwc);
1621 break;
1622 default:
1623 /* do nothing */
1624 break;
1625 }
1626
1627 /* de-assert DRVVBUS for HOST and OTG mode */
1628 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1629 }
1630
1631 static void dwc3_get_software_properties(struct dwc3 *dwc)
1632 {
1633 struct device *tmpdev;
1634 u16 gsbuscfg0_reqinfo;
1635 int ret;
1636
1637 dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED;
1638
1639 /*
1640 * Iterate over all parent nodes for finding swnode properties
1641 * and non-DT (non-ABI) properties.
1642 */
1643 for (tmpdev = dwc->dev; tmpdev; tmpdev = tmpdev->parent) {
1644 ret = device_property_read_u16(tmpdev,
1645 "snps,gsbuscfg0-reqinfo",
1646 &gsbuscfg0_reqinfo);
1647 if (!ret)
1648 dwc->gsbuscfg0_reqinfo = gsbuscfg0_reqinfo;
1649 }
1650 }
1651
1652 static void dwc3_get_properties(struct dwc3 *dwc)
1653 {
1654 struct device *dev = dwc->dev;
1655 u8 lpm_nyet_threshold;
1656 u8 tx_de_emphasis;
1657 u8 hird_threshold;
1658 u8 rx_thr_num_pkt = 0;
1659 u8 rx_max_burst = 0;
1660 u8 tx_thr_num_pkt = 0;
1661 u8 tx_max_burst = 0;
1662 u8 rx_thr_num_pkt_prd = 0;
1663 u8 rx_max_burst_prd = 0;
1664 u8 tx_thr_num_pkt_prd = 0;
1665 u8 tx_max_burst_prd = 0;
1666 u8 tx_fifo_resize_max_num;
1667 const char *usb_psy_name;
1668 int ret;
1669
1670 /* default to highest possible threshold */
1671 lpm_nyet_threshold = 0xf;
1672
1673 /* default to -3.5dB de-emphasis */
1674 tx_de_emphasis = 1;
1675
1676 /*
1677 * default to assert utmi_sleep_n and use maximum allowed HIRD
1678 * threshold value of 0b1100
1679 */
1680 hird_threshold = 12;
1681
1682 /*
1683 * default to a TXFIFO size large enough to fit 6 max packets. This
1684 * allows for systems with larger bus latencies to have some headroom
1685 * for endpoints that have a large bMaxBurst value.
1686 */
1687 tx_fifo_resize_max_num = 6;
1688
1689 dwc->maximum_speed = usb_get_maximum_speed(dev);
1690 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1691 dwc->dr_mode = usb_get_dr_mode(dev);
1692 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1693
1694 dwc->sysdev_is_parent = device_property_read_bool(dev,
1695 "linux,sysdev_is_parent");
1696 if (dwc->sysdev_is_parent)
1697 dwc->sysdev = dwc->dev->parent;
1698 else
1699 dwc->sysdev = dwc->dev;
1700
1701 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev);
1702
1703 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1704 if (ret >= 0) {
1705 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1706 if (!dwc->usb_psy)
1707 dev_err(dev, "couldn't get usb power supply\n");
1708 }
1709
1710 dwc->has_lpm_erratum = device_property_read_bool(dev,
1711 "snps,has-lpm-erratum");
1712 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1713 &lpm_nyet_threshold);
1714 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1715 "snps,is-utmi-l1-suspend");
1716 device_property_read_u8(dev, "snps,hird-threshold",
1717 &hird_threshold);
1718 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1719 "snps,dis-start-transfer-quirk");
1720 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1721 "snps,usb3_lpm_capable");
1722 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1723 "snps,usb2-lpm-disable");
1724 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1725 "snps,usb2-gadget-lpm-disable");
1726 device_property_read_u8(dev, "snps,rx-thr-num-pkt",
1727 &rx_thr_num_pkt);
1728 device_property_read_u8(dev, "snps,rx-max-burst",
1729 &rx_max_burst);
1730 device_property_read_u8(dev, "snps,tx-thr-num-pkt",
1731 &tx_thr_num_pkt);
1732 device_property_read_u8(dev, "snps,tx-max-burst",
1733 &tx_max_burst);
1734 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1735 &rx_thr_num_pkt_prd);
1736 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1737 &rx_max_burst_prd);
1738 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1739 &tx_thr_num_pkt_prd);
1740 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1741 &tx_max_burst_prd);
1742 dwc->do_fifo_resize = device_property_read_bool(dev,
1743 "tx-fifo-resize");
1744 if (dwc->do_fifo_resize)
1745 device_property_read_u8(dev, "tx-fifo-max-num",
1746 &tx_fifo_resize_max_num);
1747
1748 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1749 "snps,disable_scramble_quirk");
1750 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1751 "snps,u2exit_lfps_quirk");
1752 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1753 "snps,u2ss_inp3_quirk");
1754 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1755 "snps,req_p1p2p3_quirk");
1756 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1757 "snps,del_p1p2p3_quirk");
1758 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1759 "snps,del_phy_power_chg_quirk");
1760 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1761 "snps,lfps_filter_quirk");
1762 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1763 "snps,rx_detect_poll_quirk");
1764 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1765 "snps,dis_u3_susphy_quirk");
1766 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1767 "snps,dis_u2_susphy_quirk");
1768 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1769 "snps,dis_enblslpm_quirk");
1770 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1771 "snps,dis-u1-entry-quirk");
1772 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1773 "snps,dis-u2-entry-quirk");
1774 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1775 "snps,dis_rxdet_inp3_quirk");
1776 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1777 "snps,dis-u2-freeclk-exists-quirk");
1778 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1779 "snps,dis-del-phy-power-chg-quirk");
1780 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1781 "snps,dis-tx-ipgap-linecheck-quirk");
1782 dwc->resume_hs_terminations = device_property_read_bool(dev,
1783 "snps,resume-hs-terminations");
1784 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1785 "snps,ulpi-ext-vbus-drv");
1786 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1787 "snps,parkmode-disable-ss-quirk");
1788 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1789 "snps,parkmode-disable-hs-quirk");
1790 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1791 "snps,gfladj-refclk-lpm-sel-quirk");
1792
1793 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1794 "snps,tx_de_emphasis_quirk");
1795 device_property_read_u8(dev, "snps,tx_de_emphasis",
1796 &tx_de_emphasis);
1797 device_property_read_string(dev, "snps,hsphy_interface",
1798 &dwc->hsphy_interface);
1799 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1800 &dwc->fladj);
1801 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1802 &dwc->ref_clk_per);
1803
1804 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1805 "snps,dis_metastability_quirk");
1806
1807 dwc->dis_split_quirk = device_property_read_bool(dev,
1808 "snps,dis-split-quirk");
1809
1810 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1811 dwc->tx_de_emphasis = tx_de_emphasis;
1812
1813 dwc->hird_threshold = hird_threshold;
1814
1815 dwc->rx_thr_num_pkt = rx_thr_num_pkt;
1816 dwc->rx_max_burst = rx_max_burst;
1817
1818 dwc->tx_thr_num_pkt = tx_thr_num_pkt;
1819 dwc->tx_max_burst = tx_max_burst;
1820
1821 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1822 dwc->rx_max_burst_prd = rx_max_burst_prd;
1823
1824 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1825 dwc->tx_max_burst_prd = tx_max_burst_prd;
1826
1827 dwc->imod_interval = 0;
1828
1829 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1830 }
1831
1832 /* check whether the core supports IMOD */
1833 bool dwc3_has_imod(struct dwc3 *dwc)
1834 {
1835 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1836 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1837 DWC3_IP_IS(DWC32);
1838 }
1839
1840 static void dwc3_check_params(struct dwc3 *dwc)
1841 {
1842 struct device *dev = dwc->dev;
1843 unsigned int hwparam_gen =
1844 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1845
1846 /* Check for proper value of imod_interval */
1847 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1848 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1849 dwc->imod_interval = 0;
1850 }
1851
1852 /*
1853 * Workaround for STAR 9000961433 which affects only version
1854 * 3.00a of the DWC_usb3 core. This prevents the controller
1855 * interrupt from being masked while handling events. IMOD
1856 * allows us to work around this issue. Enable it for the
1857 * affected version.
1858 */
1859 if (!dwc->imod_interval &&
1860 DWC3_VER_IS(DWC3, 300A))
1861 dwc->imod_interval = 1;
1862
1863 /* Check the maximum_speed parameter */
1864 switch (dwc->maximum_speed) {
1865 case USB_SPEED_FULL:
1866 case USB_SPEED_HIGH:
1867 break;
1868 case USB_SPEED_SUPER:
1869 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1870 dev_warn(dev, "UDC doesn't support Gen 1\n");
1871 break;
1872 case USB_SPEED_SUPER_PLUS:
1873 if ((DWC3_IP_IS(DWC32) &&
1874 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1875 (!DWC3_IP_IS(DWC32) &&
1876 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1877 dev_warn(dev, "UDC doesn't support SSP\n");
1878 break;
1879 default:
1880 dev_err(dev, "invalid maximum_speed parameter %d\n",
1881 dwc->maximum_speed);
1882 fallthrough;
1883 case USB_SPEED_UNKNOWN:
1884 switch (hwparam_gen) {
1885 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1886 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1887 break;
1888 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1889 if (DWC3_IP_IS(DWC32))
1890 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1891 else
1892 dwc->maximum_speed = USB_SPEED_SUPER;
1893 break;
1894 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1895 dwc->maximum_speed = USB_SPEED_HIGH;
1896 break;
1897 default:
1898 dwc->maximum_speed = USB_SPEED_SUPER;
1899 break;
1900 }
1901 break;
1902 }
1903
1904 /*
1905 * Currently the controller does not have visibility into the HW
1906 * parameter to determine the maximum number of lanes the HW supports.
1907 * If the number of lanes is not specified in the device property, then
1908 * set the default to support dual-lane for DWC_usb32 and single-lane
1909 * for DWC_usb31 for super-speed-plus.
1910 */
1911 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1912 switch (dwc->max_ssp_rate) {
1913 case USB_SSP_GEN_2x1:
1914 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1915 dev_warn(dev, "UDC only supports Gen 1\n");
1916 break;
1917 case USB_SSP_GEN_1x2:
1918 case USB_SSP_GEN_2x2:
1919 if (DWC3_IP_IS(DWC31))
1920 dev_warn(dev, "UDC only supports single lane\n");
1921 break;
1922 case USB_SSP_GEN_UNKNOWN:
1923 default:
1924 switch (hwparam_gen) {
1925 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1926 if (DWC3_IP_IS(DWC32))
1927 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1928 else
1929 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1930 break;
1931 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1932 if (DWC3_IP_IS(DWC32))
1933 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1934 break;
1935 }
1936 break;
1937 }
1938 }
1939 }
1940
1941 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1942 {
1943 struct device *dev = dwc->dev;
1944 struct device_node *np_phy;
1945 struct extcon_dev *edev = NULL;
1946 const char *name;
1947
1948 if (device_property_present(dev, "extcon"))
1949 return extcon_get_edev_by_phandle(dev, 0);
1950
1951 /*
1952 * Device tree platforms should get extcon via phandle.
1953 * On ACPI platforms, we get the name from a device property.
1954 * This device property is for kernel internal use only and
1955 * is expected to be set by the glue code.
1956 */
1957 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1958 return extcon_get_extcon_dev(name);
1959
1960 /*
1961 * Check explicitly if "usb-role-switch" is used since
1962 * extcon_find_edev_by_node() can not be used to check the absence of
1963 * an extcon device. In the absence of an device it will always return
1964 * EPROBE_DEFER.
1965 */
1966 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
1967 device_property_read_bool(dev, "usb-role-switch"))
1968 return NULL;
1969
1970 /*
1971 * Try to get an extcon device from the USB PHY controller's "port"
1972 * node. Check if it has the "port" node first, to avoid printing the
1973 * error message from underlying code, as it's a valid case: extcon
1974 * device (and "port" node) may be missing in case of "usb-role-switch"
1975 * or OTG mode.
1976 */
1977 np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1978 if (of_graph_is_present(np_phy)) {
1979 struct device_node *np_conn;
1980
1981 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1982 if (np_conn)
1983 edev = extcon_find_edev_by_node(np_conn);
1984 of_node_put(np_conn);
1985 }
1986 of_node_put(np_phy);
1987
1988 return edev;
1989 }
1990
1991 static int dwc3_get_clocks(struct dwc3 *dwc)
1992 {
1993 struct device *dev = dwc->dev;
1994
1995 if (!dev->of_node)
1996 return 0;
1997
1998 /*
1999 * Clocks are optional, but new DT platforms should support all clocks
2000 * as required by the DT-binding.
2001 * Some devices have different clock names in legacy device trees,
2002 * check for them to retain backwards compatibility.
2003 */
2004 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
2005 if (IS_ERR(dwc->bus_clk)) {
2006 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
2007 "could not get bus clock\n");
2008 }
2009
2010 if (dwc->bus_clk == NULL) {
2011 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
2012 if (IS_ERR(dwc->bus_clk)) {
2013 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
2014 "could not get bus clock\n");
2015 }
2016 }
2017
2018 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
2019 if (IS_ERR(dwc->ref_clk)) {
2020 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
2021 "could not get ref clock\n");
2022 }
2023
2024 if (dwc->ref_clk == NULL) {
2025 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
2026 if (IS_ERR(dwc->ref_clk)) {
2027 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
2028 "could not get ref clock\n");
2029 }
2030 }
2031
2032 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
2033 if (IS_ERR(dwc->susp_clk)) {
2034 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
2035 "could not get suspend clock\n");
2036 }
2037
2038 if (dwc->susp_clk == NULL) {
2039 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
2040 if (IS_ERR(dwc->susp_clk)) {
2041 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
2042 "could not get suspend clock\n");
2043 }
2044 }
2045
2046 /* specific to Rockchip RK3588 */
2047 dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
2048 if (IS_ERR(dwc->utmi_clk)) {
2049 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
2050 "could not get utmi clock\n");
2051 }
2052
2053 /* specific to Rockchip RK3588 */
2054 dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
2055 if (IS_ERR(dwc->pipe_clk)) {
2056 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
2057 "could not get pipe clock\n");
2058 }
2059
2060 return 0;
2061 }
2062
2063 static int dwc3_get_num_ports(struct dwc3 *dwc)
2064 {
2065 void __iomem *base;
2066 u8 major_revision;
2067 u32 offset;
2068 u32 val;
2069
2070 /*
2071 * Remap xHCI address space to access XHCI ext cap regs since it is
2072 * needed to get information on number of ports present.
2073 */
2074 base = ioremap(dwc->xhci_resources[0].start,
2075 resource_size(&dwc->xhci_resources[0]));
2076 if (!base)
2077 return -ENOMEM;
2078
2079 offset = 0;
2080 do {
2081 offset = xhci_find_next_ext_cap(base, offset,
2082 XHCI_EXT_CAPS_PROTOCOL);
2083 if (!offset)
2084 break;
2085
2086 val = readl(base + offset);
2087 major_revision = XHCI_EXT_PORT_MAJOR(val);
2088
2089 val = readl(base + offset + 0x08);
2090 if (major_revision == 0x03) {
2091 dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val);
2092 } else if (major_revision <= 0x02) {
2093 dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val);
2094 } else {
2095 dev_warn(dwc->dev, "unrecognized port major revision %d\n",
2096 major_revision);
2097 }
2098 } while (1);
2099
2100 dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
2101 dwc->num_usb2_ports, dwc->num_usb3_ports);
2102
2103 iounmap(base);
2104
2105 if (dwc->num_usb2_ports > DWC3_USB2_MAX_PORTS ||
2106 dwc->num_usb3_ports > DWC3_USB3_MAX_PORTS)
2107 return -EINVAL;
2108
2109 return 0;
2110 }
2111
2112 static int dwc3_probe(struct platform_device *pdev)
2113 {
2114 struct device *dev = &pdev->dev;
2115 struct resource *res, dwc_res;
2116 unsigned int hw_mode;
2117 void __iomem *regs;
2118 struct dwc3 *dwc;
2119 int ret;
2120
2121 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
2122 if (!dwc)
2123 return -ENOMEM;
2124
2125 dwc->dev = dev;
2126
2127 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2128 if (!res) {
2129 dev_err(dev, "missing memory resource\n");
2130 return -ENODEV;
2131 }
2132
2133 dwc->xhci_resources[0].start = res->start;
2134 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
2135 DWC3_XHCI_REGS_END;
2136 dwc->xhci_resources[0].flags = res->flags;
2137 dwc->xhci_resources[0].name = res->name;
2138
2139 /*
2140 * Request memory region but exclude xHCI regs,
2141 * since it will be requested by the xhci-plat driver.
2142 */
2143 dwc_res = *res;
2144 dwc_res.start += DWC3_GLOBALS_REGS_START;
2145
2146 if (dev->of_node) {
2147 struct device_node *parent = of_get_parent(dev->of_node);
2148
2149 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) {
2150 dwc_res.start -= DWC3_GLOBALS_REGS_START;
2151 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
2152 }
2153
2154 of_node_put(parent);
2155 }
2156
2157 regs = devm_ioremap_resource(dev, &dwc_res);
2158 if (IS_ERR(regs))
2159 return PTR_ERR(regs);
2160
2161 dwc->regs = regs;
2162 dwc->regs_size = resource_size(&dwc_res);
2163
2164 dwc3_get_properties(dwc);
2165
2166 dwc3_get_software_properties(dwc);
2167
2168 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
2169 if (IS_ERR(dwc->reset)) {
2170 ret = PTR_ERR(dwc->reset);
2171 goto err_put_psy;
2172 }
2173
2174 ret = dwc3_get_clocks(dwc);
2175 if (ret)
2176 goto err_put_psy;
2177
2178 ret = reset_control_deassert(dwc->reset);
2179 if (ret)
2180 goto err_put_psy;
2181
2182 ret = dwc3_clk_enable(dwc);
2183 if (ret)
2184 goto err_assert_reset;
2185
2186 if (!dwc3_core_is_valid(dwc)) {
2187 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
2188 ret = -ENODEV;
2189 goto err_disable_clks;
2190 }
2191
2192 platform_set_drvdata(pdev, dwc);
2193 dwc3_cache_hwparams(dwc);
2194
2195 if (!dwc->sysdev_is_parent &&
2196 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
2197 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
2198 if (ret)
2199 goto err_disable_clks;
2200 }
2201
2202 /*
2203 * Currently only DWC3 controllers that are host-only capable
2204 * can have more than one port.
2205 */
2206 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
2207 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
2208 ret = dwc3_get_num_ports(dwc);
2209 if (ret)
2210 goto err_disable_clks;
2211 } else {
2212 dwc->num_usb2_ports = 1;
2213 dwc->num_usb3_ports = 1;
2214 }
2215
2216 spin_lock_init(&dwc->lock);
2217 mutex_init(&dwc->mutex);
2218
2219 pm_runtime_get_noresume(dev);
2220 pm_runtime_set_active(dev);
2221 pm_runtime_use_autosuspend(dev);
2222 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
2223 pm_runtime_enable(dev);
2224
2225 pm_runtime_forbid(dev);
2226
2227 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
2228 if (ret) {
2229 dev_err(dwc->dev, "failed to allocate event buffers\n");
2230 ret = -ENOMEM;
2231 goto err_allow_rpm;
2232 }
2233
2234 dwc->edev = dwc3_get_extcon(dwc);
2235 if (IS_ERR(dwc->edev)) {
2236 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
2237 goto err_free_event_buffers;
2238 }
2239
2240 ret = dwc3_get_dr_mode(dwc);
2241 if (ret)
2242 goto err_free_event_buffers;
2243
2244 ret = dwc3_core_init(dwc);
2245 if (ret) {
2246 dev_err_probe(dev, ret, "failed to initialize core\n");
2247 goto err_free_event_buffers;
2248 }
2249
2250 dwc3_check_params(dwc);
2251 dwc3_debugfs_init(dwc);
2252
2253 ret = dwc3_core_init_mode(dwc);
2254 if (ret)
2255 goto err_exit_debugfs;
2256
2257 pm_runtime_put(dev);
2258
2259 dma_set_max_seg_size(dev, UINT_MAX);
2260
2261 return 0;
2262
2263 err_exit_debugfs:
2264 dwc3_debugfs_exit(dwc);
2265 dwc3_event_buffers_cleanup(dwc);
2266 dwc3_phy_power_off(dwc);
2267 dwc3_phy_exit(dwc);
2268 dwc3_ulpi_exit(dwc);
2269 err_free_event_buffers:
2270 dwc3_free_event_buffers(dwc);
2271 err_allow_rpm:
2272 pm_runtime_allow(dev);
2273 pm_runtime_disable(dev);
2274 pm_runtime_dont_use_autosuspend(dev);
2275 pm_runtime_set_suspended(dev);
2276 pm_runtime_put_noidle(dev);
2277 err_disable_clks:
2278 dwc3_clk_disable(dwc);
2279 err_assert_reset:
2280 reset_control_assert(dwc->reset);
2281 err_put_psy:
2282 if (dwc->usb_psy)
2283 power_supply_put(dwc->usb_psy);
2284
2285 return ret;
2286 }
2287
2288 static void dwc3_remove(struct platform_device *pdev)
2289 {
2290 struct dwc3 *dwc = platform_get_drvdata(pdev);
2291
2292 pm_runtime_get_sync(&pdev->dev);
2293
2294 dwc3_core_exit_mode(dwc);
2295 dwc3_debugfs_exit(dwc);
2296
2297 dwc3_core_exit(dwc);
2298 dwc3_ulpi_exit(dwc);
2299
2300 pm_runtime_allow(&pdev->dev);
2301 pm_runtime_disable(&pdev->dev);
2302 pm_runtime_dont_use_autosuspend(&pdev->dev);
2303 pm_runtime_put_noidle(&pdev->dev);
2304 /*
2305 * HACK: Clear the driver data, which is currently accessed by parent
2306 * glue drivers, before allowing the parent to suspend.
2307 */
2308 platform_set_drvdata(pdev, NULL);
2309 pm_runtime_set_suspended(&pdev->dev);
2310
2311 dwc3_free_event_buffers(dwc);
2312
2313 if (dwc->usb_psy)
2314 power_supply_put(dwc->usb_psy);
2315 }
2316
2317 #ifdef CONFIG_PM
2318 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
2319 {
2320 int ret;
2321
2322 ret = reset_control_deassert(dwc->reset);
2323 if (ret)
2324 return ret;
2325
2326 ret = dwc3_clk_enable(dwc);
2327 if (ret)
2328 goto assert_reset;
2329
2330 ret = dwc3_core_init(dwc);
2331 if (ret)
2332 goto disable_clks;
2333
2334 return 0;
2335
2336 disable_clks:
2337 dwc3_clk_disable(dwc);
2338 assert_reset:
2339 reset_control_assert(dwc->reset);
2340
2341 return ret;
2342 }
2343
2344 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
2345 {
2346 u32 reg;
2347 int i;
2348
2349 if (!pm_runtime_suspended(dwc->dev) && !PMSG_IS_AUTO(msg)) {
2350 dwc->susphy_state = (dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)) &
2351 DWC3_GUSB2PHYCFG_SUSPHY) ||
2352 (dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)) &
2353 DWC3_GUSB3PIPECTL_SUSPHY);
2354 /*
2355 * TI AM62 platform requires SUSPHY to be
2356 * enabled for system suspend to work.
2357 */
2358 if (!dwc->susphy_state)
2359 dwc3_enable_susphy(dwc, true);
2360 }
2361
2362 switch (dwc->current_dr_role) {
2363 case DWC3_GCTL_PRTCAP_DEVICE:
2364 if (pm_runtime_suspended(dwc->dev))
2365 break;
2366 dwc3_gadget_suspend(dwc);
2367 synchronize_irq(dwc->irq_gadget);
2368 dwc3_core_exit(dwc);
2369 break;
2370 case DWC3_GCTL_PRTCAP_HOST:
2371 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2372 dwc3_core_exit(dwc);
2373 break;
2374 }
2375
2376 /* Let controller to suspend HSPHY before PHY driver suspends */
2377 if (dwc->dis_u2_susphy_quirk ||
2378 dwc->dis_enblslpm_quirk) {
2379 for (i = 0; i < dwc->num_usb2_ports; i++) {
2380 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
2381 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
2382 DWC3_GUSB2PHYCFG_SUSPHY;
2383 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
2384 }
2385
2386 /* Give some time for USB2 PHY to suspend */
2387 usleep_range(5000, 6000);
2388 }
2389
2390 for (i = 0; i < dwc->num_usb2_ports; i++)
2391 phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
2392 for (i = 0; i < dwc->num_usb3_ports; i++)
2393 phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
2394 break;
2395 case DWC3_GCTL_PRTCAP_OTG:
2396 /* do nothing during runtime_suspend */
2397 if (PMSG_IS_AUTO(msg))
2398 break;
2399
2400 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2401 dwc3_gadget_suspend(dwc);
2402 synchronize_irq(dwc->irq_gadget);
2403 }
2404
2405 dwc3_otg_exit(dwc);
2406 dwc3_core_exit(dwc);
2407 break;
2408 default:
2409 /* do nothing */
2410 break;
2411 }
2412
2413 return 0;
2414 }
2415
2416 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2417 {
2418 int ret;
2419 u32 reg;
2420 int i;
2421
2422 switch (dwc->current_dr_role) {
2423 case DWC3_GCTL_PRTCAP_DEVICE:
2424 ret = dwc3_core_init_for_resume(dwc);
2425 if (ret)
2426 return ret;
2427
2428 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2429 dwc3_gadget_resume(dwc);
2430 break;
2431 case DWC3_GCTL_PRTCAP_HOST:
2432 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2433 ret = dwc3_core_init_for_resume(dwc);
2434 if (ret)
2435 return ret;
2436 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2437 break;
2438 }
2439 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2440 for (i = 0; i < dwc->num_usb2_ports; i++) {
2441 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
2442 if (dwc->dis_u2_susphy_quirk)
2443 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2444
2445 if (dwc->dis_enblslpm_quirk)
2446 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2447
2448 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
2449 }
2450
2451 for (i = 0; i < dwc->num_usb2_ports; i++)
2452 phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
2453 for (i = 0; i < dwc->num_usb3_ports; i++)
2454 phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
2455 break;
2456 case DWC3_GCTL_PRTCAP_OTG:
2457 /* nothing to do on runtime_resume */
2458 if (PMSG_IS_AUTO(msg))
2459 break;
2460
2461 ret = dwc3_core_init_for_resume(dwc);
2462 if (ret)
2463 return ret;
2464
2465 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2466
2467 dwc3_otg_init(dwc);
2468 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2469 dwc3_otg_host_init(dwc);
2470 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2471 dwc3_gadget_resume(dwc);
2472 }
2473
2474 break;
2475 default:
2476 /* do nothing */
2477 break;
2478 }
2479
2480 if (!PMSG_IS_AUTO(msg)) {
2481 /* restore SUSPHY state to that before system suspend. */
2482 dwc3_enable_susphy(dwc, dwc->susphy_state);
2483 }
2484
2485 return 0;
2486 }
2487
2488 static int dwc3_runtime_checks(struct dwc3 *dwc)
2489 {
2490 switch (dwc->current_dr_role) {
2491 case DWC3_GCTL_PRTCAP_DEVICE:
2492 if (dwc->connected)
2493 return -EBUSY;
2494 break;
2495 case DWC3_GCTL_PRTCAP_HOST:
2496 default:
2497 /* do nothing */
2498 break;
2499 }
2500
2501 return 0;
2502 }
2503
2504 static int dwc3_runtime_suspend(struct device *dev)
2505 {
2506 struct dwc3 *dwc = dev_get_drvdata(dev);
2507 int ret;
2508
2509 if (dwc3_runtime_checks(dwc))
2510 return -EBUSY;
2511
2512 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2513 if (ret)
2514 return ret;
2515
2516 return 0;
2517 }
2518
2519 static int dwc3_runtime_resume(struct device *dev)
2520 {
2521 struct dwc3 *dwc = dev_get_drvdata(dev);
2522 int ret;
2523
2524 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2525 if (ret)
2526 return ret;
2527
2528 switch (dwc->current_dr_role) {
2529 case DWC3_GCTL_PRTCAP_DEVICE:
2530 if (dwc->pending_events) {
2531 pm_runtime_put(dwc->dev);
2532 dwc->pending_events = false;
2533 enable_irq(dwc->irq_gadget);
2534 }
2535 break;
2536 case DWC3_GCTL_PRTCAP_HOST:
2537 default:
2538 /* do nothing */
2539 break;
2540 }
2541
2542 pm_runtime_mark_last_busy(dev);
2543
2544 return 0;
2545 }
2546
2547 static int dwc3_runtime_idle(struct device *dev)
2548 {
2549 struct dwc3 *dwc = dev_get_drvdata(dev);
2550
2551 switch (dwc->current_dr_role) {
2552 case DWC3_GCTL_PRTCAP_DEVICE:
2553 if (dwc3_runtime_checks(dwc))
2554 return -EBUSY;
2555 break;
2556 case DWC3_GCTL_PRTCAP_HOST:
2557 default:
2558 /* do nothing */
2559 break;
2560 }
2561
2562 pm_runtime_mark_last_busy(dev);
2563 pm_runtime_autosuspend(dev);
2564
2565 return 0;
2566 }
2567 #endif /* CONFIG_PM */
2568
2569 #ifdef CONFIG_PM_SLEEP
2570 static int dwc3_suspend(struct device *dev)
2571 {
2572 struct dwc3 *dwc = dev_get_drvdata(dev);
2573 int ret;
2574
2575 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2576 if (ret)
2577 return ret;
2578
2579 pinctrl_pm_select_sleep_state(dev);
2580
2581 return 0;
2582 }
2583
2584 static int dwc3_resume(struct device *dev)
2585 {
2586 struct dwc3 *dwc = dev_get_drvdata(dev);
2587 int ret = 0;
2588
2589 pinctrl_pm_select_default_state(dev);
2590
2591 pm_runtime_disable(dev);
2592 pm_runtime_set_active(dev);
2593
2594 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2595 if (ret)
2596 pm_runtime_set_suspended(dev);
2597
2598 pm_runtime_enable(dev);
2599
2600 return ret;
2601 }
2602
2603 static void dwc3_complete(struct device *dev)
2604 {
2605 struct dwc3 *dwc = dev_get_drvdata(dev);
2606 u32 reg;
2607
2608 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2609 dwc->dis_split_quirk) {
2610 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2611 reg |= DWC3_GUCTL3_SPLITDISABLE;
2612 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2613 }
2614 }
2615 #else
2616 #define dwc3_complete NULL
2617 #endif /* CONFIG_PM_SLEEP */
2618
2619 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2620 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2621 .complete = dwc3_complete,
2622
2623 /*
2624 * Runtime suspend halts the controller on disconnection. It relies on
2625 * platforms with custom connection notification to start the controller
2626 * again.
2627 */
2628 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2629 dwc3_runtime_idle)
2630 };
2631
2632 #ifdef CONFIG_OF
2633 static const struct of_device_id of_dwc3_match[] = {
2634 {
2635 .compatible = "snps,dwc3"
2636 },
2637 {
2638 .compatible = "synopsys,dwc3"
2639 },
2640 { },
2641 };
2642 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2643 #endif
2644
2645 #ifdef CONFIG_ACPI
2646
2647 #define ACPI_ID_INTEL_BSW "808622B7"
2648
2649 static const struct acpi_device_id dwc3_acpi_match[] = {
2650 { ACPI_ID_INTEL_BSW, 0 },
2651 { },
2652 };
2653 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2654 #endif
2655
2656 static struct platform_driver dwc3_driver = {
2657 .probe = dwc3_probe,
2658 .remove = dwc3_remove,
2659 .driver = {
2660 .name = "dwc3",
2661 .of_match_table = of_match_ptr(of_dwc3_match),
2662 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2663 .pm = &dwc3_dev_pm_ops,
2664 },
2665 };
2666
2667 module_platform_driver(dwc3_driver);
2668
2669 MODULE_ALIAS("platform:dwc3");
2670 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2671 MODULE_LICENSE("GPL v2");
2672 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux Kernel