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module: Convert symbol namespace to string literal
[linux.git] / sound / pci / atiixp.c
blobdf2fef726d603bbcfa15b9328bf1532fe01bba83
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers
4 *
5 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
6 */
7
8 #include <linux/io.h>
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/init.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <sound/core.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/info.h>
20 #include <sound/ac97_codec.h>
21 #include <sound/initval.h>
22
23 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
24 MODULE_DESCRIPTION("ATI IXP AC97 controller");
25 MODULE_LICENSE("GPL");
26
27 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
28 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
29 static int ac97_clock = 48000;
30 static char *ac97_quirk;
31 static bool spdif_aclink = 1;
32 static int ac97_codec = -1;
33
34 module_param(index, int, 0444);
35 MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
36 module_param(id, charp, 0444);
37 MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
38 module_param(ac97_clock, int, 0444);
39 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
40 module_param(ac97_quirk, charp, 0444);
41 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
42 module_param(ac97_codec, int, 0444);
43 MODULE_PARM_DESC(ac97_codec, "Specify codec instead of probing.");
44 module_param(spdif_aclink, bool, 0444);
45 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
46
47 /* just for backward compatibility */
48 static bool enable;
49 module_param(enable, bool, 0444);
50
51
52 /*
53 */
54
55 #define ATI_REG_ISR 0x00 /* interrupt source */
56 #define ATI_REG_ISR_IN_XRUN (1U<<0)
57 #define ATI_REG_ISR_IN_STATUS (1U<<1)
58 #define ATI_REG_ISR_OUT_XRUN (1U<<2)
59 #define ATI_REG_ISR_OUT_STATUS (1U<<3)
60 #define ATI_REG_ISR_SPDF_XRUN (1U<<4)
61 #define ATI_REG_ISR_SPDF_STATUS (1U<<5)
62 #define ATI_REG_ISR_PHYS_INTR (1U<<8)
63 #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
64 #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
65 #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
66 #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
67 #define ATI_REG_ISR_NEW_FRAME (1U<<13)
68
69 #define ATI_REG_IER 0x04 /* interrupt enable */
70 #define ATI_REG_IER_IN_XRUN_EN (1U<<0)
71 #define ATI_REG_IER_IO_STATUS_EN (1U<<1)
72 #define ATI_REG_IER_OUT_XRUN_EN (1U<<2)
73 #define ATI_REG_IER_OUT_XRUN_COND (1U<<3)
74 #define ATI_REG_IER_SPDF_XRUN_EN (1U<<4)
75 #define ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
76 #define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
77 #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
78 #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
79 #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
80 #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
81 #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
82 #define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */
83
84 #define ATI_REG_CMD 0x08 /* command */
85 #define ATI_REG_CMD_POWERDOWN (1U<<0)
86 #define ATI_REG_CMD_RECEIVE_EN (1U<<1)
87 #define ATI_REG_CMD_SEND_EN (1U<<2)
88 #define ATI_REG_CMD_STATUS_MEM (1U<<3)
89 #define ATI_REG_CMD_SPDF_OUT_EN (1U<<4)
90 #define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5)
91 #define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
92 #define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6
93 #define ATI_REG_CMD_IN_DMA_EN (1U<<8)
94 #define ATI_REG_CMD_OUT_DMA_EN (1U<<9)
95 #define ATI_REG_CMD_SPDF_DMA_EN (1U<<10)
96 #define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11)
97 #define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12)
98 #define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12)
99 #define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12)
100 #define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12)
101 #define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12)
102 #define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16)
103 #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
104 #define ATI_REG_CMD_INTERLEAVE_IN (1U<<21)
105 #define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
106 #define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
107 #define ATI_REG_CMD_PACKED_DIS (1U<<24)
108 #define ATI_REG_CMD_BURST_EN (1U<<25)
109 #define ATI_REG_CMD_PANIC_EN (1U<<26)
110 #define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
111 #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
112 #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
113 #define ATI_REG_CMD_AC_SYNC (1U<<30)
114 #define ATI_REG_CMD_AC_RESET (1U<<31)
115
116 #define ATI_REG_PHYS_OUT_ADDR 0x0c
117 #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
118 #define ATI_REG_PHYS_OUT_RW (1U<<2)
119 #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
120 #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
121 #define ATI_REG_PHYS_OUT_DATA_SHIFT 16
122
123 #define ATI_REG_PHYS_IN_ADDR 0x10
124 #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
125 #define ATI_REG_PHYS_IN_ADDR_SHIFT 9
126 #define ATI_REG_PHYS_IN_DATA_SHIFT 16
127
128 #define ATI_REG_SLOTREQ 0x14
129
130 #define ATI_REG_COUNTER 0x18
131 #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
132 #define ATI_REG_COUNTER_BITCLOCK (31U<<8)
133
134 #define ATI_REG_IN_FIFO_THRESHOLD 0x1c
135
136 #define ATI_REG_IN_DMA_LINKPTR 0x20
137 #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
138 #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
139 #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
140 #define ATI_REG_IN_DMA_DT_SIZE 0x30
141
142 #define ATI_REG_OUT_DMA_SLOT 0x34
143 #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))
144 #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
145 #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
146 #define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11
147
148 #define ATI_REG_OUT_DMA_LINKPTR 0x38
149 #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
150 #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
151 #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
152 #define ATI_REG_OUT_DMA_DT_SIZE 0x48
153
154 #define ATI_REG_SPDF_CMD 0x4c
155 #define ATI_REG_SPDF_CMD_LFSR (1U<<4)
156 #define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
157 #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
158
159 #define ATI_REG_SPDF_DMA_LINKPTR 0x50
160 #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
161 #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
162 #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
163 #define ATI_REG_SPDF_DMA_DT_SIZE 0x60
164
165 #define ATI_REG_MODEM_MIRROR 0x7c
166 #define ATI_REG_AUDIO_MIRROR 0x80
167
168 #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
169 #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
170
171 #define ATI_REG_FIFO_FLUSH 0x88
172 #define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
173 #define ATI_REG_FIFO_IN_FLUSH (1U<<1)
174
175 /* LINKPTR */
176 #define ATI_REG_LINKPTR_EN (1U<<0)
177
178 /* [INT|OUT|SPDIF]_DMA_DT_SIZE */
179 #define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
180 #define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
181 #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)
182 #define ATI_REG_DMA_STATE (7U<<26)
183
184
185 #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
186
187
188 struct atiixp;
189
190 /*
191 * DMA packate descriptor
192 */
193
194 struct atiixp_dma_desc {
195 __le32 addr; /* DMA buffer address */
196 u16 status; /* status bits */
197 u16 size; /* size of the packet in dwords */
198 __le32 next; /* address of the next packet descriptor */
199 };
200
201 /*
202 * stream enum
203 */
204 enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */
205 enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */
206 enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */
207
208 #define NUM_ATI_CODECS 3
209
210
211 /*
212 * constants and callbacks for each DMA type
213 */
214 struct atiixp_dma_ops {
215 int type; /* ATI_DMA_XXX */
216 unsigned int llp_offset; /* LINKPTR offset */
217 unsigned int dt_cur; /* DT_CUR offset */
218 /* called from open callback */
219 void (*enable_dma)(struct atiixp *chip, int on);
220 /* called from trigger (START/STOP) */
221 void (*enable_transfer)(struct atiixp *chip, int on);
222 /* called from trigger (STOP only) */
223 void (*flush_dma)(struct atiixp *chip);
224 };
225
226 /*
227 * DMA stream
228 */
229 struct atiixp_dma {
230 const struct atiixp_dma_ops *ops;
231 struct snd_dma_buffer desc_buf;
232 struct snd_pcm_substream *substream; /* assigned PCM substream */
233 unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
234 unsigned int period_bytes, periods;
235 int opened;
236 int running;
237 int suspended;
238 int pcm_open_flag;
239 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
240 unsigned int saved_curptr;
241 };
242
243 /*
244 * ATI IXP chip
245 */
246 struct atiixp {
247 struct snd_card *card;
248 struct pci_dev *pci;
249
250 unsigned long addr;
251 void __iomem *remap_addr;
252 int irq;
253
254 struct snd_ac97_bus *ac97_bus;
255 struct snd_ac97 *ac97[NUM_ATI_CODECS];
256
257 spinlock_t reg_lock;
258
259 struct atiixp_dma dmas[NUM_ATI_DMAS];
260 struct ac97_pcm *pcms[NUM_ATI_PCMS];
261 struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS];
262
263 int max_channels; /* max. channels for PCM out */
264
265 unsigned int codec_not_ready_bits; /* for codec detection */
266
267 int spdif_over_aclink; /* passed from the module option */
268 struct mutex open_mutex; /* playback open mutex */
269 };
270
271
272 /*
273 */
274 static const struct pci_device_id snd_atiixp_ids[] = {
275 { PCI_VDEVICE(ATI, 0x4341), 0 }, /* SB200 */
276 { PCI_VDEVICE(ATI, 0x4361), 0 }, /* SB300 */
277 { PCI_VDEVICE(ATI, 0x4370), 0 }, /* SB400 */
278 { PCI_VDEVICE(ATI, 0x4382), 0 }, /* SB600 */
279 { 0, }
280 };
281
282 MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
283
284 static const struct snd_pci_quirk atiixp_quirks[] = {
285 SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0),
286 SND_PCI_QUIRK(0x15bd, 0x3100, "DFI RS482", 0),
287 { } /* terminator */
288 };
289
290 /*
291 * lowlevel functions
292 */
293
294 /*
295 * update the bits of the given register.
296 * return 1 if the bits changed.
297 */
298 static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg,
299 unsigned int mask, unsigned int value)
300 {
301 void __iomem *addr = chip->remap_addr + reg;
302 unsigned int data, old_data;
303 old_data = data = readl(addr);
304 data &= ~mask;
305 data |= value;
306 if (old_data == data)
307 return 0;
308 writel(data, addr);
309 return 1;
310 }
311
312 /*
313 * macros for easy use
314 */
315 #define atiixp_write(chip,reg,value) \
316 writel(value, chip->remap_addr + ATI_REG_##reg)
317 #define atiixp_read(chip,reg) \
318 readl(chip->remap_addr + ATI_REG_##reg)
319 #define atiixp_update(chip,reg,mask,val) \
320 snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
321
322 /*
323 * handling DMA packets
324 *
325 * we allocate a linear buffer for the DMA, and split it to each packet.
326 * in a future version, a scatter-gather buffer should be implemented.
327 */
328
329 #define ATI_DESC_LIST_SIZE \
330 PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc))
331
332 /*
333 * build packets ring for the given buffer size.
334 *
335 * IXP handles the buffer descriptors, which are connected as a linked
336 * list. although we can change the list dynamically, in this version,
337 * a static RING of buffer descriptors is used.
338 *
339 * the ring is built in this function, and is set up to the hardware.
340 */
341 static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
342 struct snd_pcm_substream *substream,
343 unsigned int periods,
344 unsigned int period_bytes)
345 {
346 unsigned int i;
347 u32 addr, desc_addr;
348 unsigned long flags;
349
350 if (periods > ATI_MAX_DESCRIPTORS)
351 return -ENOMEM;
352
353 if (dma->desc_buf.area == NULL) {
354 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
355 &chip->pci->dev,
356 ATI_DESC_LIST_SIZE,
357 &dma->desc_buf) < 0)
358 return -ENOMEM;
359 dma->period_bytes = dma->periods = 0; /* clear */
360 }
361
362 if (dma->periods == periods && dma->period_bytes == period_bytes)
363 return 0;
364
365 /* reset DMA before changing the descriptor table */
366 spin_lock_irqsave(&chip->reg_lock, flags);
367 writel(0, chip->remap_addr + dma->ops->llp_offset);
368 dma->ops->enable_dma(chip, 0);
369 dma->ops->enable_dma(chip, 1);
370 spin_unlock_irqrestore(&chip->reg_lock, flags);
371
372 /* fill the entries */
373 addr = (u32)substream->runtime->dma_addr;
374 desc_addr = (u32)dma->desc_buf.addr;
375 for (i = 0; i < periods; i++) {
376 struct atiixp_dma_desc *desc;
377 desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i];
378 desc->addr = cpu_to_le32(addr);
379 desc->status = 0;
380 desc->size = period_bytes >> 2; /* in dwords */
381 desc_addr += sizeof(struct atiixp_dma_desc);
382 if (i == periods - 1)
383 desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
384 else
385 desc->next = cpu_to_le32(desc_addr);
386 addr += period_bytes;
387 }
388
389 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
390 chip->remap_addr + dma->ops->llp_offset);
391
392 dma->period_bytes = period_bytes;
393 dma->periods = periods;
394
395 return 0;
396 }
397
398 /*
399 * remove the ring buffer and release it if assigned
400 */
401 static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
402 struct snd_pcm_substream *substream)
403 {
404 if (dma->desc_buf.area) {
405 writel(0, chip->remap_addr + dma->ops->llp_offset);
406 snd_dma_free_pages(&dma->desc_buf);
407 dma->desc_buf.area = NULL;
408 }
409 }
410
411 /*
412 * AC97 interface
413 */
414 static int snd_atiixp_acquire_codec(struct atiixp *chip)
415 {
416 int timeout = 1000;
417
418 while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
419 if (! timeout--) {
420 dev_warn(chip->card->dev, "codec acquire timeout\n");
421 return -EBUSY;
422 }
423 udelay(1);
424 }
425 return 0;
426 }
427
428 static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg)
429 {
430 unsigned int data;
431 int timeout;
432
433 if (snd_atiixp_acquire_codec(chip) < 0)
434 return 0xffff;
435 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
436 ATI_REG_PHYS_OUT_ADDR_EN |
437 ATI_REG_PHYS_OUT_RW |
438 codec;
439 atiixp_write(chip, PHYS_OUT_ADDR, data);
440 if (snd_atiixp_acquire_codec(chip) < 0)
441 return 0xffff;
442 timeout = 1000;
443 do {
444 data = atiixp_read(chip, PHYS_IN_ADDR);
445 if (data & ATI_REG_PHYS_IN_READ_FLAG)
446 return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
447 udelay(1);
448 } while (--timeout);
449 /* time out may happen during reset */
450 if (reg < 0x7c)
451 dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg);
452 return 0xffff;
453 }
454
455
456 static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec,
457 unsigned short reg, unsigned short val)
458 {
459 unsigned int data;
460
461 if (snd_atiixp_acquire_codec(chip) < 0)
462 return;
463 data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
464 ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
465 ATI_REG_PHYS_OUT_ADDR_EN | codec;
466 atiixp_write(chip, PHYS_OUT_ADDR, data);
467 }
468
469
470 static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97,
471 unsigned short reg)
472 {
473 struct atiixp *chip = ac97->private_data;
474 return snd_atiixp_codec_read(chip, ac97->num, reg);
475
476 }
477
478 static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
479 unsigned short val)
480 {
481 struct atiixp *chip = ac97->private_data;
482 snd_atiixp_codec_write(chip, ac97->num, reg, val);
483 }
484
485 /*
486 * reset AC link
487 */
488 static int snd_atiixp_aclink_reset(struct atiixp *chip)
489 {
490 int timeout;
491
492 /* reset powerdoewn */
493 if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
494 udelay(10);
495
496 /* perform a software reset */
497 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
498 atiixp_read(chip, CMD);
499 udelay(10);
500 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
501
502 timeout = 10;
503 while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
504 /* do a hard reset */
505 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
506 ATI_REG_CMD_AC_SYNC);
507 atiixp_read(chip, CMD);
508 mdelay(1);
509 atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
510 if (!--timeout) {
511 dev_err(chip->card->dev, "codec reset timeout\n");
512 break;
513 }
514 }
515
516 /* deassert RESET and assert SYNC to make sure */
517 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
518 ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
519
520 return 0;
521 }
522
523 static int snd_atiixp_aclink_down(struct atiixp *chip)
524 {
525 // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
526 // return -EBUSY;
527 atiixp_update(chip, CMD,
528 ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
529 ATI_REG_CMD_POWERDOWN);
530 return 0;
531 }
532
533 /*
534 * auto-detection of codecs
535 *
536 * the IXP chip can generate interrupts for the non-existing codecs.
537 * NEW_FRAME interrupt is used to make sure that the interrupt is generated
538 * even if all three codecs are connected.
539 */
540
541 #define ALL_CODEC_NOT_READY \
542 (ATI_REG_ISR_CODEC0_NOT_READY |\
543 ATI_REG_ISR_CODEC1_NOT_READY |\
544 ATI_REG_ISR_CODEC2_NOT_READY)
545 #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
546
547 static int ac97_probing_bugs(struct pci_dev *pci)
548 {
549 const struct snd_pci_quirk *q;
550
551 q = snd_pci_quirk_lookup(pci, atiixp_quirks);
552 if (q) {
553 dev_dbg(&pci->dev, "atiixp quirk for %s. Forcing codec %d\n",
554 snd_pci_quirk_name(q), q->value);
555 return q->value;
556 }
557 /* this hardware doesn't need workarounds. Probe for codec */
558 return -1;
559 }
560
561 static int snd_atiixp_codec_detect(struct atiixp *chip)
562 {
563 int timeout;
564
565 chip->codec_not_ready_bits = 0;
566 if (ac97_codec == -1)
567 ac97_codec = ac97_probing_bugs(chip->pci);
568 if (ac97_codec >= 0) {
569 chip->codec_not_ready_bits |=
570 CODEC_CHECK_BITS ^ (1 << (ac97_codec + 10));
571 return 0;
572 }
573
574 atiixp_write(chip, IER, CODEC_CHECK_BITS);
575 /* wait for the interrupts */
576 timeout = 50;
577 while (timeout-- > 0) {
578 mdelay(1);
579 if (chip->codec_not_ready_bits)
580 break;
581 }
582 atiixp_write(chip, IER, 0); /* disable irqs */
583
584 if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
585 dev_err(chip->card->dev, "no codec detected!\n");
586 return -ENXIO;
587 }
588 return 0;
589 }
590
591
592 /*
593 * enable DMA and irqs
594 */
595 static int snd_atiixp_chip_start(struct atiixp *chip)
596 {
597 unsigned int reg;
598
599 /* set up spdif, enable burst mode */
600 reg = atiixp_read(chip, CMD);
601 reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT;
602 reg |= ATI_REG_CMD_BURST_EN;
603 atiixp_write(chip, CMD, reg);
604
605 reg = atiixp_read(chip, SPDF_CMD);
606 reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH);
607 atiixp_write(chip, SPDF_CMD, reg);
608
609 /* clear all interrupt source */
610 atiixp_write(chip, ISR, 0xffffffff);
611 /* enable irqs */
612 atiixp_write(chip, IER,
613 ATI_REG_IER_IO_STATUS_EN |
614 ATI_REG_IER_IN_XRUN_EN |
615 ATI_REG_IER_OUT_XRUN_EN |
616 ATI_REG_IER_SPDF_XRUN_EN |
617 ATI_REG_IER_SPDF_STATUS_EN);
618 return 0;
619 }
620
621
622 /*
623 * disable DMA and IRQs
624 */
625 static int snd_atiixp_chip_stop(struct atiixp *chip)
626 {
627 /* clear interrupt source */
628 atiixp_write(chip, ISR, atiixp_read(chip, ISR));
629 /* disable irqs */
630 atiixp_write(chip, IER, 0);
631 return 0;
632 }
633
634
635 /*
636 * PCM section
637 */
638
639 /*
640 * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
641 * position. when SG-buffer is implemented, the offset must be calculated
642 * correctly...
643 */
644 static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream)
645 {
646 struct atiixp *chip = snd_pcm_substream_chip(substream);
647 struct snd_pcm_runtime *runtime = substream->runtime;
648 struct atiixp_dma *dma = runtime->private_data;
649 unsigned int curptr;
650 int timeout = 1000;
651
652 while (timeout--) {
653 curptr = readl(chip->remap_addr + dma->ops->dt_cur);
654 if (curptr < dma->buf_addr)
655 continue;
656 curptr -= dma->buf_addr;
657 if (curptr >= dma->buf_bytes)
658 continue;
659 return bytes_to_frames(runtime, curptr);
660 }
661 dev_dbg(chip->card->dev, "invalid DMA pointer read 0x%x (buf=%x)\n",
662 readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr);
663 return 0;
664 }
665
666 /*
667 * XRUN detected, and stop the PCM substream
668 */
669 static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma)
670 {
671 if (! dma->substream || ! dma->running)
672 return;
673 dev_dbg(chip->card->dev, "XRUN detected (DMA %d)\n", dma->ops->type);
674 snd_pcm_stop_xrun(dma->substream);
675 }
676
677 /*
678 * the period ack. update the substream.
679 */
680 static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma)
681 {
682 if (! dma->substream || ! dma->running)
683 return;
684 snd_pcm_period_elapsed(dma->substream);
685 }
686
687 /* set BUS_BUSY interrupt bit if any DMA is running */
688 /* call with spinlock held */
689 static void snd_atiixp_check_bus_busy(struct atiixp *chip)
690 {
691 unsigned int bus_busy;
692 if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN |
693 ATI_REG_CMD_RECEIVE_EN |
694 ATI_REG_CMD_SPDF_OUT_EN))
695 bus_busy = ATI_REG_IER_SET_BUS_BUSY;
696 else
697 bus_busy = 0;
698 atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy);
699 }
700
701 /* common trigger callback
702 * calling the lowlevel callbacks in it
703 */
704 static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
705 {
706 struct atiixp *chip = snd_pcm_substream_chip(substream);
707 struct atiixp_dma *dma = substream->runtime->private_data;
708 int err = 0;
709
710 if (snd_BUG_ON(!dma->ops->enable_transfer ||
711 !dma->ops->flush_dma))
712 return -EINVAL;
713
714 spin_lock(&chip->reg_lock);
715 switch (cmd) {
716 case SNDRV_PCM_TRIGGER_START:
717 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
718 case SNDRV_PCM_TRIGGER_RESUME:
719 if (dma->running && dma->suspended &&
720 cmd == SNDRV_PCM_TRIGGER_RESUME)
721 writel(dma->saved_curptr, chip->remap_addr +
722 dma->ops->dt_cur);
723 dma->ops->enable_transfer(chip, 1);
724 dma->running = 1;
725 dma->suspended = 0;
726 break;
727 case SNDRV_PCM_TRIGGER_STOP:
728 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
729 case SNDRV_PCM_TRIGGER_SUSPEND:
730 dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND;
731 if (dma->running && dma->suspended)
732 dma->saved_curptr = readl(chip->remap_addr +
733 dma->ops->dt_cur);
734 dma->ops->enable_transfer(chip, 0);
735 dma->running = 0;
736 break;
737 default:
738 err = -EINVAL;
739 break;
740 }
741 if (! err) {
742 snd_atiixp_check_bus_busy(chip);
743 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
744 dma->ops->flush_dma(chip);
745 snd_atiixp_check_bus_busy(chip);
746 }
747 }
748 spin_unlock(&chip->reg_lock);
749 return err;
750 }
751
752
753 /*
754 * lowlevel callbacks for each DMA type
755 *
756 * every callback is supposed to be called in chip->reg_lock spinlock
757 */
758
759 /* flush FIFO of analog OUT DMA */
760 static void atiixp_out_flush_dma(struct atiixp *chip)
761 {
762 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH);
763 }
764
765 /* enable/disable analog OUT DMA */
766 static void atiixp_out_enable_dma(struct atiixp *chip, int on)
767 {
768 unsigned int data;
769 data = atiixp_read(chip, CMD);
770 if (on) {
771 if (data & ATI_REG_CMD_OUT_DMA_EN)
772 return;
773 atiixp_out_flush_dma(chip);
774 data |= ATI_REG_CMD_OUT_DMA_EN;
775 } else
776 data &= ~ATI_REG_CMD_OUT_DMA_EN;
777 atiixp_write(chip, CMD, data);
778 }
779
780 /* start/stop transfer over OUT DMA */
781 static void atiixp_out_enable_transfer(struct atiixp *chip, int on)
782 {
783 atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN,
784 on ? ATI_REG_CMD_SEND_EN : 0);
785 }
786
787 /* enable/disable analog IN DMA */
788 static void atiixp_in_enable_dma(struct atiixp *chip, int on)
789 {
790 atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN,
791 on ? ATI_REG_CMD_IN_DMA_EN : 0);
792 }
793
794 /* start/stop analog IN DMA */
795 static void atiixp_in_enable_transfer(struct atiixp *chip, int on)
796 {
797 if (on) {
798 unsigned int data = atiixp_read(chip, CMD);
799 if (! (data & ATI_REG_CMD_RECEIVE_EN)) {
800 data |= ATI_REG_CMD_RECEIVE_EN;
801 #if 0 /* FIXME: this causes the endless loop */
802 /* wait until slot 3/4 are finished */
803 while ((atiixp_read(chip, COUNTER) &
804 ATI_REG_COUNTER_SLOT) != 5)
805 ;
806 #endif
807 atiixp_write(chip, CMD, data);
808 }
809 } else
810 atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0);
811 }
812
813 /* flush FIFO of analog IN DMA */
814 static void atiixp_in_flush_dma(struct atiixp *chip)
815 {
816 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH);
817 }
818
819 /* enable/disable SPDIF OUT DMA */
820 static void atiixp_spdif_enable_dma(struct atiixp *chip, int on)
821 {
822 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN,
823 on ? ATI_REG_CMD_SPDF_DMA_EN : 0);
824 }
825
826 /* start/stop SPDIF OUT DMA */
827 static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on)
828 {
829 unsigned int data;
830 data = atiixp_read(chip, CMD);
831 if (on)
832 data |= ATI_REG_CMD_SPDF_OUT_EN;
833 else
834 data &= ~ATI_REG_CMD_SPDF_OUT_EN;
835 atiixp_write(chip, CMD, data);
836 }
837
838 /* flush FIFO of SPDIF OUT DMA */
839 static void atiixp_spdif_flush_dma(struct atiixp *chip)
840 {
841 int timeout;
842
843 /* DMA off, transfer on */
844 atiixp_spdif_enable_dma(chip, 0);
845 atiixp_spdif_enable_transfer(chip, 1);
846
847 timeout = 100;
848 do {
849 if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED))
850 break;
851 udelay(1);
852 } while (timeout-- > 0);
853
854 atiixp_spdif_enable_transfer(chip, 0);
855 }
856
857 /* set up slots and formats for SPDIF OUT */
858 static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream)
859 {
860 struct atiixp *chip = snd_pcm_substream_chip(substream);
861
862 spin_lock_irq(&chip->reg_lock);
863 if (chip->spdif_over_aclink) {
864 unsigned int data;
865 /* enable slots 10/11 */
866 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK,
867 ATI_REG_CMD_SPDF_CONFIG_01);
868 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
869 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
870 ATI_REG_OUT_DMA_SLOT_BIT(11);
871 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
872 atiixp_write(chip, OUT_DMA_SLOT, data);
873 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
874 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
875 ATI_REG_CMD_INTERLEAVE_OUT : 0);
876 } else {
877 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0);
878 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0);
879 }
880 spin_unlock_irq(&chip->reg_lock);
881 return 0;
882 }
883
884 /* set up slots and formats for analog OUT */
885 static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream)
886 {
887 struct atiixp *chip = snd_pcm_substream_chip(substream);
888 unsigned int data;
889
890 spin_lock_irq(&chip->reg_lock);
891 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
892 switch (substream->runtime->channels) {
893 case 8:
894 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
895 ATI_REG_OUT_DMA_SLOT_BIT(11);
896 fallthrough;
897 case 6:
898 data |= ATI_REG_OUT_DMA_SLOT_BIT(7) |
899 ATI_REG_OUT_DMA_SLOT_BIT(8);
900 fallthrough;
901 case 4:
902 data |= ATI_REG_OUT_DMA_SLOT_BIT(6) |
903 ATI_REG_OUT_DMA_SLOT_BIT(9);
904 fallthrough;
905 default:
906 data |= ATI_REG_OUT_DMA_SLOT_BIT(3) |
907 ATI_REG_OUT_DMA_SLOT_BIT(4);
908 break;
909 }
910
911 /* set output threshold */
912 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
913 atiixp_write(chip, OUT_DMA_SLOT, data);
914
915 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
916 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
917 ATI_REG_CMD_INTERLEAVE_OUT : 0);
918
919 /*
920 * enable 6 channel re-ordering bit if needed
921 */
922 atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN,
923 substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0);
924
925 spin_unlock_irq(&chip->reg_lock);
926 return 0;
927 }
928
929 /* set up slots and formats for analog IN */
930 static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream)
931 {
932 struct atiixp *chip = snd_pcm_substream_chip(substream);
933
934 spin_lock_irq(&chip->reg_lock);
935 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN,
936 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
937 ATI_REG_CMD_INTERLEAVE_IN : 0);
938 spin_unlock_irq(&chip->reg_lock);
939 return 0;
940 }
941
942 /*
943 * hw_params - allocate the buffer and set up buffer descriptors
944 */
945 static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream,
946 struct snd_pcm_hw_params *hw_params)
947 {
948 struct atiixp *chip = snd_pcm_substream_chip(substream);
949 struct atiixp_dma *dma = substream->runtime->private_data;
950 int err;
951
952 dma->buf_addr = substream->runtime->dma_addr;
953 dma->buf_bytes = params_buffer_bytes(hw_params);
954
955 err = atiixp_build_dma_packets(chip, dma, substream,
956 params_periods(hw_params),
957 params_period_bytes(hw_params));
958 if (err < 0)
959 return err;
960
961 if (dma->ac97_pcm_type >= 0) {
962 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
963 /* PCM is bound to AC97 codec(s)
964 * set up the AC97 codecs
965 */
966 if (dma->pcm_open_flag) {
967 snd_ac97_pcm_close(pcm);
968 dma->pcm_open_flag = 0;
969 }
970 err = snd_ac97_pcm_open(pcm, params_rate(hw_params),
971 params_channels(hw_params),
972 pcm->r[0].slots);
973 if (err >= 0)
974 dma->pcm_open_flag = 1;
975 }
976
977 return err;
978 }
979
980 static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream)
981 {
982 struct atiixp *chip = snd_pcm_substream_chip(substream);
983 struct atiixp_dma *dma = substream->runtime->private_data;
984
985 if (dma->pcm_open_flag) {
986 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
987 snd_ac97_pcm_close(pcm);
988 dma->pcm_open_flag = 0;
989 }
990 atiixp_clear_dma_packets(chip, dma, substream);
991 return 0;
992 }
993
994
995 /*
996 * pcm hardware definition, identical for all DMA types
997 */
998 static const struct snd_pcm_hardware snd_atiixp_pcm_hw =
999 {
1000 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1001 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1002 SNDRV_PCM_INFO_PAUSE |
1003 SNDRV_PCM_INFO_RESUME |
1004 SNDRV_PCM_INFO_MMAP_VALID),
1005 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1006 .rates = SNDRV_PCM_RATE_48000,
1007 .rate_min = 48000,
1008 .rate_max = 48000,
1009 .channels_min = 2,
1010 .channels_max = 2,
1011 .buffer_bytes_max = 256 * 1024,
1012 .period_bytes_min = 32,
1013 .period_bytes_max = 128 * 1024,
1014 .periods_min = 2,
1015 .periods_max = ATI_MAX_DESCRIPTORS,
1016 };
1017
1018 static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream,
1019 struct atiixp_dma *dma, int pcm_type)
1020 {
1021 struct atiixp *chip = snd_pcm_substream_chip(substream);
1022 struct snd_pcm_runtime *runtime = substream->runtime;
1023 int err;
1024
1025 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1026 return -EINVAL;
1027
1028 if (dma->opened)
1029 return -EBUSY;
1030 dma->substream = substream;
1031 runtime->hw = snd_atiixp_pcm_hw;
1032 dma->ac97_pcm_type = pcm_type;
1033 if (pcm_type >= 0) {
1034 runtime->hw.rates = chip->pcms[pcm_type]->rates;
1035 snd_pcm_limit_hw_rates(runtime);
1036 } else {
1037 /* direct SPDIF */
1038 runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
1039 }
1040 err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1041 if (err < 0)
1042 return err;
1043 runtime->private_data = dma;
1044
1045 /* enable DMA bits */
1046 spin_lock_irq(&chip->reg_lock);
1047 dma->ops->enable_dma(chip, 1);
1048 spin_unlock_irq(&chip->reg_lock);
1049 dma->opened = 1;
1050
1051 return 0;
1052 }
1053
1054 static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream,
1055 struct atiixp_dma *dma)
1056 {
1057 struct atiixp *chip = snd_pcm_substream_chip(substream);
1058 /* disable DMA bits */
1059 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1060 return -EINVAL;
1061 spin_lock_irq(&chip->reg_lock);
1062 dma->ops->enable_dma(chip, 0);
1063 spin_unlock_irq(&chip->reg_lock);
1064 dma->substream = NULL;
1065 dma->opened = 0;
1066 return 0;
1067 }
1068
1069 /*
1070 */
1071 static int snd_atiixp_playback_open(struct snd_pcm_substream *substream)
1072 {
1073 struct atiixp *chip = snd_pcm_substream_chip(substream);
1074 int err;
1075
1076 mutex_lock(&chip->open_mutex);
1077 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
1078 mutex_unlock(&chip->open_mutex);
1079 if (err < 0)
1080 return err;
1081 substream->runtime->hw.channels_max = chip->max_channels;
1082 if (chip->max_channels > 2)
1083 /* channels must be even */
1084 snd_pcm_hw_constraint_step(substream->runtime, 0,
1085 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1086 return 0;
1087 }
1088
1089 static int snd_atiixp_playback_close(struct snd_pcm_substream *substream)
1090 {
1091 struct atiixp *chip = snd_pcm_substream_chip(substream);
1092 int err;
1093 mutex_lock(&chip->open_mutex);
1094 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1095 mutex_unlock(&chip->open_mutex);
1096 return err;
1097 }
1098
1099 static int snd_atiixp_capture_open(struct snd_pcm_substream *substream)
1100 {
1101 struct atiixp *chip = snd_pcm_substream_chip(substream);
1102 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
1103 }
1104
1105 static int snd_atiixp_capture_close(struct snd_pcm_substream *substream)
1106 {
1107 struct atiixp *chip = snd_pcm_substream_chip(substream);
1108 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
1109 }
1110
1111 static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream)
1112 {
1113 struct atiixp *chip = snd_pcm_substream_chip(substream);
1114 int err;
1115 mutex_lock(&chip->open_mutex);
1116 if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */
1117 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2);
1118 else
1119 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1);
1120 mutex_unlock(&chip->open_mutex);
1121 return err;
1122 }
1123
1124 static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream)
1125 {
1126 struct atiixp *chip = snd_pcm_substream_chip(substream);
1127 int err;
1128 mutex_lock(&chip->open_mutex);
1129 if (chip->spdif_over_aclink)
1130 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1131 else
1132 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]);
1133 mutex_unlock(&chip->open_mutex);
1134 return err;
1135 }
1136
1137 /* AC97 playback */
1138 static const struct snd_pcm_ops snd_atiixp_playback_ops = {
1139 .open = snd_atiixp_playback_open,
1140 .close = snd_atiixp_playback_close,
1141 .hw_params = snd_atiixp_pcm_hw_params,
1142 .hw_free = snd_atiixp_pcm_hw_free,
1143 .prepare = snd_atiixp_playback_prepare,
1144 .trigger = snd_atiixp_pcm_trigger,
1145 .pointer = snd_atiixp_pcm_pointer,
1146 };
1147
1148 /* AC97 capture */
1149 static const struct snd_pcm_ops snd_atiixp_capture_ops = {
1150 .open = snd_atiixp_capture_open,
1151 .close = snd_atiixp_capture_close,
1152 .hw_params = snd_atiixp_pcm_hw_params,
1153 .hw_free = snd_atiixp_pcm_hw_free,
1154 .prepare = snd_atiixp_capture_prepare,
1155 .trigger = snd_atiixp_pcm_trigger,
1156 .pointer = snd_atiixp_pcm_pointer,
1157 };
1158
1159 /* SPDIF playback */
1160 static const struct snd_pcm_ops snd_atiixp_spdif_ops = {
1161 .open = snd_atiixp_spdif_open,
1162 .close = snd_atiixp_spdif_close,
1163 .hw_params = snd_atiixp_pcm_hw_params,
1164 .hw_free = snd_atiixp_pcm_hw_free,
1165 .prepare = snd_atiixp_spdif_prepare,
1166 .trigger = snd_atiixp_pcm_trigger,
1167 .pointer = snd_atiixp_pcm_pointer,
1168 };
1169
1170 static const struct ac97_pcm atiixp_pcm_defs[] = {
1171 /* front PCM */
1172 {
1173 .exclusive = 1,
1174 .r = { {
1175 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1176 (1 << AC97_SLOT_PCM_RIGHT) |
1177 (1 << AC97_SLOT_PCM_CENTER) |
1178 (1 << AC97_SLOT_PCM_SLEFT) |
1179 (1 << AC97_SLOT_PCM_SRIGHT) |
1180 (1 << AC97_SLOT_LFE)
1181 }
1182 }
1183 },
1184 /* PCM IN #1 */
1185 {
1186 .stream = 1,
1187 .exclusive = 1,
1188 .r = { {
1189 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1190 (1 << AC97_SLOT_PCM_RIGHT)
1191 }
1192 }
1193 },
1194 /* S/PDIF OUT (optional) */
1195 {
1196 .exclusive = 1,
1197 .spdif = 1,
1198 .r = { {
1199 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1200 (1 << AC97_SLOT_SPDIF_RIGHT2)
1201 }
1202 }
1203 },
1204 };
1205
1206 static const struct atiixp_dma_ops snd_atiixp_playback_dma_ops = {
1207 .type = ATI_DMA_PLAYBACK,
1208 .llp_offset = ATI_REG_OUT_DMA_LINKPTR,
1209 .dt_cur = ATI_REG_OUT_DMA_DT_CUR,
1210 .enable_dma = atiixp_out_enable_dma,
1211 .enable_transfer = atiixp_out_enable_transfer,
1212 .flush_dma = atiixp_out_flush_dma,
1213 };
1214
1215 static const struct atiixp_dma_ops snd_atiixp_capture_dma_ops = {
1216 .type = ATI_DMA_CAPTURE,
1217 .llp_offset = ATI_REG_IN_DMA_LINKPTR,
1218 .dt_cur = ATI_REG_IN_DMA_DT_CUR,
1219 .enable_dma = atiixp_in_enable_dma,
1220 .enable_transfer = atiixp_in_enable_transfer,
1221 .flush_dma = atiixp_in_flush_dma,
1222 };
1223
1224 static const struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = {
1225 .type = ATI_DMA_SPDIF,
1226 .llp_offset = ATI_REG_SPDF_DMA_LINKPTR,
1227 .dt_cur = ATI_REG_SPDF_DMA_DT_CUR,
1228 .enable_dma = atiixp_spdif_enable_dma,
1229 .enable_transfer = atiixp_spdif_enable_transfer,
1230 .flush_dma = atiixp_spdif_flush_dma,
1231 };
1232
1233
1234 static int snd_atiixp_pcm_new(struct atiixp *chip)
1235 {
1236 struct snd_pcm *pcm;
1237 struct snd_pcm_chmap *chmap;
1238 struct snd_ac97_bus *pbus = chip->ac97_bus;
1239 int err, i, num_pcms;
1240
1241 /* initialize constants */
1242 chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
1243 chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
1244 if (! chip->spdif_over_aclink)
1245 chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops;
1246
1247 /* assign AC97 pcm */
1248 if (chip->spdif_over_aclink)
1249 num_pcms = 3;
1250 else
1251 num_pcms = 2;
1252 err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs);
1253 if (err < 0)
1254 return err;
1255 for (i = 0; i < num_pcms; i++)
1256 chip->pcms[i] = &pbus->pcms[i];
1257
1258 chip->max_channels = 2;
1259 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
1260 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE))
1261 chip->max_channels = 6;
1262 else
1263 chip->max_channels = 4;
1264 }
1265
1266 /* PCM #0: analog I/O */
1267 err = snd_pcm_new(chip->card, "ATI IXP AC97",
1268 ATI_PCMDEV_ANALOG, 1, 1, &pcm);
1269 if (err < 0)
1270 return err;
1271 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
1272 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
1273 pcm->private_data = chip;
1274 strcpy(pcm->name, "ATI IXP AC97");
1275 chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
1276
1277 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1278 &chip->pci->dev, 64*1024, 128*1024);
1279
1280 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1281 snd_pcm_alt_chmaps, chip->max_channels, 0,
1282 &chmap);
1283 if (err < 0)
1284 return err;
1285 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1286 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1287
1288 /* no SPDIF support on codec? */
1289 if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates)
1290 return 0;
1291
1292 /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */
1293 if (chip->pcms[ATI_PCM_SPDIF])
1294 chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000;
1295
1296 /* PCM #1: spdif playback */
1297 err = snd_pcm_new(chip->card, "ATI IXP IEC958",
1298 ATI_PCMDEV_DIGITAL, 1, 0, &pcm);
1299 if (err < 0)
1300 return err;
1301 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops);
1302 pcm->private_data = chip;
1303 if (chip->spdif_over_aclink)
1304 strcpy(pcm->name, "ATI IXP IEC958 (AC97)");
1305 else
1306 strcpy(pcm->name, "ATI IXP IEC958 (Direct)");
1307 chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm;
1308
1309 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1310 &chip->pci->dev, 64*1024, 128*1024);
1311
1312 /* pre-select AC97 SPDIF slots 10/11 */
1313 for (i = 0; i < NUM_ATI_CODECS; i++) {
1314 if (chip->ac97[i])
1315 snd_ac97_update_bits(chip->ac97[i],
1316 AC97_EXTENDED_STATUS,
1317 0x03 << 4, 0x03 << 4);
1318 }
1319
1320 return 0;
1321 }
1322
1323
1324
1325 /*
1326 * interrupt handler
1327 */
1328 static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id)
1329 {
1330 struct atiixp *chip = dev_id;
1331 unsigned int status;
1332
1333 status = atiixp_read(chip, ISR);
1334
1335 if (! status)
1336 return IRQ_NONE;
1337
1338 /* process audio DMA */
1339 if (status & ATI_REG_ISR_OUT_XRUN)
1340 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1341 else if (status & ATI_REG_ISR_OUT_STATUS)
1342 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1343 if (status & ATI_REG_ISR_IN_XRUN)
1344 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1345 else if (status & ATI_REG_ISR_IN_STATUS)
1346 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1347 if (! chip->spdif_over_aclink) {
1348 if (status & ATI_REG_ISR_SPDF_XRUN)
1349 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1350 else if (status & ATI_REG_ISR_SPDF_STATUS)
1351 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1352 }
1353
1354 /* for codec detection */
1355 if (status & CODEC_CHECK_BITS) {
1356 unsigned int detected;
1357 detected = status & CODEC_CHECK_BITS;
1358 spin_lock(&chip->reg_lock);
1359 chip->codec_not_ready_bits |= detected;
1360 atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
1361 spin_unlock(&chip->reg_lock);
1362 }
1363
1364 /* ack */
1365 atiixp_write(chip, ISR, status);
1366
1367 return IRQ_HANDLED;
1368 }
1369
1370
1371 /*
1372 * ac97 mixer section
1373 */
1374
1375 static const struct ac97_quirk ac97_quirks[] = {
1376 {
1377 .subvendor = 0x103c,
1378 .subdevice = 0x006b,
1379 .name = "HP Pavilion ZV5030US",
1380 .type = AC97_TUNE_MUTE_LED
1381 },
1382 {
1383 .subvendor = 0x103c,
1384 .subdevice = 0x308b,
1385 .name = "HP nx6125",
1386 .type = AC97_TUNE_MUTE_LED
1387 },
1388 {
1389 .subvendor = 0x103c,
1390 .subdevice = 0x3091,
1391 .name = "unknown HP",
1392 .type = AC97_TUNE_MUTE_LED
1393 },
1394 { } /* terminator */
1395 };
1396
1397 static int snd_atiixp_mixer_new(struct atiixp *chip, int clock,
1398 const char *quirk_override)
1399 {
1400 struct snd_ac97_bus *pbus;
1401 struct snd_ac97_template ac97;
1402 int i, err;
1403 int codec_count;
1404 static const struct snd_ac97_bus_ops ops = {
1405 .write = snd_atiixp_ac97_write,
1406 .read = snd_atiixp_ac97_read,
1407 };
1408 static const unsigned int codec_skip[NUM_ATI_CODECS] = {
1409 ATI_REG_ISR_CODEC0_NOT_READY,
1410 ATI_REG_ISR_CODEC1_NOT_READY,
1411 ATI_REG_ISR_CODEC2_NOT_READY,
1412 };
1413
1414 if (snd_atiixp_codec_detect(chip) < 0)
1415 return -ENXIO;
1416
1417 err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus);
1418 if (err < 0)
1419 return err;
1420 pbus->clock = clock;
1421 chip->ac97_bus = pbus;
1422
1423 codec_count = 0;
1424 for (i = 0; i < NUM_ATI_CODECS; i++) {
1425 if (chip->codec_not_ready_bits & codec_skip[i])
1426 continue;
1427 memset(&ac97, 0, sizeof(ac97));
1428 ac97.private_data = chip;
1429 ac97.pci = chip->pci;
1430 ac97.num = i;
1431 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
1432 if (! chip->spdif_over_aclink)
1433 ac97.scaps |= AC97_SCAP_NO_SPDIF;
1434 err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i]);
1435 if (err < 0) {
1436 chip->ac97[i] = NULL; /* to be sure */
1437 dev_dbg(chip->card->dev,
1438 "codec %d not available for audio\n", i);
1439 continue;
1440 }
1441 codec_count++;
1442 }
1443
1444 if (! codec_count) {
1445 dev_err(chip->card->dev, "no codec available\n");
1446 return -ENODEV;
1447 }
1448
1449 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
1450
1451 return 0;
1452 }
1453
1454
1455 /*
1456 * power management
1457 */
1458 static int snd_atiixp_suspend(struct device *dev)
1459 {
1460 struct snd_card *card = dev_get_drvdata(dev);
1461 struct atiixp *chip = card->private_data;
1462 int i;
1463
1464 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1465 for (i = 0; i < NUM_ATI_CODECS; i++)
1466 snd_ac97_suspend(chip->ac97[i]);
1467 snd_atiixp_aclink_down(chip);
1468 snd_atiixp_chip_stop(chip);
1469 return 0;
1470 }
1471
1472 static int snd_atiixp_resume(struct device *dev)
1473 {
1474 struct snd_card *card = dev_get_drvdata(dev);
1475 struct atiixp *chip = card->private_data;
1476 int i;
1477
1478 snd_atiixp_aclink_reset(chip);
1479 snd_atiixp_chip_start(chip);
1480
1481 for (i = 0; i < NUM_ATI_CODECS; i++)
1482 snd_ac97_resume(chip->ac97[i]);
1483
1484 for (i = 0; i < NUM_ATI_PCMDEVS; i++)
1485 if (chip->pcmdevs[i]) {
1486 struct atiixp_dma *dma = &chip->dmas[i];
1487 if (dma->substream && dma->suspended) {
1488 dma->ops->enable_dma(chip, 1);
1489 dma->substream->ops->prepare(dma->substream);
1490 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
1491 chip->remap_addr + dma->ops->llp_offset);
1492 }
1493 }
1494
1495 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1496 return 0;
1497 }
1498
1499 static DEFINE_SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume);
1500
1501 /*
1502 * proc interface for register dump
1503 */
1504
1505 static void snd_atiixp_proc_read(struct snd_info_entry *entry,
1506 struct snd_info_buffer *buffer)
1507 {
1508 struct atiixp *chip = entry->private_data;
1509 int i;
1510
1511 for (i = 0; i < 256; i += 4)
1512 snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
1513 }
1514
1515 static void snd_atiixp_proc_init(struct atiixp *chip)
1516 {
1517 snd_card_ro_proc_new(chip->card, "atiixp", chip, snd_atiixp_proc_read);
1518 }
1519
1520
1521 /*
1522 * destructor
1523 */
1524
1525 static void snd_atiixp_free(struct snd_card *card)
1526 {
1527 snd_atiixp_chip_stop(card->private_data);
1528 }
1529
1530 /*
1531 * constructor for chip instance
1532 */
1533 static int snd_atiixp_init(struct snd_card *card, struct pci_dev *pci)
1534 {
1535 struct atiixp *chip = card->private_data;
1536 int err;
1537
1538 err = pcim_enable_device(pci);
1539 if (err < 0)
1540 return err;
1541
1542 spin_lock_init(&chip->reg_lock);
1543 mutex_init(&chip->open_mutex);
1544 chip->card = card;
1545 chip->pci = pci;
1546 chip->irq = -1;
1547 err = pcim_iomap_regions(pci, 1 << 0, "ATI IXP AC97");
1548 if (err < 0)
1549 return err;
1550 chip->addr = pci_resource_start(pci, 0);
1551 chip->remap_addr = pcim_iomap_table(pci)[0];
1552
1553 if (devm_request_irq(&pci->dev, pci->irq, snd_atiixp_interrupt,
1554 IRQF_SHARED, KBUILD_MODNAME, chip)) {
1555 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1556 return -EBUSY;
1557 }
1558 chip->irq = pci->irq;
1559 card->sync_irq = chip->irq;
1560 card->private_free = snd_atiixp_free;
1561 pci_set_master(pci);
1562
1563 return 0;
1564 }
1565
1566
1567 static int __snd_atiixp_probe(struct pci_dev *pci,
1568 const struct pci_device_id *pci_id)
1569 {
1570 struct snd_card *card;
1571 struct atiixp *chip;
1572 int err;
1573
1574 err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
1575 sizeof(*chip), &card);
1576 if (err < 0)
1577 return err;
1578 chip = card->private_data;
1579
1580 strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA");
1581 strcpy(card->shortname, "ATI IXP");
1582 err = snd_atiixp_init(card, pci);
1583 if (err < 0)
1584 return err;
1585
1586 err = snd_atiixp_aclink_reset(chip);
1587 if (err < 0)
1588 return err;
1589
1590 chip->spdif_over_aclink = spdif_aclink;
1591
1592 err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk);
1593 if (err < 0)
1594 return err;
1595
1596 err = snd_atiixp_pcm_new(chip);
1597 if (err < 0)
1598 return err;
1599
1600 snd_atiixp_proc_init(chip);
1601
1602 snd_atiixp_chip_start(chip);
1603
1604 snprintf(card->longname, sizeof(card->longname),
1605 "%s rev %x with %s at %#lx, irq %i", card->shortname,
1606 pci->revision,
1607 chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?",
1608 chip->addr, chip->irq);
1609
1610 err = snd_card_register(card);
1611 if (err < 0)
1612 return err;
1613
1614 pci_set_drvdata(pci, card);
1615 return 0;
1616 }
1617
1618 static int snd_atiixp_probe(struct pci_dev *pci,
1619 const struct pci_device_id *pci_id)
1620 {
1621 return snd_card_free_on_error(&pci->dev, __snd_atiixp_probe(pci, pci_id));
1622 }
1623
1624 static struct pci_driver atiixp_driver = {
1625 .name = KBUILD_MODNAME,
1626 .id_table = snd_atiixp_ids,
1627 .probe = snd_atiixp_probe,
1628 .driver = {
1629 .pm = &snd_atiixp_pm,
1630 },
1631 };
1632
1633 module_pci_driver(atiixp_driver);
Linux Kernel