sound/soc/amd/acp/amd.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
   2 /*
   3  * This file is provided under a dual BSD/GPLv2 license. When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
   7  *
   8  * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
   9  */
  10
  11 #ifndef __AMD_ACP_H
  12 #define __AMD_ACP_H
  13
  14 #include <sound/pcm.h>
  15 #include <sound/soc.h>
  16 #include <sound/soc-acpi.h>
  17 #include <sound/soc-dai.h>
  18
  19 #include "acp_common.h"
  20 #include "chip_offset_byte.h"
  21
  22 #define DMIC_INSTANCE                   0x00
  23 #define I2S_SP_INSTANCE                 0x01
  24 #define I2S_BT_INSTANCE                 0x02
  25 #define I2S_HS_INSTANCE                 0x03
  26
  27 #define MEM_WINDOW_START                0x4080000
  28
  29 #define ACP_I2S_REG_START               0x1242400
  30 #define ACP_I2S_REG_END                 0x1242810
  31 #define ACP3x_I2STDM_REG_START          0x1242400
  32 #define ACP3x_I2STDM_REG_END            0x1242410
  33 #define ACP3x_BT_TDM_REG_START          0x1242800
  34 #define ACP3x_BT_TDM_REG_END            0x1242810
  35
  36 #define THRESHOLD(bit, base)    ((bit) + (base))
  37 #define I2S_RX_THRESHOLD(base)  THRESHOLD(7, base)
  38 #define I2S_TX_THRESHOLD(base)  THRESHOLD(8, base)
  39 #define BT_TX_THRESHOLD(base)   THRESHOLD(6, base)
  40 #define BT_RX_THRESHOLD(base)   THRESHOLD(5, base)
  41 #define HS_TX_THRESHOLD(base)   THRESHOLD(4, base)
  42 #define HS_RX_THRESHOLD(base)   THRESHOLD(3, base)
  43
  44 #define ACP_SRAM_SP_PB_PTE_OFFSET       0x0
  45 #define ACP_SRAM_SP_CP_PTE_OFFSET       0x100
  46 #define ACP_SRAM_BT_PB_PTE_OFFSET       0x200
  47 #define ACP_SRAM_BT_CP_PTE_OFFSET       0x300
  48 #define ACP_SRAM_PDM_PTE_OFFSET         0x400
  49 #define ACP_SRAM_HS_PB_PTE_OFFSET       0x500
  50 #define ACP_SRAM_HS_CP_PTE_OFFSET       0x600
  51 #define PAGE_SIZE_4K_ENABLE             0x2
  52
  53 #define I2S_SP_TX_MEM_WINDOW_START      0x4000000
  54 #define I2S_SP_RX_MEM_WINDOW_START      0x4020000
  55 #define I2S_BT_TX_MEM_WINDOW_START      0x4040000
  56 #define I2S_BT_RX_MEM_WINDOW_START      0x4060000
  57 #define I2S_HS_TX_MEM_WINDOW_START      0x40A0000
  58 #define I2S_HS_RX_MEM_WINDOW_START      0x40C0000
  59
  60 #define ACP7x_I2S_SP_TX_MEM_WINDOW_START        0x4000000
  61 #define ACP7x_I2S_SP_RX_MEM_WINDOW_START        0x4200000
  62 #define ACP7x_I2S_BT_TX_MEM_WINDOW_START        0x4400000
  63 #define ACP7x_I2S_BT_RX_MEM_WINDOW_START        0x4600000
  64 #define ACP7x_I2S_HS_TX_MEM_WINDOW_START        0x4800000
  65 #define ACP7x_I2S_HS_RX_MEM_WINDOW_START        0x4A00000
  66 #define ACP7x_DMIC_MEM_WINDOW_START                     0x4C00000
  67
  68 #define SP_PB_FIFO_ADDR_OFFSET          0x500
  69 #define SP_CAPT_FIFO_ADDR_OFFSET        0x700
  70 #define BT_PB_FIFO_ADDR_OFFSET          0x900
  71 #define BT_CAPT_FIFO_ADDR_OFFSET        0xB00
  72 #define HS_PB_FIFO_ADDR_OFFSET          0xD00
  73 #define HS_CAPT_FIFO_ADDR_OFFSET        0xF00
  74 #define PLAYBACK_MIN_NUM_PERIODS        2
  75 #define PLAYBACK_MAX_NUM_PERIODS        8
  76 #define PLAYBACK_MAX_PERIOD_SIZE        8192
  77 #define PLAYBACK_MIN_PERIOD_SIZE        1024
  78 #define CAPTURE_MIN_NUM_PERIODS         2
  79 #define CAPTURE_MAX_NUM_PERIODS         8
  80 #define CAPTURE_MAX_PERIOD_SIZE         8192
  81 #define CAPTURE_MIN_PERIOD_SIZE         1024
  82
  83 #define MAX_BUFFER                      65536
  84 #define MIN_BUFFER                      MAX_BUFFER
  85 #define FIFO_SIZE                       0x100
  86 #define DMA_SIZE                        0x40
  87 #define FRM_LEN                         0x100
  88
  89 #define ACP3x_ITER_IRER_SAMP_LEN_MASK   0x38
  90
  91 #define ACP_MAX_STREAM                  8
  92
  93 #define TDM_ENABLE      1
  94 #define TDM_DISABLE     0
  95
  96 #define SLOT_WIDTH_8    0x8
  97 #define SLOT_WIDTH_16   0x10
  98 #define SLOT_WIDTH_24   0x18
  99 #define SLOT_WIDTH_32   0x20
 100
 101 #define ACP6X_PGFSM_CONTROL                     0x1024
 102 #define ACP6X_PGFSM_STATUS                      0x1028
 103
 104 #define ACP63_PGFSM_CONTROL                     ACP6X_PGFSM_CONTROL
 105 #define ACP63_PGFSM_STATUS                      ACP6X_PGFSM_STATUS
 106
 107 #define ACP70_PGFSM_CONTROL                     ACP6X_PGFSM_CONTROL
 108 #define ACP70_PGFSM_STATUS                      ACP6X_PGFSM_STATUS
 109
 110 #define ACP_ZSC_DSP_CTRL                        0x0001014
 111 #define ACP_ZSC_STS                             0x0001018
 112 #define ACP_SOFT_RST_DONE_MASK  0x00010001
 113
 114 #define ACP_PGFSM_CNTL_POWER_ON_MASK            0xffffffff
 115 #define ACP_PGFSM_CNTL_POWER_OFF_MASK           0x00
 116 #define ACP_PGFSM_STATUS_MASK                   0x03
 117 #define ACP_POWERED_ON                          0x00
 118 #define ACP_POWER_ON_IN_PROGRESS                0x01
 119 #define ACP_POWERED_OFF                         0x02
 120 #define ACP_POWER_OFF_IN_PROGRESS               0x03
 121
 122 #define ACP_ERROR_MASK                          0x20000000
 123 #define ACP_EXT_INTR_STAT_CLEAR_MASK            0xffffffff
 124
 125 #define ACP_TIMEOUT             500
 126 #define DELAY_US                5
 127 #define ACP_SUSPEND_DELAY_MS   2000
 128
 129 #define PDM_DMA_STAT            0x10
 130 #define PDM_DMA_INTR_MASK       0x10000
 131 #define PDM_DEC_64              0x2
 132 #define PDM_CLK_FREQ_MASK       0x07
 133 #define PDM_MISC_CTRL_MASK      0x10
 134 #define PDM_ENABLE              0x01
 135 #define PDM_DISABLE             0x00
 136 #define DMA_EN_MASK             0x02
 137 #define DELAY_US                5
 138 #define PDM_TIMEOUT             1000
 139 #define ACP_REGION2_OFFSET      0x02000000
 140
 141 struct acp_chip_info {
 142         char *name;             /* Platform name */
 143         unsigned int acp_rev;   /* ACP Revision id */
 144         void __iomem *base;     /* ACP memory PCI base */
 145         struct platform_device *chip_pdev;
 146         unsigned int flag;      /* Distinguish b/w Legacy or Only PDM */
 147         bool is_pdm_dev;        /* flag set to true when ACP PDM controller exists */
 148         bool is_pdm_config;     /* flag set to true when PDM configuration is selected from BIOS */
 149         bool is_i2s_config;     /* flag set to true when I2S configuration is selected from BIOS */
 150 };
 151
 152 struct acp_stream {
 153         struct list_head list;
 154         struct snd_pcm_substream *substream;
 155         int irq_bit;
 156         int dai_id;
 157         int id;
 158         int dir;
 159         u64 bytescount;
 160         u32 reg_offset;
 161         u32 pte_offset;
 162         u32 fifo_offset;
 163 };
 164
 165 struct acp_resource {
 166         int offset;
 167         int no_of_ctrls;
 168         int irqp_used;
 169         bool soc_mclk;
 170         u32 irq_reg_offset;
 171         u64 scratch_reg_offset;
 172         u64 sram_pte_offset;
 173 };
 174
 175 struct acp_dev_data {
 176         char *name;
 177         struct device *dev;
 178         void __iomem *acp_base;
 179         unsigned int i2s_irq;
 180         unsigned int acp_rev;   /* ACP Revision id */
 181
 182         bool tdm_mode;
 183         bool is_i2s_config;
 184         /* SOC specific dais */
 185         struct snd_soc_dai_driver *dai_driver;
 186         int num_dai;
 187
 188         struct list_head stream_list;
 189         spinlock_t acp_lock;
 190
 191         struct snd_soc_acpi_mach *machines;
 192         struct platform_device *mach_dev;
 193
 194         u32 bclk_div;
 195         u32 lrclk_div;
 196
 197         struct acp_resource *rsrc;
 198         u32 ch_mask;
 199         u32 tdm_tx_fmt[3];
 200         u32 tdm_rx_fmt[3];
 201         u32 xfer_tx_resolution[3];
 202         u32 xfer_rx_resolution[3];
 203         unsigned int flag;
 204 };
 205
 206 enum acp_config {
 207         ACP_CONFIG_0 = 0,
 208         ACP_CONFIG_1,
 209         ACP_CONFIG_2,
 210         ACP_CONFIG_3,
 211         ACP_CONFIG_4,
 212         ACP_CONFIG_5,
 213         ACP_CONFIG_6,
 214         ACP_CONFIG_7,
 215         ACP_CONFIG_8,
 216         ACP_CONFIG_9,
 217         ACP_CONFIG_10,
 218         ACP_CONFIG_11,
 219         ACP_CONFIG_12,
 220         ACP_CONFIG_13,
 221         ACP_CONFIG_14,
 222         ACP_CONFIG_15,
 223         ACP_CONFIG_16,
 224         ACP_CONFIG_17,
 225         ACP_CONFIG_18,
 226         ACP_CONFIG_19,
 227         ACP_CONFIG_20,
 228 };
 229
 230 extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
 231 extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
 232
 233 int acp_platform_register(struct device *dev);
 234 int acp_platform_unregister(struct device *dev);
 235
 236 int acp_machine_select(struct acp_dev_data *adata);
 237
 238 int smn_read(struct pci_dev *dev, u32 smn_addr);
 239 int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data);
 240
 241 int acp_init(struct acp_chip_info *chip);
 242 int acp_deinit(struct acp_chip_info *chip);
 243 void acp_enable_interrupts(struct acp_dev_data *adata);
 244 void acp_disable_interrupts(struct acp_dev_data *adata);
 245 /* Machine configuration */
 246 int snd_amd_acp_find_config(struct pci_dev *pci);
 247
 248 void config_pte_for_stream(struct acp_dev_data *adata, struct acp_stream *stream);
 249 void config_acp_dma(struct acp_dev_data *adata, struct acp_stream *stream, int size);
 250 void restore_acp_pdm_params(struct snd_pcm_substream *substream,
 251                             struct acp_dev_data *adata);
 252
 253 int restore_acp_i2s_params(struct snd_pcm_substream *substream,
 254                            struct acp_dev_data *adata, struct acp_stream *stream);
 255
 256 void check_acp_config(struct pci_dev *pci, struct acp_chip_info *chip);
 257
 258 static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int direction)
 259 {
 260         u64 byte_count = 0, low = 0, high = 0;
 261
 262         if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
 263                 switch (dai_id) {
 264                 case I2S_BT_INSTANCE:
 265                         high = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_HIGH(adata));
 266                         low = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_LOW(adata));
 267                         break;
 268                 case I2S_SP_INSTANCE:
 269                         high = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH(adata));
 270                         low = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_LOW(adata));
 271                         break;
 272                 case I2S_HS_INSTANCE:
 273                         high = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_HIGH);
 274                         low = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_LOW);
 275                         break;
 276                 default:
 277                         dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
 278                         goto POINTER_RETURN_BYTES;
 279                 }
 280         } else {
 281                 switch (dai_id) {
 282                 case I2S_BT_INSTANCE:
 283                         high = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_HIGH(adata));
 284                         low = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_LOW(adata));
 285                         break;
 286                 case I2S_SP_INSTANCE:
 287                         high = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH(adata));
 288                         low = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW(adata));
 289                         break;
 290                 case I2S_HS_INSTANCE:
 291                         high = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_HIGH);
 292                         low = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_LOW);
 293                         break;
 294                 case DMIC_INSTANCE:
 295                         high = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
 296                         low = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
 297                         break;
 298                 default:
 299                         dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
 300                         goto POINTER_RETURN_BYTES;
 301                 }
 302         }
 303         /* Get 64 bit value from two 32 bit registers */
 304         byte_count = (high << 32) | low;
 305
 306 POINTER_RETURN_BYTES:
 307         return byte_count;
 308 }
 309 #endif