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Merge tag 'seccomp-v6.13-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/kees...
[linux.git] / sound / soc / atmel / mchp-pdmc.c
blob06dc3c48e7e8daf764d1d466a51ef286306ddfd7
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Driver for Microchip Pulse Density Microphone Controller (PDMC) interfaces
4 //
5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries
6 //
7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
8
9 #include <dt-bindings/sound/microchip,pdmc.h>
10
11 #include <linux/bitfield.h>
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17
18 #include <sound/core.h>
19 #include <sound/dmaengine_pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/tlv.h>
22
23 /*
24 * ---- PDMC Register map ----
25 */
26 #define MCHP_PDMC_CR 0x00 /* Control Register */
27 #define MCHP_PDMC_MR 0x04 /* Mode Register */
28 #define MCHP_PDMC_CFGR 0x08 /* Configuration Register */
29 #define MCHP_PDMC_RHR 0x0C /* Receive Holding Register */
30 #define MCHP_PDMC_IER 0x14 /* Interrupt Enable Register */
31 #define MCHP_PDMC_IDR 0x18 /* Interrupt Disable Register */
32 #define MCHP_PDMC_IMR 0x1C /* Interrupt Mask Register */
33 #define MCHP_PDMC_ISR 0x20 /* Interrupt Status Register */
34 #define MCHP_PDMC_VER 0x50 /* Version Register */
35
36 /*
37 * ---- Control Register (Write-only) ----
38 */
39 #define MCHP_PDMC_CR_SWRST BIT(0) /* Software Reset */
40
41 /*
42 * ---- Mode Register (Read/Write) ----
43 */
44 #define MCHP_PDMC_MR_PDMCEN_MASK GENMASK(3, 0)
45 #define MCHP_PDMC_MR_PDMCEN(ch) (BIT(ch) & MCHP_PDMC_MR_PDMCEN_MASK)
46
47 #define MCHP_PDMC_MR_OSR_MASK GENMASK(17, 16)
48 #define MCHP_PDMC_MR_OSR64 (1 << 16)
49 #define MCHP_PDMC_MR_OSR128 (2 << 16)
50 #define MCHP_PDMC_MR_OSR256 (3 << 16)
51
52 #define MCHP_PDMC_MR_SINCORDER_MASK GENMASK(23, 20)
53
54 #define MCHP_PDMC_MR_SINC_OSR_MASK GENMASK(27, 24)
55 #define MCHP_PDMC_MR_SINC_OSR_DIS (0 << 24)
56 #define MCHP_PDMC_MR_SINC_OSR_8 (1 << 24)
57 #define MCHP_PDMC_MR_SINC_OSR_16 (2 << 24)
58 #define MCHP_PDMC_MR_SINC_OSR_32 (3 << 24)
59 #define MCHP_PDMC_MR_SINC_OSR_64 (4 << 24)
60 #define MCHP_PDMC_MR_SINC_OSR_128 (5 << 24)
61 #define MCHP_PDMC_MR_SINC_OSR_256 (6 << 24)
62
63 #define MCHP_PDMC_MR_CHUNK_MASK GENMASK(31, 28)
64
65 /*
66 * ---- Configuration Register (Read/Write) ----
67 */
68 #define MCHP_PDMC_CFGR_BSSEL_MASK (BIT(0) | BIT(2) | BIT(4) | BIT(6))
69 #define MCHP_PDMC_CFGR_BSSEL(ch) BIT((ch) * 2)
70
71 #define MCHP_PDMC_CFGR_PDMSEL_MASK (BIT(16) | BIT(18) | BIT(20) | BIT(22))
72 #define MCHP_PDMC_CFGR_PDMSEL(ch) BIT((ch) * 2 + 16)
73
74 /*
75 * ---- Interrupt Enable/Disable/Mask/Status Registers ----
76 */
77 #define MCHP_PDMC_IR_RXRDY BIT(0)
78 #define MCHP_PDMC_IR_RXEMPTY BIT(1)
79 #define MCHP_PDMC_IR_RXFULL BIT(2)
80 #define MCHP_PDMC_IR_RXCHUNK BIT(3)
81 #define MCHP_PDMC_IR_RXUDR BIT(4)
82 #define MCHP_PDMC_IR_RXOVR BIT(5)
83
84 /*
85 * ---- Version Register (Read-only) ----
86 */
87 #define MCHP_PDMC_VER_VERSION GENMASK(11, 0)
88
89 #define MCHP_PDMC_MAX_CHANNELS 4
90 #define MCHP_PDMC_DS_NO 2
91 #define MCHP_PDMC_EDGE_NO 2
92
93 /*
94 * ---- DMA chunk size allowed ----
95 */
96 #define MCHP_PDMC_DMA_8_WORD_CHUNK 8
97 #define MCHP_PDMC_DMA_4_WORD_CHUNK 4
98 #define MCHP_PDMC_DMA_2_WORD_CHUNK 2
99 #define MCHP_PDMC_DMA_1_WORD_CHUNK 1
100 #define DMA_BURST_ALIGNED(_p, _s, _w) !(_p % (_s * _w))
101
102 struct mic_map {
103 int ds_pos;
104 int clk_edge;
105 };
106
107 struct mchp_pdmc_chmap {
108 struct snd_pcm_chmap_elem *chmap;
109 struct mchp_pdmc *dd;
110 struct snd_pcm *pcm;
111 struct snd_kcontrol *kctl;
112 };
113
114 struct mchp_pdmc {
115 struct mic_map channel_mic_map[MCHP_PDMC_MAX_CHANNELS];
116 struct device *dev;
117 struct snd_dmaengine_dai_dma_data addr;
118 struct regmap *regmap;
119 struct clk *pclk;
120 struct clk *gclk;
121 u32 pdmcen;
122 u32 suspend_irq;
123 u32 startup_delay_us;
124 int mic_no;
125 int sinc_order;
126 bool audio_filter_en;
127 atomic_t busy_stream;
128 };
129
130 static const char *const mchp_pdmc_sinc_filter_order_text[] = {
131 "1", "2", "3", "4", "5"
132 };
133
134 static const unsigned int mchp_pdmc_sinc_filter_order_values[] = {
135 1, 2, 3, 4, 5,
136 };
137
138 static const struct soc_enum mchp_pdmc_sinc_filter_order_enum = {
139 .items = ARRAY_SIZE(mchp_pdmc_sinc_filter_order_text),
140 .texts = mchp_pdmc_sinc_filter_order_text,
141 .values = mchp_pdmc_sinc_filter_order_values,
142 };
143
144 static int mchp_pdmc_sinc_order_get(struct snd_kcontrol *kcontrol,
145 struct snd_ctl_elem_value *uvalue)
146 {
147 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
148 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
149 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
150 unsigned int item;
151
152 item = snd_soc_enum_val_to_item(e, dd->sinc_order);
153 uvalue->value.enumerated.item[0] = item;
154
155 return 0;
156 }
157
158 static int mchp_pdmc_sinc_order_put(struct snd_kcontrol *kcontrol,
159 struct snd_ctl_elem_value *uvalue)
160 {
161 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
162 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
163 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
164 unsigned int *item = uvalue->value.enumerated.item;
165 unsigned int val;
166
167 if (item[0] >= e->items)
168 return -EINVAL;
169
170 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
171
172 if (atomic_read(&dd->busy_stream))
173 return -EBUSY;
174
175 if (val == dd->sinc_order)
176 return 0;
177
178 dd->sinc_order = val;
179
180 return 1;
181 }
182
183 static int mchp_pdmc_af_get(struct snd_kcontrol *kcontrol,
184 struct snd_ctl_elem_value *uvalue)
185 {
186 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
187 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
188
189 uvalue->value.integer.value[0] = !!dd->audio_filter_en;
190
191 return 0;
192 }
193
194 static int mchp_pdmc_af_put(struct snd_kcontrol *kcontrol,
195 struct snd_ctl_elem_value *uvalue)
196 {
197 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
198 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
199 bool af = uvalue->value.integer.value[0] ? true : false;
200
201 if (atomic_read(&dd->busy_stream))
202 return -EBUSY;
203
204 if (dd->audio_filter_en == af)
205 return 0;
206
207 dd->audio_filter_en = af;
208
209 return 1;
210 }
211
212 static int mchp_pdmc_chmap_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
213 {
214 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
215
216 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
217 uinfo->count = info->dd->mic_no;
218 uinfo->value.integer.min = 0;
219 uinfo->value.integer.max = SNDRV_CHMAP_RR; /* maxmimum 4 channels */
220 return 0;
221 }
222
223 static inline struct snd_pcm_substream *
224 mchp_pdmc_chmap_substream(struct mchp_pdmc_chmap *info, unsigned int idx)
225 {
226 struct snd_pcm_substream *s;
227
228 for (s = info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; s; s = s->next)
229 if (s->number == idx)
230 return s;
231 return NULL;
232 }
233
234 static struct snd_pcm_chmap_elem *mchp_pdmc_chmap_get(struct snd_pcm_substream *substream,
235 struct mchp_pdmc_chmap *ch_info)
236 {
237 struct snd_pcm_chmap_elem *map;
238
239 for (map = ch_info->chmap; map->channels; map++) {
240 if (map->channels == substream->runtime->channels)
241 return map;
242 }
243 return NULL;
244 }
245
246 static int mchp_pdmc_chmap_ctl_get(struct snd_kcontrol *kcontrol,
247 struct snd_ctl_elem_value *ucontrol)
248 {
249 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
250 struct mchp_pdmc *dd = info->dd;
251 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
252 struct snd_pcm_substream *substream;
253 const struct snd_pcm_chmap_elem *map;
254 int i;
255 u32 cfgr_val = 0;
256
257 if (!info->chmap)
258 return -EINVAL;
259 substream = mchp_pdmc_chmap_substream(info, idx);
260 if (!substream)
261 return -ENODEV;
262 memset(ucontrol->value.integer.value, 0, sizeof(long) * info->dd->mic_no);
263 if (!substream->runtime)
264 return 0; /* no channels set */
265
266 map = mchp_pdmc_chmap_get(substream, info);
267 if (!map)
268 return -EINVAL;
269
270 for (i = 0; i < map->channels; i++) {
271 int map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO :
272 map->map[i] - SNDRV_CHMAP_FL;
273
274 /* make sure the reported channel map is the real one, so write the map */
275 if (dd->channel_mic_map[map_idx].ds_pos)
276 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
277 if (dd->channel_mic_map[map_idx].clk_edge)
278 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
279
280 ucontrol->value.integer.value[i] = map->map[i];
281 }
282
283 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
284
285 return 0;
286 }
287
288 static int mchp_pdmc_chmap_ctl_put(struct snd_kcontrol *kcontrol,
289 struct snd_ctl_elem_value *ucontrol)
290 {
291 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
292 struct mchp_pdmc *dd = info->dd;
293 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
294 struct snd_pcm_substream *substream;
295 struct snd_pcm_chmap_elem *map;
296 u32 cfgr_val = 0;
297 int i;
298
299 if (!info->chmap)
300 return -EINVAL;
301 substream = mchp_pdmc_chmap_substream(info, idx);
302 if (!substream)
303 return -ENODEV;
304
305 if (!substream->runtime)
306 return 0; /* just for avoiding error from alsactl restore */
307
308 map = mchp_pdmc_chmap_get(substream, info);
309 if (!map)
310 return -EINVAL;
311
312 for (i = 0; i < map->channels; i++) {
313 int map_idx;
314
315 map->map[i] = ucontrol->value.integer.value[i];
316 map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO :
317 map->map[i] - SNDRV_CHMAP_FL;
318
319 /* configure IP for the desired channel map */
320 if (dd->channel_mic_map[map_idx].ds_pos)
321 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
322 if (dd->channel_mic_map[map_idx].clk_edge)
323 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
324 }
325
326 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
327
328 return 0;
329 }
330
331 static void mchp_pdmc_chmap_ctl_private_free(struct snd_kcontrol *kcontrol)
332 {
333 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
334
335 info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = NULL;
336 kfree(info);
337 }
338
339 static int mchp_pdmc_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
340 unsigned int size, unsigned int __user *tlv)
341 {
342 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
343 const struct snd_pcm_chmap_elem *map;
344 unsigned int __user *dst;
345 int c, count = 0;
346
347 if (!info->chmap)
348 return -EINVAL;
349 if (size < 8)
350 return -ENOMEM;
351 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
352 return -EFAULT;
353 size -= 8;
354 dst = tlv + 2;
355 for (map = info->chmap; map->channels; map++) {
356 int chs_bytes = map->channels * 4;
357
358 if (size < 8)
359 return -ENOMEM;
360 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
361 put_user(chs_bytes, dst + 1))
362 return -EFAULT;
363 dst += 2;
364 size -= 8;
365 count += 8;
366 if (size < chs_bytes)
367 return -ENOMEM;
368 size -= chs_bytes;
369 count += chs_bytes;
370 for (c = 0; c < map->channels; c++) {
371 if (put_user(map->map[c], dst))
372 return -EFAULT;
373 dst++;
374 }
375 }
376 if (put_user(count, tlv + 1))
377 return -EFAULT;
378 return 0;
379 }
380
381 static const struct snd_kcontrol_new mchp_pdmc_snd_controls[] = {
382 SOC_SINGLE_BOOL_EXT("Audio Filter", 0, &mchp_pdmc_af_get, &mchp_pdmc_af_put),
383 {
384 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
385 .name = "SINC Filter Order",
386 .info = snd_soc_info_enum_double,
387 .get = mchp_pdmc_sinc_order_get,
388 .put = mchp_pdmc_sinc_order_put,
389 .private_value = (unsigned long)&mchp_pdmc_sinc_filter_order_enum,
390 },
391 };
392
393 static const struct snd_soc_component_driver mchp_pdmc_dai_component = {
394 .name = "mchp-pdmc",
395 .controls = mchp_pdmc_snd_controls,
396 .num_controls = ARRAY_SIZE(mchp_pdmc_snd_controls),
397 };
398
399 static const unsigned int mchp_pdmc_1mic[] = {1};
400 static const unsigned int mchp_pdmc_2mic[] = {1, 2};
401 static const unsigned int mchp_pdmc_3mic[] = {1, 2, 3};
402 static const unsigned int mchp_pdmc_4mic[] = {1, 2, 3, 4};
403
404 static const struct snd_pcm_hw_constraint_list mchp_pdmc_chan_constr[] = {
405 {
406 .list = mchp_pdmc_1mic,
407 .count = ARRAY_SIZE(mchp_pdmc_1mic),
408 },
409 {
410 .list = mchp_pdmc_2mic,
411 .count = ARRAY_SIZE(mchp_pdmc_2mic),
412 },
413 {
414 .list = mchp_pdmc_3mic,
415 .count = ARRAY_SIZE(mchp_pdmc_3mic),
416 },
417 {
418 .list = mchp_pdmc_4mic,
419 .count = ARRAY_SIZE(mchp_pdmc_4mic),
420 },
421 };
422
423 static int mchp_pdmc_startup(struct snd_pcm_substream *substream,
424 struct snd_soc_dai *dai)
425 {
426 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
427
428 regmap_write(dd->regmap, MCHP_PDMC_CR, MCHP_PDMC_CR_SWRST);
429
430 snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
431 &mchp_pdmc_chan_constr[dd->mic_no - 1]);
432
433 return 0;
434 }
435
436 static int mchp_pdmc_dai_probe(struct snd_soc_dai *dai)
437 {
438 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
439
440 snd_soc_dai_init_dma_data(dai, NULL, &dd->addr);
441
442 return 0;
443 }
444
445 static int mchp_pdmc_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
446 {
447 unsigned int fmt_master = fmt & SND_SOC_DAIFMT_MASTER_MASK;
448 unsigned int fmt_format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
449
450 /* IP needs to be bitclock master */
451 if (fmt_master != SND_SOC_DAIFMT_BP_FP &&
452 fmt_master != SND_SOC_DAIFMT_BP_FC)
453 return -EINVAL;
454
455 /* IP supports only PDM interface */
456 if (fmt_format != SND_SOC_DAIFMT_PDM)
457 return -EINVAL;
458
459 return 0;
460 }
461
462 static u32 mchp_pdmc_mr_set_osr(int audio_filter_en, unsigned int osr)
463 {
464 if (audio_filter_en) {
465 switch (osr) {
466 case 64:
467 return MCHP_PDMC_MR_OSR64;
468 case 128:
469 return MCHP_PDMC_MR_OSR128;
470 case 256:
471 return MCHP_PDMC_MR_OSR256;
472 }
473 } else {
474 switch (osr) {
475 case 8:
476 return MCHP_PDMC_MR_SINC_OSR_8;
477 case 16:
478 return MCHP_PDMC_MR_SINC_OSR_16;
479 case 32:
480 return MCHP_PDMC_MR_SINC_OSR_32;
481 case 64:
482 return MCHP_PDMC_MR_SINC_OSR_64;
483 case 128:
484 return MCHP_PDMC_MR_SINC_OSR_128;
485 case 256:
486 return MCHP_PDMC_MR_SINC_OSR_256;
487 }
488 }
489 return 0;
490 }
491
492 static inline int mchp_pdmc_period_to_maxburst(int period_size, int sample_size)
493 {
494 int p_size = period_size;
495 int s_size = sample_size;
496
497 if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_PDMC_DMA_8_WORD_CHUNK))
498 return MCHP_PDMC_DMA_8_WORD_CHUNK;
499 if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_PDMC_DMA_4_WORD_CHUNK))
500 return MCHP_PDMC_DMA_4_WORD_CHUNK;
501 if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_PDMC_DMA_2_WORD_CHUNK))
502 return MCHP_PDMC_DMA_2_WORD_CHUNK;
503 return MCHP_PDMC_DMA_1_WORD_CHUNK;
504 }
505
506 static struct snd_pcm_chmap_elem mchp_pdmc_std_chmaps[] = {
507 { .channels = 1,
508 .map = { SNDRV_CHMAP_MONO } },
509 { .channels = 2,
510 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
511 { .channels = 3,
512 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
513 SNDRV_CHMAP_RL } },
514 { .channels = 4,
515 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
516 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
517 { }
518 };
519
520 static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream,
521 struct snd_pcm_hw_params *params,
522 struct snd_soc_dai *dai)
523 {
524 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
525 struct snd_soc_component *comp = dai->component;
526 unsigned long gclk_rate = 0;
527 unsigned long best_diff_rate = ~0UL;
528 unsigned int channels = params_channels(params);
529 unsigned int osr = 0, osr_start;
530 unsigned int fs = params_rate(params);
531 int sample_bytes = params_physical_width(params) / 8;
532 int period_bytes = params_period_size(params) *
533 params_channels(params) * sample_bytes;
534 int maxburst;
535 u32 mr_val = 0;
536 u32 cfgr_val = 0;
537 int i;
538 int ret;
539
540 dev_dbg(comp->dev, "%s() rate=%u format=%#x width=%u channels=%u period_bytes=%d\n",
541 __func__, params_rate(params), params_format(params),
542 params_width(params), params_channels(params), period_bytes);
543
544 if (channels > dd->mic_no) {
545 dev_err(comp->dev, "more channels %u than microphones %d\n",
546 channels, dd->mic_no);
547 return -EINVAL;
548 }
549
550 dd->pdmcen = 0;
551 for (i = 0; i < channels; i++) {
552 dd->pdmcen |= MCHP_PDMC_MR_PDMCEN(i);
553 if (dd->channel_mic_map[i].ds_pos)
554 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
555 if (dd->channel_mic_map[i].clk_edge)
556 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
557 }
558
559 /*
560 * from these point forward, we consider the controller busy, so the
561 * audio filter and SINC order can't be changed
562 */
563 atomic_set(&dd->busy_stream, 1);
564 for (osr_start = dd->audio_filter_en ? 64 : 8;
565 osr_start <= 256 && best_diff_rate; osr_start *= 2) {
566 long round_rate;
567 unsigned long diff_rate;
568
569 round_rate = clk_round_rate(dd->gclk,
570 (unsigned long)fs * 16 * osr_start);
571 if (round_rate < 0)
572 continue;
573 diff_rate = abs((fs * 16 * osr_start) - round_rate);
574 if (diff_rate < best_diff_rate) {
575 best_diff_rate = diff_rate;
576 osr = osr_start;
577 gclk_rate = fs * 16 * osr;
578 }
579 }
580 if (!gclk_rate) {
581 dev_err(comp->dev, "invalid sampling rate: %u\n", fs);
582 return -EINVAL;
583 }
584
585 /* CLK is enabled by runtime PM. */
586 clk_disable_unprepare(dd->gclk);
587
588 /* set the rate */
589 ret = clk_set_rate(dd->gclk, gclk_rate);
590 clk_prepare_enable(dd->gclk);
591 if (ret) {
592 dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n",
593 gclk_rate, ret);
594 return ret;
595 }
596
597 mr_val |= mchp_pdmc_mr_set_osr(dd->audio_filter_en, osr);
598
599 mr_val |= FIELD_PREP(MCHP_PDMC_MR_SINCORDER_MASK, dd->sinc_order);
600
601 maxburst = mchp_pdmc_period_to_maxburst(period_bytes, sample_bytes);
602 dd->addr.maxburst = maxburst;
603 mr_val |= FIELD_PREP(MCHP_PDMC_MR_CHUNK_MASK, dd->addr.maxburst);
604 dev_dbg(comp->dev, "maxburst set to %d\n", dd->addr.maxburst);
605
606 snd_soc_component_update_bits(comp, MCHP_PDMC_MR,
607 MCHP_PDMC_MR_OSR_MASK |
608 MCHP_PDMC_MR_SINCORDER_MASK |
609 MCHP_PDMC_MR_SINC_OSR_MASK |
610 MCHP_PDMC_MR_CHUNK_MASK, mr_val);
611
612 snd_soc_component_write(comp, MCHP_PDMC_CFGR, cfgr_val);
613
614 return 0;
615 }
616
617 static void mchp_pdmc_noise_filter_workaround(struct mchp_pdmc *dd)
618 {
619 u32 tmp, steps = 16;
620
621 /*
622 * PDMC doesn't wait for microphones' startup time thus the acquisition
623 * may start before the microphones are ready leading to poc noises at
624 * the beginning of capture. To avoid this, we need to wait 50ms (in
625 * normal startup procedure) or 150 ms (worst case after resume from sleep
626 * states) after microphones are enabled and then clear the FIFOs (by
627 * reading the RHR 16 times) and possible interrupts before continuing.
628 * Also, for this to work the DMA needs to be started after interrupts
629 * are enabled.
630 */
631 usleep_range(dd->startup_delay_us, dd->startup_delay_us + 5);
632
633 while (steps--)
634 regmap_read(dd->regmap, MCHP_PDMC_RHR, &tmp);
635
636 /* Clear interrupts. */
637 regmap_read(dd->regmap, MCHP_PDMC_ISR, &tmp);
638 }
639
640 static int mchp_pdmc_trigger(struct snd_pcm_substream *substream,
641 int cmd, struct snd_soc_dai *dai)
642 {
643 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
644 struct snd_soc_component *cpu = dai->component;
645 #ifdef DEBUG
646 u32 val;
647 #endif
648
649 switch (cmd) {
650 case SNDRV_PCM_TRIGGER_RESUME:
651 case SNDRV_PCM_TRIGGER_START:
652 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
653 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR,
654 MCHP_PDMC_MR_PDMCEN_MASK,
655 dd->pdmcen);
656
657 mchp_pdmc_noise_filter_workaround(dd);
658
659 /* Enable interrupts. */
660 regmap_write(dd->regmap, MCHP_PDMC_IER, dd->suspend_irq |
661 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR);
662 dd->suspend_irq = 0;
663 break;
664 case SNDRV_PCM_TRIGGER_SUSPEND:
665 regmap_read(dd->regmap, MCHP_PDMC_IMR, &dd->suspend_irq);
666 fallthrough;
667 case SNDRV_PCM_TRIGGER_STOP:
668 /* Disable overrun and underrun error interrupts */
669 regmap_write(dd->regmap, MCHP_PDMC_IDR, dd->suspend_irq |
670 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR);
671 fallthrough;
672 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
673 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR,
674 MCHP_PDMC_MR_PDMCEN_MASK, 0);
675 break;
676 default:
677 return -EINVAL;
678 }
679
680 #ifdef DEBUG
681 regmap_read(dd->regmap, MCHP_PDMC_MR, &val);
682 dev_dbg(dd->dev, "MR (0x%02x): 0x%08x\n", MCHP_PDMC_MR, val);
683 regmap_read(dd->regmap, MCHP_PDMC_CFGR, &val);
684 dev_dbg(dd->dev, "CFGR (0x%02x): 0x%08x\n", MCHP_PDMC_CFGR, val);
685 regmap_read(dd->regmap, MCHP_PDMC_IMR, &val);
686 dev_dbg(dd->dev, "IMR (0x%02x): 0x%08x\n", MCHP_PDMC_IMR, val);
687 #endif
688
689 return 0;
690 }
691
692 static int mchp_pdmc_add_chmap_ctls(struct snd_pcm *pcm, struct mchp_pdmc *dd)
693 {
694 struct mchp_pdmc_chmap *info;
695 struct snd_kcontrol_new knew = {
696 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
697 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
698 SNDRV_CTL_ELEM_ACCESS_TLV_READ |
699 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK,
700 .info = mchp_pdmc_chmap_ctl_info,
701 .get = mchp_pdmc_chmap_ctl_get,
702 .put = mchp_pdmc_chmap_ctl_put,
703 .tlv.c = mchp_pdmc_chmap_ctl_tlv,
704 };
705 int err;
706
707 if (WARN_ON(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl))
708 return -EBUSY;
709 info = kzalloc(sizeof(*info), GFP_KERNEL);
710 if (!info)
711 return -ENOMEM;
712 info->pcm = pcm;
713 info->dd = dd;
714 info->chmap = mchp_pdmc_std_chmaps;
715 knew.name = "Capture Channel Map";
716 knew.device = pcm->device;
717 knew.count = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream_count;
718 info->kctl = snd_ctl_new1(&knew, info);
719 if (!info->kctl) {
720 kfree(info);
721 return -ENOMEM;
722 }
723 info->kctl->private_free = mchp_pdmc_chmap_ctl_private_free;
724 err = snd_ctl_add(pcm->card, info->kctl);
725 if (err < 0)
726 return err;
727 pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = info->kctl;
728 return 0;
729 }
730
731 static int mchp_pdmc_pcm_new(struct snd_soc_pcm_runtime *rtd,
732 struct snd_soc_dai *dai)
733 {
734 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
735 int ret;
736
737 ret = mchp_pdmc_add_chmap_ctls(rtd->pcm, dd);
738 if (ret < 0)
739 dev_err(dd->dev, "failed to add channel map controls: %d\n", ret);
740
741 return ret;
742 }
743
744 static const struct snd_soc_dai_ops mchp_pdmc_dai_ops = {
745 .probe = mchp_pdmc_dai_probe,
746 .set_fmt = mchp_pdmc_set_fmt,
747 .startup = mchp_pdmc_startup,
748 .hw_params = mchp_pdmc_hw_params,
749 .trigger = mchp_pdmc_trigger,
750 .pcm_new = &mchp_pdmc_pcm_new,
751 };
752
753 static struct snd_soc_dai_driver mchp_pdmc_dai = {
754 .name = "mchp-pdmc",
755 .capture = {
756 .stream_name = "Capture",
757 .channels_min = 1,
758 .channels_max = 4,
759 .rate_min = 8000,
760 .rate_max = 192000,
761 .rates = SNDRV_PCM_RATE_KNOT,
762 .formats = SNDRV_PCM_FMTBIT_S24_LE,
763 },
764 .ops = &mchp_pdmc_dai_ops,
765 };
766
767 /* PDMC interrupt handler */
768 static irqreturn_t mchp_pdmc_interrupt(int irq, void *dev_id)
769 {
770 struct mchp_pdmc *dd = dev_id;
771 u32 isr, msr, pending;
772 irqreturn_t ret = IRQ_NONE;
773
774 regmap_read(dd->regmap, MCHP_PDMC_ISR, &isr);
775 regmap_read(dd->regmap, MCHP_PDMC_IMR, &msr);
776
777 pending = isr & msr;
778 dev_dbg(dd->dev, "ISR (0x%02x): 0x%08x, IMR (0x%02x): 0x%08x, pending: 0x%08x\n",
779 MCHP_PDMC_ISR, isr, MCHP_PDMC_IMR, msr, pending);
780 if (!pending)
781 return IRQ_NONE;
782
783 if (pending & MCHP_PDMC_IR_RXUDR) {
784 dev_warn(dd->dev, "underrun detected\n");
785 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXUDR);
786 ret = IRQ_HANDLED;
787 }
788 if (pending & MCHP_PDMC_IR_RXOVR) {
789 dev_warn(dd->dev, "overrun detected\n");
790 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXOVR);
791 ret = IRQ_HANDLED;
792 }
793
794 return ret;
795 }
796
797 /* regmap configuration */
798 static bool mchp_pdmc_readable_reg(struct device *dev, unsigned int reg)
799 {
800 switch (reg) {
801 case MCHP_PDMC_MR:
802 case MCHP_PDMC_CFGR:
803 case MCHP_PDMC_IMR:
804 case MCHP_PDMC_ISR:
805 case MCHP_PDMC_RHR:
806 case MCHP_PDMC_VER:
807 return true;
808 default:
809 return false;
810 }
811 }
812
813 static bool mchp_pdmc_writeable_reg(struct device *dev, unsigned int reg)
814 {
815 switch (reg) {
816 case MCHP_PDMC_CR:
817 case MCHP_PDMC_MR:
818 case MCHP_PDMC_CFGR:
819 case MCHP_PDMC_IER:
820 case MCHP_PDMC_IDR:
821 return true;
822 default:
823 return false;
824 }
825 }
826
827 static bool mchp_pdmc_volatile_reg(struct device *dev, unsigned int reg)
828 {
829 switch (reg) {
830 case MCHP_PDMC_ISR:
831 case MCHP_PDMC_RHR:
832 return true;
833 default:
834 return false;
835 }
836 }
837
838 static bool mchp_pdmc_precious_reg(struct device *dev, unsigned int reg)
839 {
840 switch (reg) {
841 case MCHP_PDMC_RHR:
842 case MCHP_PDMC_ISR:
843 return true;
844 default:
845 return false;
846 }
847 }
848
849 static const struct regmap_config mchp_pdmc_regmap_config = {
850 .reg_bits = 32,
851 .reg_stride = 4,
852 .val_bits = 32,
853 .max_register = MCHP_PDMC_VER,
854 .readable_reg = mchp_pdmc_readable_reg,
855 .writeable_reg = mchp_pdmc_writeable_reg,
856 .precious_reg = mchp_pdmc_precious_reg,
857 .volatile_reg = mchp_pdmc_volatile_reg,
858 .cache_type = REGCACHE_FLAT,
859 };
860
861 static int mchp_pdmc_dt_init(struct mchp_pdmc *dd)
862 {
863 struct device_node *np = dd->dev->of_node;
864 bool mic_ch[MCHP_PDMC_DS_NO][MCHP_PDMC_EDGE_NO] = {0};
865 int i;
866 int ret;
867
868 if (!np) {
869 dev_err(dd->dev, "device node not found\n");
870 return -EINVAL;
871 }
872
873 dd->mic_no = of_property_count_u32_elems(np, "microchip,mic-pos");
874 if (dd->mic_no < 0) {
875 dev_err(dd->dev, "failed to get microchip,mic-pos: %d",
876 dd->mic_no);
877 return dd->mic_no;
878 }
879 if (!dd->mic_no || dd->mic_no % 2 ||
880 dd->mic_no / 2 > MCHP_PDMC_MAX_CHANNELS) {
881 dev_err(dd->dev, "invalid array length for microchip,mic-pos: %d",
882 dd->mic_no);
883 return -EINVAL;
884 }
885
886 dd->mic_no /= 2;
887
888 dev_info(dd->dev, "%d PDM microphones declared\n", dd->mic_no);
889
890 /*
891 * by default, we consider the order of microphones in
892 * microchip,mic-pos to be the same with the channel mapping;
893 * 1st microphone channel 0, 2nd microphone channel 1, etc.
894 */
895 for (i = 0; i < dd->mic_no; i++) {
896 int ds;
897 int edge;
898
899 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2,
900 &ds);
901 if (ret) {
902 dev_err(dd->dev,
903 "failed to get value no %d value from microchip,mic-pos: %d",
904 i * 2, ret);
905 return ret;
906 }
907 if (ds >= MCHP_PDMC_DS_NO) {
908 dev_err(dd->dev,
909 "invalid DS index in microchip,mic-pos array: %d",
910 ds);
911 return -EINVAL;
912 }
913
914 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2 + 1,
915 &edge);
916 if (ret) {
917 dev_err(dd->dev,
918 "failed to get value no %d value from microchip,mic-pos: %d",
919 i * 2 + 1, ret);
920 return ret;
921 }
922
923 if (edge != MCHP_PDMC_CLK_POSITIVE &&
924 edge != MCHP_PDMC_CLK_NEGATIVE) {
925 dev_err(dd->dev,
926 "invalid edge in microchip,mic-pos array: %d", edge);
927 return -EINVAL;
928 }
929 if (mic_ch[ds][edge]) {
930 dev_err(dd->dev,
931 "duplicated mic (DS %d, edge %d) in microchip,mic-pos array",
932 ds, edge);
933 return -EINVAL;
934 }
935 mic_ch[ds][edge] = true;
936 dd->channel_mic_map[i].ds_pos = ds;
937 dd->channel_mic_map[i].clk_edge = edge;
938 }
939
940 dd->startup_delay_us = 150000;
941 of_property_read_u32(np, "microchip,startup-delay-us", &dd->startup_delay_us);
942
943 return 0;
944 }
945
946 /* used to clean the channel index found on RHR's MSB */
947 static int mchp_pdmc_process(struct snd_pcm_substream *substream,
948 int channel, unsigned long hwoff,
949 unsigned long bytes)
950 {
951 struct snd_pcm_runtime *runtime = substream->runtime;
952 u8 *dma_ptr = runtime->dma_area + hwoff +
953 channel * (runtime->dma_bytes / runtime->channels);
954 u8 *dma_ptr_end = dma_ptr + bytes;
955 unsigned int sample_size = samples_to_bytes(runtime, 1);
956
957 for (; dma_ptr < dma_ptr_end; dma_ptr += sample_size)
958 *dma_ptr = 0;
959
960 return 0;
961 }
962
963 static struct snd_dmaengine_pcm_config mchp_pdmc_config = {
964 .process = mchp_pdmc_process,
965 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
966 };
967
968 static int mchp_pdmc_runtime_suspend(struct device *dev)
969 {
970 struct mchp_pdmc *dd = dev_get_drvdata(dev);
971
972 regcache_cache_only(dd->regmap, true);
973
974 clk_disable_unprepare(dd->gclk);
975 clk_disable_unprepare(dd->pclk);
976
977 return 0;
978 }
979
980 static int mchp_pdmc_runtime_resume(struct device *dev)
981 {
982 struct mchp_pdmc *dd = dev_get_drvdata(dev);
983 int ret;
984
985 ret = clk_prepare_enable(dd->pclk);
986 if (ret) {
987 dev_err(dd->dev,
988 "failed to enable the peripheral clock: %d\n", ret);
989 return ret;
990 }
991 ret = clk_prepare_enable(dd->gclk);
992 if (ret) {
993 dev_err(dd->dev,
994 "failed to enable generic clock: %d\n", ret);
995 goto disable_pclk;
996 }
997
998 regcache_cache_only(dd->regmap, false);
999 regcache_mark_dirty(dd->regmap);
1000 ret = regcache_sync(dd->regmap);
1001 if (ret) {
1002 regcache_cache_only(dd->regmap, true);
1003 clk_disable_unprepare(dd->gclk);
1004 disable_pclk:
1005 clk_disable_unprepare(dd->pclk);
1006 }
1007
1008 return ret;
1009 }
1010
1011 static int mchp_pdmc_probe(struct platform_device *pdev)
1012 {
1013 struct device *dev = &pdev->dev;
1014 struct mchp_pdmc *dd;
1015 struct resource *res;
1016 void __iomem *io_base;
1017 u32 version;
1018 int irq;
1019 int ret;
1020
1021 dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL);
1022 if (!dd)
1023 return -ENOMEM;
1024
1025 dd->dev = &pdev->dev;
1026 ret = mchp_pdmc_dt_init(dd);
1027 if (ret < 0)
1028 return ret;
1029
1030 irq = platform_get_irq(pdev, 0);
1031 if (irq < 0)
1032 return irq;
1033
1034 dd->pclk = devm_clk_get(dev, "pclk");
1035 if (IS_ERR(dd->pclk)) {
1036 ret = PTR_ERR(dd->pclk);
1037 dev_err(dev, "failed to get peripheral clock: %d\n", ret);
1038 return ret;
1039 }
1040
1041 dd->gclk = devm_clk_get(dev, "gclk");
1042 if (IS_ERR(dd->gclk)) {
1043 ret = PTR_ERR(dd->gclk);
1044 dev_err(dev, "failed to get GCK: %d\n", ret);
1045 return ret;
1046 }
1047
1048 io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1049 if (IS_ERR(io_base)) {
1050 ret = PTR_ERR(io_base);
1051 dev_err(dev, "failed to remap register memory: %d\n", ret);
1052 return ret;
1053 }
1054
1055 dd->regmap = devm_regmap_init_mmio(dev, io_base,
1056 &mchp_pdmc_regmap_config);
1057 if (IS_ERR(dd->regmap)) {
1058 ret = PTR_ERR(dd->regmap);
1059 dev_err(dev, "failed to init register map: %d\n", ret);
1060 return ret;
1061 }
1062
1063 ret = devm_request_irq(dev, irq, mchp_pdmc_interrupt, 0,
1064 dev_name(&pdev->dev), dd);
1065 if (ret < 0) {
1066 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
1067 irq, ret);
1068 return ret;
1069 }
1070
1071 /* by default audio filter is enabled and the SINC Filter order
1072 * will be set to the recommended value, 3
1073 */
1074 dd->audio_filter_en = true;
1075 dd->sinc_order = 3;
1076
1077 dd->addr.addr = (dma_addr_t)res->start + MCHP_PDMC_RHR;
1078 platform_set_drvdata(pdev, dd);
1079
1080 pm_runtime_enable(dd->dev);
1081 if (!pm_runtime_enabled(dd->dev)) {
1082 ret = mchp_pdmc_runtime_resume(dd->dev);
1083 if (ret)
1084 return ret;
1085 }
1086
1087 /* register platform */
1088 ret = devm_snd_dmaengine_pcm_register(dev, &mchp_pdmc_config, 0);
1089 if (ret) {
1090 dev_err(dev, "could not register platform: %d\n", ret);
1091 goto pm_runtime_suspend;
1092 }
1093
1094 ret = devm_snd_soc_register_component(dev, &mchp_pdmc_dai_component,
1095 &mchp_pdmc_dai, 1);
1096 if (ret) {
1097 dev_err(dev, "could not register CPU DAI: %d\n", ret);
1098 goto pm_runtime_suspend;
1099 }
1100
1101 /* print IP version */
1102 regmap_read(dd->regmap, MCHP_PDMC_VER, &version);
1103 dev_info(dd->dev, "hw version: %#lx\n",
1104 version & MCHP_PDMC_VER_VERSION);
1105
1106 return 0;
1107
1108 pm_runtime_suspend:
1109 if (!pm_runtime_status_suspended(dd->dev))
1110 mchp_pdmc_runtime_suspend(dd->dev);
1111 pm_runtime_disable(dd->dev);
1112
1113 return ret;
1114 }
1115
1116 static void mchp_pdmc_remove(struct platform_device *pdev)
1117 {
1118 struct mchp_pdmc *dd = platform_get_drvdata(pdev);
1119
1120 atomic_set(&dd->busy_stream, 0);
1121
1122 if (!pm_runtime_status_suspended(dd->dev))
1123 mchp_pdmc_runtime_suspend(dd->dev);
1124
1125 pm_runtime_disable(dd->dev);
1126 }
1127
1128 static const struct of_device_id mchp_pdmc_of_match[] = {
1129 {
1130 .compatible = "microchip,sama7g5-pdmc",
1131 }, {
1132 /* sentinel */
1133 }
1134 };
1135 MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match);
1136
1137 static const struct dev_pm_ops mchp_pdmc_pm_ops = {
1138 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1139 RUNTIME_PM_OPS(mchp_pdmc_runtime_suspend, mchp_pdmc_runtime_resume,
1140 NULL)
1141 };
1142
1143 static struct platform_driver mchp_pdmc_driver = {
1144 .driver = {
1145 .name = "mchp-pdmc",
1146 .of_match_table = of_match_ptr(mchp_pdmc_of_match),
1147 .pm = pm_ptr(&mchp_pdmc_pm_ops),
1148 },
1149 .probe = mchp_pdmc_probe,
1150 .remove = mchp_pdmc_remove,
1151 };
1152 module_platform_driver(mchp_pdmc_driver);
1153
1154 MODULE_DESCRIPTION("Microchip PDMC driver under ALSA SoC architecture");
1155 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
1156 MODULE_LICENSE("GPL v2");
Linux Kernel