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Merge tag 'sched_ext-for-6.13-rc5-fixes' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / sound / soc / fsl / fsl_xcvr.c
blob9c184ab7346884a1cd40cf8d2d79b490b611a86f
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright 2019 NXP
3
4 #include <linux/bitrev.h>
5 #include <linux/clk.h>
6 #include <linux/firmware.h>
7 #include <linux/interrupt.h>
8 #include <linux/module.h>
9 #include <linux/of_platform.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/regmap.h>
12 #include <linux/reset.h>
13 #include <sound/dmaengine_pcm.h>
14 #include <sound/pcm_iec958.h>
15 #include <sound/pcm_params.h>
16
17 #include "fsl_xcvr.h"
18 #include "fsl_utils.h"
19 #include "imx-pcm.h"
20
21 #define FSL_XCVR_CAPDS_SIZE 256
22
23 enum fsl_xcvr_pll_verison {
24 PLL_MX8MP,
25 PLL_MX95,
26 };
27
28 struct fsl_xcvr_soc_data {
29 const char *fw_name;
30 bool spdif_only;
31 bool use_edma;
32 bool use_phy;
33 enum fsl_xcvr_pll_verison pll_ver;
34 };
35
36 struct fsl_xcvr {
37 const struct fsl_xcvr_soc_data *soc_data;
38 struct platform_device *pdev;
39 struct regmap *regmap;
40 struct clk *ipg_clk;
41 struct clk *pll_ipg_clk;
42 struct clk *phy_clk;
43 struct clk *spba_clk;
44 struct clk *pll8k_clk;
45 struct clk *pll11k_clk;
46 struct reset_control *reset;
47 u8 streams;
48 u32 mode;
49 u32 arc_mode;
50 void __iomem *ram_addr;
51 struct snd_dmaengine_dai_dma_data dma_prms_rx;
52 struct snd_dmaengine_dai_dma_data dma_prms_tx;
53 struct snd_aes_iec958 rx_iec958;
54 struct snd_aes_iec958 tx_iec958;
55 u8 cap_ds[FSL_XCVR_CAPDS_SIZE];
56 struct work_struct work_rst;
57 spinlock_t lock; /* Protect hw_reset and trigger */
58 };
59
60 static const struct fsl_xcvr_pll_conf {
61 u8 mfi; /* min=0x18, max=0x38 */
62 u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */
63 u32 mfd; /* unsigned int */
64 u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */
65 } fsl_xcvr_pll_cfg[] = {
66 { .mfi = 54, .mfn = 1, .mfd = 6, .fout = 1300000000, }, /* 1.3 GHz */
67 { .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, }, /* 8000 Hz */
68 { .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, }, /* 11025 Hz */
69 { .mfi = 29, .mfn = 1, .mfd = 6, .fout = 700000000, }, /* 700 MHz */
70 };
71
72 /*
73 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
74 * stream. Todo: to check how this case can be considered below
75 */
76 static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, };
77 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = {
78 .count = ARRAY_SIZE(fsl_xcvr_earc_channels),
79 .list = fsl_xcvr_earc_channels,
80 };
81
82 static const u32 fsl_xcvr_earc_rates[] = {
83 32000, 44100, 48000, 64000, 88200, 96000,
84 128000, 176400, 192000, 256000, 352800, 384000,
85 512000, 705600, 768000, 1024000, 1411200, 1536000,
86 };
87 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = {
88 .count = ARRAY_SIZE(fsl_xcvr_earc_rates),
89 .list = fsl_xcvr_earc_rates,
90 };
91
92 static const u32 fsl_xcvr_spdif_channels[] = { 2, };
93 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr = {
94 .count = ARRAY_SIZE(fsl_xcvr_spdif_channels),
95 .list = fsl_xcvr_spdif_channels,
96 };
97
98 static const u32 fsl_xcvr_spdif_rates[] = {
99 32000, 44100, 48000, 88200, 96000, 176400, 192000,
100 };
101 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = {
102 .count = ARRAY_SIZE(fsl_xcvr_spdif_rates),
103 .list = fsl_xcvr_spdif_rates,
104 };
105
106 static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol,
107 struct snd_ctl_elem_value *ucontrol)
108 {
109 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
110 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
111 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
112 unsigned int *item = ucontrol->value.enumerated.item;
113
114 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]);
115
116 return 0;
117 }
118
119 static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol,
120 struct snd_ctl_elem_value *ucontrol)
121 {
122 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
123 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
124
125 ucontrol->value.enumerated.item[0] = xcvr->arc_mode;
126
127 return 0;
128 }
129
130 static const u32 fsl_xcvr_phy_arc_cfg[] = {
131 FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN,
132 };
133
134 static const char * const fsl_xcvr_arc_mode[] = { "Single Ended", "Common", };
135 static const struct soc_enum fsl_xcvr_arc_mode_enum =
136 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_arc_mode), fsl_xcvr_arc_mode);
137 static struct snd_kcontrol_new fsl_xcvr_arc_mode_kctl =
138 SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum,
139 fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put);
140
141 /* Capabilities data structure, bytes */
142 static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol,
143 struct snd_ctl_elem_info *uinfo)
144 {
145 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
146 uinfo->count = FSL_XCVR_CAPDS_SIZE;
147
148 return 0;
149 }
150
151 static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol,
152 struct snd_ctl_elem_value *ucontrol)
153 {
154 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
155 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
156
157 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE);
158
159 return 0;
160 }
161
162 static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol,
163 struct snd_ctl_elem_value *ucontrol)
164 {
165 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
166 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
167
168 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE);
169
170 return 0;
171 }
172
173 static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = {
174 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
175 .name = "Capabilities Data Structure",
176 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
177 .info = fsl_xcvr_type_capds_bytes_info,
178 .get = fsl_xcvr_capds_get,
179 .put = fsl_xcvr_capds_put,
180 };
181
182 static int fsl_xcvr_activate_ctl(struct snd_soc_dai *dai, const char *name,
183 bool active)
184 {
185 struct snd_soc_card *card = dai->component->card;
186 struct snd_kcontrol *kctl;
187 bool enabled;
188
189 lockdep_assert_held(&card->snd_card->controls_rwsem);
190
191 kctl = snd_soc_card_get_kcontrol(card, name);
192 if (kctl == NULL)
193 return -ENOENT;
194
195 enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0);
196 if (active == enabled)
197 return 0; /* nothing to do */
198
199 if (active)
200 kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
201 else
202 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE;
203
204 snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
205
206 return 1;
207 }
208
209 static int fsl_xcvr_mode_put(struct snd_kcontrol *kcontrol,
210 struct snd_ctl_elem_value *ucontrol)
211 {
212 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
213 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
214 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
215 unsigned int *item = ucontrol->value.enumerated.item;
216 struct snd_soc_card *card = dai->component->card;
217 struct snd_soc_pcm_runtime *rtd;
218
219 xcvr->mode = snd_soc_enum_item_to_val(e, item[0]);
220
221 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
222 (xcvr->mode == FSL_XCVR_MODE_ARC));
223 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
224 (xcvr->mode == FSL_XCVR_MODE_EARC));
225 /* Allow playback for SPDIF only */
226 rtd = snd_soc_get_pcm_runtime(card, card->dai_link);
227 rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count =
228 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0);
229 return 0;
230 }
231
232 static int fsl_xcvr_mode_get(struct snd_kcontrol *kcontrol,
233 struct snd_ctl_elem_value *ucontrol)
234 {
235 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
236 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
237
238 ucontrol->value.enumerated.item[0] = xcvr->mode;
239
240 return 0;
241 }
242
243 static const char * const fsl_xcvr_mode[] = { "SPDIF", "ARC RX", "eARC", };
244 static const struct soc_enum fsl_xcvr_mode_enum =
245 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_mode), fsl_xcvr_mode);
246 static struct snd_kcontrol_new fsl_xcvr_mode_kctl =
247 SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum,
248 fsl_xcvr_mode_get, fsl_xcvr_mode_put);
249
250 /** phy: true => phy, false => pll */
251 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
252 {
253 struct device *dev = &xcvr->pdev->dev;
254 u32 val, idx, tidx;
255 int ret;
256
257 idx = BIT(phy ? 26 : 24);
258 tidx = BIT(phy ? 27 : 25);
259
260 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF);
261 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg);
262 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data);
263 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
264
265 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val,
266 (val & idx) == ((val & tidx) >> 1),
267 10, 10000);
268 if (ret)
269 dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n",
270 phy ? "PHY" : "PLL", reg, data);
271 return ret;
272 }
273
274 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
275 {
276 struct device *dev = &xcvr->pdev->dev;
277 u32 i, div = 0, log2, val;
278 int ret;
279
280 if (!xcvr->soc_data->use_phy)
281 return 0;
282
283 for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) {
284 if (fsl_xcvr_pll_cfg[i].fout % freq == 0) {
285 div = fsl_xcvr_pll_cfg[i].fout / freq;
286 break;
287 }
288 }
289
290 if (!div || i >= ARRAY_SIZE(fsl_xcvr_pll_cfg))
291 return -EINVAL;
292
293 log2 = ilog2(div);
294
295 /* Release AI interface from reset */
296 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
297 FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
298 if (ret < 0) {
299 dev_err(dev, "Error while setting IER0: %d\n", ret);
300 return ret;
301 }
302
303 switch (xcvr->soc_data->pll_ver) {
304 case PLL_MX8MP:
305 /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */
306 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET,
307 FSL_XCVR_PLL_BANDGAP_EN_VBG, 0);
308
309 /* PLL: CTRL0: DIV_INTEGER */
310 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0);
311 /* PLL: NUMERATOR: MFN */
312 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0);
313 /* PLL: DENOMINATOR: MFD */
314 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0);
315 /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */
316 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
317 FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP, 0);
318 udelay(25);
319 /* PLL: CTRL0: Clear Hold Ring Off */
320 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR,
321 FSL_XCVR_PLL_CTRL0_HROFF, 0);
322 udelay(100);
323 if (tx) { /* TX is enabled for SPDIF only */
324 /* PLL: POSTDIV: PDIV0 */
325 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
326 FSL_XCVR_PLL_PDIVx(log2, 0), 0);
327 /* PLL: CTRL_SET: CLKMUX0_EN */
328 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
329 FSL_XCVR_PLL_CTRL0_CM0_EN, 0);
330 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */
331 /* PLL: POSTDIV: PDIV1 */
332 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
333 FSL_XCVR_PLL_PDIVx(log2, 1), 0);
334 /* PLL: CTRL_SET: CLKMUX1_EN */
335 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
336 FSL_XCVR_PLL_CTRL0_CM1_EN, 0);
337 } else { /* SPDIF / ARC RX */
338 /* PLL: POSTDIV: PDIV2 */
339 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
340 FSL_XCVR_PLL_PDIVx(log2, 2), 0);
341 /* PLL: CTRL_SET: CLKMUX2_EN */
342 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
343 FSL_XCVR_PLL_CTRL0_CM2_EN, 0);
344 }
345 break;
346 case PLL_MX95:
347 val = fsl_xcvr_pll_cfg[i].mfi << FSL_XCVR_GP_PLL_DIV_MFI_SHIFT | div;
348 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DIV, val, 0);
349 val = fsl_xcvr_pll_cfg[i].mfn << FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT;
350 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_NUMERATOR, val, 0);
351 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DENOMINATOR,
352 fsl_xcvr_pll_cfg[i].mfd, 0);
353 val = FSL_XCVR_GP_PLL_CTRL_POWERUP | FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN;
354 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_CTRL, val, 0);
355 break;
356 default:
357 dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver);
358 return -EINVAL;
359 }
360
361 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
362 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
363 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
364 FSL_XCVR_PHY_CTRL_TSDIFF_OE |
365 FSL_XCVR_PHY_CTRL_PHY_EN, 1);
366 /* PHY: CTRL2_SET: EARC_TX_MODE */
367 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
368 FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
369 } else if (!tx) { /* SPDIF / ARC RX mode */
370 if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
371 /* PHY: CTRL_SET: SPDIF_EN */
372 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
373 FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
374 else /* PHY: CTRL_SET: ARC RX setup */
375 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
376 FSL_XCVR_PHY_CTRL_PHY_EN |
377 FSL_XCVR_PHY_CTRL_RX_CM_EN |
378 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1);
379 }
380
381 dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n",
382 freq, fsl_xcvr_pll_cfg[i].fout, fsl_xcvr_pll_cfg[i].mfi,
383 fsl_xcvr_pll_cfg[i].mfn, fsl_xcvr_pll_cfg[i].mfd, div, log2);
384 return 0;
385 }
386
387 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
388 {
389 struct device *dev = &xcvr->pdev->dev;
390 int ret;
391
392 freq = xcvr->soc_data->spdif_only ? freq / 5 : freq;
393 clk_disable_unprepare(xcvr->phy_clk);
394 fsl_asoc_reparent_pll_clocks(dev, xcvr->phy_clk,
395 xcvr->pll8k_clk, xcvr->pll11k_clk, freq);
396 ret = clk_set_rate(xcvr->phy_clk, freq);
397 if (ret < 0) {
398 dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret);
399 return ret;
400 }
401 ret = clk_prepare_enable(xcvr->phy_clk);
402 if (ret) {
403 dev_err(dev, "failed to start PHY clock: %d\n", ret);
404 return ret;
405 }
406
407 if (!xcvr->soc_data->use_phy)
408 return 0;
409 /* Release AI interface from reset */
410 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
411 FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
412 if (ret < 0) {
413 dev_err(dev, "Error while setting IER0: %d\n", ret);
414 return ret;
415 }
416
417 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
418 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
419 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
420 FSL_XCVR_PHY_CTRL_TSDIFF_OE |
421 FSL_XCVR_PHY_CTRL_PHY_EN, 1);
422 /* PHY: CTRL2_SET: EARC_TX_MODE */
423 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
424 FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
425 } else { /* SPDIF mode */
426 /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */
427 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
428 FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS |
429 FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
430 }
431
432 dev_dbg(dev, "PLL Fexp: %u\n", freq);
433
434 return 0;
435 }
436
437 #define FSL_XCVR_SPDIF_RX_FREQ 175000000
438 static int fsl_xcvr_prepare(struct snd_pcm_substream *substream,
439 struct snd_soc_dai *dai)
440 {
441 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
442 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
443 u32 m_ctl = 0, v_ctl = 0;
444 u32 r = substream->runtime->rate, ch = substream->runtime->channels;
445 u32 fout = 32 * r * ch * 10;
446 int ret = 0;
447
448 switch (xcvr->mode) {
449 case FSL_XCVR_MODE_SPDIF:
450 if (xcvr->soc_data->spdif_only && tx) {
451 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
452 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM,
453 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM);
454 if (ret < 0) {
455 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret);
456 return ret;
457 }
458 }
459 fallthrough;
460 case FSL_XCVR_MODE_ARC:
461 if (tx) {
462 ret = fsl_xcvr_en_aud_pll(xcvr, fout);
463 if (ret < 0) {
464 dev_err(dai->dev, "Failed to set TX freq %u: %d\n",
465 fout, ret);
466 return ret;
467 }
468
469 ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
470 FSL_XCVR_TX_DPTH_CTRL_FRM_FMT);
471 if (ret < 0) {
472 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret);
473 return ret;
474 }
475
476 /**
477 * set SPDIF MODE - this flag is used to gate
478 * SPDIF output, useless for SPDIF RX
479 */
480 m_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
481 v_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
482 } else {
483 /**
484 * Clear RX FIFO, flip RX FIFO bits,
485 * disable eARC related HW mode detects
486 */
487 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
488 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
489 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO |
490 FSL_XCVR_RX_DPTH_CTRL_COMP |
491 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
492 if (ret < 0) {
493 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
494 return ret;
495 }
496
497 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx);
498 if (ret < 0) {
499 dev_err(dai->dev, "Failed to set RX freq %u: %d\n",
500 FSL_XCVR_SPDIF_RX_FREQ, ret);
501 return ret;
502 }
503 }
504 break;
505 case FSL_XCVR_MODE_EARC:
506 if (!tx) {
507 /** Clear RX FIFO, flip RX FIFO bits */
508 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
509 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
510 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO);
511 if (ret < 0) {
512 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
513 return ret;
514 }
515
516 /** Enable eARC related HW mode detects */
517 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR,
518 FSL_XCVR_RX_DPTH_CTRL_COMP |
519 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
520 if (ret < 0) {
521 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret);
522 return ret;
523 }
524 }
525
526 /* clear CMDC RESET */
527 m_ctl |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
528 /* set TX_RX_MODE */
529 m_ctl |= FSL_XCVR_EXT_CTRL_TX_RX_MODE;
530 v_ctl |= (tx ? FSL_XCVR_EXT_CTRL_TX_RX_MODE : 0);
531 break;
532 }
533
534 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl);
535 if (ret < 0) {
536 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret);
537 return ret;
538 }
539
540 return 0;
541 }
542
543 static int fsl_xcvr_constr(const struct snd_pcm_substream *substream,
544 const struct snd_pcm_hw_constraint_list *channels,
545 const struct snd_pcm_hw_constraint_list *rates)
546 {
547 struct snd_pcm_runtime *rt = substream->runtime;
548 int ret;
549
550 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
551 channels);
552 if (ret < 0)
553 return ret;
554
555 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE,
556 rates);
557 if (ret < 0)
558 return ret;
559
560 return 0;
561 }
562
563 static int fsl_xcvr_startup(struct snd_pcm_substream *substream,
564 struct snd_soc_dai *dai)
565 {
566 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
567 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
568 int ret = 0;
569
570 if (xcvr->streams & BIT(substream->stream)) {
571 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R");
572 return -EBUSY;
573 }
574
575 /*
576 * EDMA controller needs period size to be a multiple of
577 * tx/rx maxburst
578 */
579 if (xcvr->soc_data->use_edma)
580 snd_pcm_hw_constraint_step(substream->runtime, 0,
581 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
582 tx ? xcvr->dma_prms_tx.maxburst :
583 xcvr->dma_prms_rx.maxburst);
584
585 switch (xcvr->mode) {
586 case FSL_XCVR_MODE_SPDIF:
587 case FSL_XCVR_MODE_ARC:
588 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr,
589 &fsl_xcvr_spdif_rates_constr);
590 break;
591 case FSL_XCVR_MODE_EARC:
592 ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr,
593 &fsl_xcvr_earc_rates_constr);
594 break;
595 }
596 if (ret < 0)
597 return ret;
598
599 xcvr->streams |= BIT(substream->stream);
600
601 if (!xcvr->soc_data->spdif_only) {
602 struct snd_soc_card *card = dai->component->card;
603
604 /* Disable XCVR controls if there is stream started */
605 down_read(&card->snd_card->controls_rwsem);
606 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false);
607 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false);
608 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false);
609 up_read(&card->snd_card->controls_rwsem);
610 }
611
612 return 0;
613 }
614
615 static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream,
616 struct snd_soc_dai *dai)
617 {
618 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
619 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
620 u32 mask = 0, val = 0;
621 int ret;
622
623 xcvr->streams &= ~BIT(substream->stream);
624
625 /* Enable XCVR controls if there is no stream started */
626 if (!xcvr->streams) {
627 if (!xcvr->soc_data->spdif_only) {
628 struct snd_soc_card *card = dai->component->card;
629
630 down_read(&card->snd_card->controls_rwsem);
631 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true);
632 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
633 (xcvr->mode == FSL_XCVR_MODE_ARC));
634 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
635 (xcvr->mode == FSL_XCVR_MODE_EARC));
636 up_read(&card->snd_card->controls_rwsem);
637 }
638 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
639 FSL_XCVR_IRQ_EARC_ALL, 0);
640 if (ret < 0) {
641 dev_err(dai->dev, "Failed to set IER0: %d\n", ret);
642 return;
643 }
644
645 /* clear SPDIF MODE */
646 if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
647 mask |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
648 }
649
650 if (xcvr->mode == FSL_XCVR_MODE_EARC) {
651 /* set CMDC RESET */
652 mask |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
653 val |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
654 }
655
656 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
657 if (ret < 0) {
658 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret);
659 return;
660 }
661 }
662
663 static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
664 struct snd_soc_dai *dai)
665 {
666 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
667 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
668 unsigned long lock_flags;
669 int ret = 0;
670
671 spin_lock_irqsave(&xcvr->lock, lock_flags);
672
673 switch (cmd) {
674 case SNDRV_PCM_TRIGGER_START:
675 case SNDRV_PCM_TRIGGER_RESUME:
676 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
677 /* set DPATH RESET */
678 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
679 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx),
680 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx));
681 if (ret < 0) {
682 dev_err(dai->dev, "Failed to set DPATH RESET: %d\n", ret);
683 goto release_lock;
684 }
685
686 if (tx) {
687 switch (xcvr->mode) {
688 case FSL_XCVR_MODE_EARC:
689 /* set isr_cmdc_tx_en, w1c */
690 ret = regmap_write(xcvr->regmap,
691 FSL_XCVR_ISR_SET,
692 FSL_XCVR_ISR_CMDC_TX_EN);
693 if (ret < 0) {
694 dev_err(dai->dev, "err updating isr %d\n", ret);
695 goto release_lock;
696 }
697 fallthrough;
698 case FSL_XCVR_MODE_SPDIF:
699 ret = regmap_write(xcvr->regmap,
700 FSL_XCVR_TX_DPTH_CTRL_SET,
701 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
702 if (ret < 0) {
703 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret);
704 goto release_lock;
705 }
706 break;
707 }
708 }
709
710 /* enable DMA RD/WR */
711 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
712 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0);
713 if (ret < 0) {
714 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret);
715 goto release_lock;
716 }
717
718 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
719 FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL);
720 if (ret < 0) {
721 dev_err(dai->dev, "Error while setting IER0: %d\n", ret);
722 goto release_lock;
723 }
724
725 /* clear DPATH RESET */
726 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
727 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx),
728 0);
729 if (ret < 0) {
730 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret);
731 goto release_lock;
732 }
733
734 break;
735 case SNDRV_PCM_TRIGGER_STOP:
736 case SNDRV_PCM_TRIGGER_SUSPEND:
737 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
738 /* disable DMA RD/WR */
739 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
740 FSL_XCVR_EXT_CTRL_DMA_DIS(tx),
741 FSL_XCVR_EXT_CTRL_DMA_DIS(tx));
742 if (ret < 0) {
743 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret);
744 goto release_lock;
745 }
746
747 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
748 FSL_XCVR_IRQ_EARC_ALL, 0);
749 if (ret < 0) {
750 dev_err(dai->dev, "Failed to clear IER0: %d\n", ret);
751 goto release_lock;
752 }
753
754 if (tx) {
755 switch (xcvr->mode) {
756 case FSL_XCVR_MODE_SPDIF:
757 ret = regmap_write(xcvr->regmap,
758 FSL_XCVR_TX_DPTH_CTRL_CLR,
759 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
760 if (ret < 0) {
761 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret);
762 goto release_lock;
763 }
764 if (xcvr->soc_data->spdif_only)
765 break;
766 else
767 fallthrough;
768 case FSL_XCVR_MODE_EARC:
769 /* clear ISR_CMDC_TX_EN, W1C */
770 ret = regmap_write(xcvr->regmap,
771 FSL_XCVR_ISR_CLR,
772 FSL_XCVR_ISR_CMDC_TX_EN);
773 if (ret < 0) {
774 dev_err(dai->dev,
775 "Err updating ISR %d\n", ret);
776 goto release_lock;
777 }
778 break;
779 }
780 }
781 break;
782 default:
783 ret = -EINVAL;
784 break;
785 }
786
787 release_lock:
788 spin_unlock_irqrestore(&xcvr->lock, lock_flags);
789 return ret;
790 }
791
792 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
793 {
794 struct device *dev = &xcvr->pdev->dev;
795 const struct firmware *fw;
796 int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET;
797 u32 mask, val;
798
799 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev);
800 if (ret) {
801 dev_err(dev, "failed to request firmware.\n");
802 return ret;
803 }
804
805 rem = fw->size;
806
807 /* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */
808 if (rem > 16384) {
809 dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem);
810 release_firmware(fw);
811 return -ENOMEM;
812 }
813
814 for (page = 0; page < 10; page++) {
815 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
816 FSL_XCVR_EXT_CTRL_PAGE_MASK,
817 FSL_XCVR_EXT_CTRL_PAGE(page));
818 if (ret < 0) {
819 dev_err(dev, "FW: failed to set page %d, err=%d\n",
820 page, ret);
821 goto err_firmware;
822 }
823
824 off = page * size;
825 out = min(rem, size);
826 /* IPG clock is assumed to be running, otherwise it will hang */
827 if (out > 0) {
828 /* write firmware into code memory */
829 memcpy_toio(xcvr->ram_addr, fw->data + off, out);
830 rem -= out;
831 if (rem == 0) {
832 /* last part of firmware written */
833 /* clean remaining part of code memory page */
834 memset_io(xcvr->ram_addr + out, 0, size - out);
835 }
836 } else {
837 /* clean current page, including data memory */
838 memset_io(xcvr->ram_addr, 0, size);
839 }
840 }
841
842 err_firmware:
843 release_firmware(fw);
844 if (ret < 0)
845 return ret;
846
847 /* configure watermarks */
848 mask = FSL_XCVR_EXT_CTRL_RX_FWM_MASK | FSL_XCVR_EXT_CTRL_TX_FWM_MASK;
849 val = FSL_XCVR_EXT_CTRL_RX_FWM(FSL_XCVR_FIFO_WMK_RX);
850 val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX);
851 /* disable DMA RD/WR */
852 mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
853 val |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
854 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
855 mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK;
856 val |= FSL_XCVR_EXT_CTRL_PAGE(8);
857
858 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
859 if (ret < 0) {
860 dev_err(dev, "Failed to set watermarks: %d\n", ret);
861 return ret;
862 }
863
864 /* Store Capabilities Data Structure into Data RAM */
865 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds,
866 FSL_XCVR_CAPDS_SIZE);
867 return 0;
868 }
869
870 static int fsl_xcvr_type_iec958_info(struct snd_kcontrol *kcontrol,
871 struct snd_ctl_elem_info *uinfo)
872 {
873 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
874 uinfo->count = 1;
875
876 return 0;
877 }
878
879 static int fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol *kcontrol,
880 struct snd_ctl_elem_info *uinfo)
881 {
882 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
883 uinfo->count = sizeof_field(struct snd_aes_iec958, status);
884
885 return 0;
886 }
887
888 static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol,
889 struct snd_ctl_elem_value *ucontrol)
890 {
891 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
892 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
893
894 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24);
895
896 return 0;
897 }
898
899 static int fsl_xcvr_tx_cs_get(struct snd_kcontrol *kcontrol,
900 struct snd_ctl_elem_value *ucontrol)
901 {
902 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
903 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
904
905 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24);
906
907 return 0;
908 }
909
910 static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol,
911 struct snd_ctl_elem_value *ucontrol)
912 {
913 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
914 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
915
916 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24);
917
918 return 0;
919 }
920
921 static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = {
922 /* Channel status controller */
923 {
924 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
925 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
926 .access = SNDRV_CTL_ELEM_ACCESS_READ,
927 .info = fsl_xcvr_type_iec958_info,
928 .get = fsl_xcvr_rx_cs_get,
929 },
930 /* Capture channel status, bytes */
931 {
932 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
933 .name = "Capture Channel Status",
934 .access = SNDRV_CTL_ELEM_ACCESS_READ,
935 .info = fsl_xcvr_type_iec958_bytes_info,
936 .get = fsl_xcvr_rx_cs_get,
937 },
938 };
939
940 static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = {
941 /* Channel status controller */
942 {
943 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
944 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
945 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
946 .info = fsl_xcvr_type_iec958_info,
947 .get = fsl_xcvr_tx_cs_get,
948 .put = fsl_xcvr_tx_cs_put,
949 },
950 /* Playback channel status, bytes */
951 {
952 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
953 .name = "Playback Channel Status",
954 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
955 .info = fsl_xcvr_type_iec958_bytes_info,
956 .get = fsl_xcvr_tx_cs_get,
957 .put = fsl_xcvr_tx_cs_put,
958 },
959 };
960
961 static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai)
962 {
963 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
964
965 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx);
966
967 if (xcvr->soc_data->spdif_only)
968 xcvr->mode = FSL_XCVR_MODE_SPDIF;
969 else {
970 snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1);
971 snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1);
972 snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1);
973 }
974 snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls,
975 ARRAY_SIZE(fsl_xcvr_tx_ctls));
976 snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls,
977 ARRAY_SIZE(fsl_xcvr_rx_ctls));
978 return 0;
979 }
980
981 static const struct snd_soc_dai_ops fsl_xcvr_dai_ops = {
982 .probe = fsl_xcvr_dai_probe,
983 .prepare = fsl_xcvr_prepare,
984 .startup = fsl_xcvr_startup,
985 .shutdown = fsl_xcvr_shutdown,
986 .trigger = fsl_xcvr_trigger,
987 };
988
989 static struct snd_soc_dai_driver fsl_xcvr_dai = {
990 .ops = &fsl_xcvr_dai_ops,
991 .playback = {
992 .stream_name = "CPU-Playback",
993 .channels_min = 1,
994 .channels_max = 32,
995 .rate_min = 32000,
996 .rate_max = 1536000,
997 .rates = SNDRV_PCM_RATE_KNOT,
998 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
999 },
1000 .capture = {
1001 .stream_name = "CPU-Capture",
1002 .channels_min = 1,
1003 .channels_max = 32,
1004 .rate_min = 32000,
1005 .rate_max = 1536000,
1006 .rates = SNDRV_PCM_RATE_KNOT,
1007 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1008 },
1009 };
1010
1011 static const struct snd_soc_component_driver fsl_xcvr_comp = {
1012 .name = "fsl-xcvr-dai",
1013 .legacy_dai_naming = 1,
1014 };
1015
1016 static const struct reg_default fsl_xcvr_reg_defaults[] = {
1017 { FSL_XCVR_VERSION, 0x00000000 },
1018 { FSL_XCVR_EXT_CTRL, 0xF8204040 },
1019 { FSL_XCVR_EXT_STATUS, 0x00000000 },
1020 { FSL_XCVR_EXT_IER0, 0x00000000 },
1021 { FSL_XCVR_EXT_IER1, 0x00000000 },
1022 { FSL_XCVR_EXT_ISR, 0x00000000 },
1023 { FSL_XCVR_EXT_ISR_SET, 0x00000000 },
1024 { FSL_XCVR_EXT_ISR_CLR, 0x00000000 },
1025 { FSL_XCVR_EXT_ISR_TOG, 0x00000000 },
1026 { FSL_XCVR_IER, 0x00000000 },
1027 { FSL_XCVR_ISR, 0x00000000 },
1028 { FSL_XCVR_ISR_SET, 0x00000000 },
1029 { FSL_XCVR_ISR_CLR, 0x00000000 },
1030 { FSL_XCVR_ISR_TOG, 0x00000000 },
1031 { FSL_XCVR_CLK_CTRL, 0x0000018F },
1032 { FSL_XCVR_RX_DPTH_CTRL, 0x00040CC1 },
1033 { FSL_XCVR_RX_DPTH_CTRL_SET, 0x00040CC1 },
1034 { FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00040CC1 },
1035 { FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00040CC1 },
1036 { FSL_XCVR_RX_DPTH_CNTR_CTRL, 0x00000000 },
1037 { FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 },
1038 { FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
1039 { FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
1040 { FSL_XCVR_RX_DPTH_TSCR, 0x00000000 },
1041 { FSL_XCVR_RX_DPTH_BCR, 0x00000000 },
1042 { FSL_XCVR_RX_DPTH_BCTR, 0x00000000 },
1043 { FSL_XCVR_RX_DPTH_BCRR, 0x00000000 },
1044 { FSL_XCVR_TX_DPTH_CTRL, 0x00000000 },
1045 { FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 },
1046 { FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 },
1047 { FSL_XCVR_TX_DPTH_CTRL_TOG, 0x00000000 },
1048 { FSL_XCVR_TX_CS_DATA_0, 0x00000000 },
1049 { FSL_XCVR_TX_CS_DATA_1, 0x00000000 },
1050 { FSL_XCVR_TX_CS_DATA_2, 0x00000000 },
1051 { FSL_XCVR_TX_CS_DATA_3, 0x00000000 },
1052 { FSL_XCVR_TX_CS_DATA_4, 0x00000000 },
1053 { FSL_XCVR_TX_CS_DATA_5, 0x00000000 },
1054 { FSL_XCVR_TX_DPTH_CNTR_CTRL, 0x00000000 },
1055 { FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 },
1056 { FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
1057 { FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
1058 { FSL_XCVR_TX_DPTH_TSCR, 0x00000000 },
1059 { FSL_XCVR_TX_DPTH_BCR, 0x00000000 },
1060 { FSL_XCVR_TX_DPTH_BCTR, 0x00000000 },
1061 { FSL_XCVR_TX_DPTH_BCRR, 0x00000000 },
1062 { FSL_XCVR_DEBUG_REG_0, 0x00000000 },
1063 { FSL_XCVR_DEBUG_REG_1, 0x00000000 },
1064 };
1065
1066 static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
1067 {
1068 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1069
1070 if (!xcvr->soc_data->use_phy)
1071 if ((reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) ||
1072 reg > FSL_XCVR_TX_DPTH_BCRR)
1073 return false;
1074 switch (reg) {
1075 case FSL_XCVR_VERSION:
1076 case FSL_XCVR_EXT_CTRL:
1077 case FSL_XCVR_EXT_STATUS:
1078 case FSL_XCVR_EXT_IER0:
1079 case FSL_XCVR_EXT_IER1:
1080 case FSL_XCVR_EXT_ISR:
1081 case FSL_XCVR_EXT_ISR_SET:
1082 case FSL_XCVR_EXT_ISR_CLR:
1083 case FSL_XCVR_EXT_ISR_TOG:
1084 case FSL_XCVR_IER:
1085 case FSL_XCVR_ISR:
1086 case FSL_XCVR_ISR_SET:
1087 case FSL_XCVR_ISR_CLR:
1088 case FSL_XCVR_ISR_TOG:
1089 case FSL_XCVR_PHY_AI_CTRL:
1090 case FSL_XCVR_PHY_AI_CTRL_SET:
1091 case FSL_XCVR_PHY_AI_CTRL_CLR:
1092 case FSL_XCVR_PHY_AI_CTRL_TOG:
1093 case FSL_XCVR_PHY_AI_RDATA:
1094 case FSL_XCVR_CLK_CTRL:
1095 case FSL_XCVR_RX_DPTH_CTRL:
1096 case FSL_XCVR_RX_DPTH_CTRL_SET:
1097 case FSL_XCVR_RX_DPTH_CTRL_CLR:
1098 case FSL_XCVR_RX_DPTH_CTRL_TOG:
1099 case FSL_XCVR_RX_CS_DATA_0:
1100 case FSL_XCVR_RX_CS_DATA_1:
1101 case FSL_XCVR_RX_CS_DATA_2:
1102 case FSL_XCVR_RX_CS_DATA_3:
1103 case FSL_XCVR_RX_CS_DATA_4:
1104 case FSL_XCVR_RX_CS_DATA_5:
1105 case FSL_XCVR_RX_DPTH_CNTR_CTRL:
1106 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
1107 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
1108 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
1109 case FSL_XCVR_RX_DPTH_TSCR:
1110 case FSL_XCVR_RX_DPTH_BCR:
1111 case FSL_XCVR_RX_DPTH_BCTR:
1112 case FSL_XCVR_RX_DPTH_BCRR:
1113 case FSL_XCVR_TX_DPTH_CTRL:
1114 case FSL_XCVR_TX_DPTH_CTRL_SET:
1115 case FSL_XCVR_TX_DPTH_CTRL_CLR:
1116 case FSL_XCVR_TX_DPTH_CTRL_TOG:
1117 case FSL_XCVR_TX_CS_DATA_0:
1118 case FSL_XCVR_TX_CS_DATA_1:
1119 case FSL_XCVR_TX_CS_DATA_2:
1120 case FSL_XCVR_TX_CS_DATA_3:
1121 case FSL_XCVR_TX_CS_DATA_4:
1122 case FSL_XCVR_TX_CS_DATA_5:
1123 case FSL_XCVR_TX_DPTH_CNTR_CTRL:
1124 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
1125 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
1126 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
1127 case FSL_XCVR_TX_DPTH_TSCR:
1128 case FSL_XCVR_TX_DPTH_BCR:
1129 case FSL_XCVR_TX_DPTH_BCTR:
1130 case FSL_XCVR_TX_DPTH_BCRR:
1131 case FSL_XCVR_DEBUG_REG_0:
1132 case FSL_XCVR_DEBUG_REG_1:
1133 return true;
1134 default:
1135 return false;
1136 }
1137 }
1138
1139 static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg)
1140 {
1141 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1142
1143 if (!xcvr->soc_data->use_phy)
1144 if (reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA)
1145 return false;
1146 switch (reg) {
1147 case FSL_XCVR_EXT_CTRL:
1148 case FSL_XCVR_EXT_IER0:
1149 case FSL_XCVR_EXT_IER1:
1150 case FSL_XCVR_EXT_ISR:
1151 case FSL_XCVR_EXT_ISR_SET:
1152 case FSL_XCVR_EXT_ISR_CLR:
1153 case FSL_XCVR_EXT_ISR_TOG:
1154 case FSL_XCVR_IER:
1155 case FSL_XCVR_ISR_SET:
1156 case FSL_XCVR_ISR_CLR:
1157 case FSL_XCVR_ISR_TOG:
1158 case FSL_XCVR_PHY_AI_CTRL:
1159 case FSL_XCVR_PHY_AI_CTRL_SET:
1160 case FSL_XCVR_PHY_AI_CTRL_CLR:
1161 case FSL_XCVR_PHY_AI_CTRL_TOG:
1162 case FSL_XCVR_PHY_AI_WDATA:
1163 case FSL_XCVR_CLK_CTRL:
1164 case FSL_XCVR_RX_DPTH_CTRL:
1165 case FSL_XCVR_RX_DPTH_CTRL_SET:
1166 case FSL_XCVR_RX_DPTH_CTRL_CLR:
1167 case FSL_XCVR_RX_DPTH_CTRL_TOG:
1168 case FSL_XCVR_RX_DPTH_CNTR_CTRL:
1169 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
1170 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
1171 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
1172 case FSL_XCVR_TX_DPTH_CTRL_SET:
1173 case FSL_XCVR_TX_DPTH_CTRL_CLR:
1174 case FSL_XCVR_TX_DPTH_CTRL_TOG:
1175 case FSL_XCVR_TX_CS_DATA_0:
1176 case FSL_XCVR_TX_CS_DATA_1:
1177 case FSL_XCVR_TX_CS_DATA_2:
1178 case FSL_XCVR_TX_CS_DATA_3:
1179 case FSL_XCVR_TX_CS_DATA_4:
1180 case FSL_XCVR_TX_CS_DATA_5:
1181 case FSL_XCVR_TX_DPTH_CNTR_CTRL:
1182 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
1183 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
1184 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
1185 return true;
1186 default:
1187 return false;
1188 }
1189 }
1190
1191 static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg)
1192 {
1193 return fsl_xcvr_readable_reg(dev, reg);
1194 }
1195
1196 static const struct regmap_config fsl_xcvr_regmap_cfg = {
1197 .reg_bits = 32,
1198 .reg_stride = 4,
1199 .val_bits = 32,
1200 .max_register = FSL_XCVR_MAX_REG,
1201 .reg_defaults = fsl_xcvr_reg_defaults,
1202 .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_reg_defaults),
1203 .readable_reg = fsl_xcvr_readable_reg,
1204 .volatile_reg = fsl_xcvr_volatile_reg,
1205 .writeable_reg = fsl_xcvr_writeable_reg,
1206 .cache_type = REGCACHE_FLAT,
1207 };
1208
1209 static void reset_rx_work(struct work_struct *work)
1210 {
1211 struct fsl_xcvr *xcvr = container_of(work, struct fsl_xcvr, work_rst);
1212 struct device *dev = &xcvr->pdev->dev;
1213 unsigned long lock_flags;
1214 u32 ext_ctrl;
1215
1216 dev_dbg(dev, "reset rx path\n");
1217 spin_lock_irqsave(&xcvr->lock, lock_flags);
1218 regmap_read(xcvr->regmap, FSL_XCVR_EXT_CTRL, &ext_ctrl);
1219
1220 if (!(ext_ctrl & FSL_XCVR_EXT_CTRL_DMA_RD_DIS)) {
1221 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1222 FSL_XCVR_EXT_CTRL_DMA_RD_DIS,
1223 FSL_XCVR_EXT_CTRL_DMA_RD_DIS);
1224 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1225 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET,
1226 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET);
1227 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1228 FSL_XCVR_EXT_CTRL_DMA_RD_DIS,
1229 0);
1230 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1231 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET,
1232 0);
1233 }
1234 spin_unlock_irqrestore(&xcvr->lock, lock_flags);
1235 }
1236
1237 static irqreturn_t irq0_isr(int irq, void *devid)
1238 {
1239 struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid;
1240 struct device *dev = &xcvr->pdev->dev;
1241 struct regmap *regmap = xcvr->regmap;
1242 void __iomem *reg_ctrl, *reg_buff;
1243 u32 isr, isr_clr = 0, val, i;
1244
1245 regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr);
1246
1247 if (isr & FSL_XCVR_IRQ_NEW_CS) {
1248 dev_dbg(dev, "Received new CS block\n");
1249 isr_clr |= FSL_XCVR_IRQ_NEW_CS;
1250 if (!xcvr->soc_data->spdif_only) {
1251 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
1252 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1253 FSL_XCVR_EXT_CTRL_PAGE_MASK,
1254 FSL_XCVR_EXT_CTRL_PAGE(8));
1255
1256 /* Find updated CS buffer */
1257 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0;
1258 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0;
1259 memcpy_fromio(&val, reg_ctrl, sizeof(val));
1260 if (!val) {
1261 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1;
1262 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1;
1263 memcpy_fromio(&val, reg_ctrl, sizeof(val));
1264 }
1265
1266 if (val) {
1267 /* copy CS buffer */
1268 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff,
1269 sizeof(xcvr->rx_iec958.status));
1270 for (i = 0; i < 6; i++) {
1271 val = *(u32 *)(xcvr->rx_iec958.status + i*4);
1272 *(u32 *)(xcvr->rx_iec958.status + i*4) =
1273 bitrev32(val);
1274 }
1275 /* clear CS control register */
1276 memset_io(reg_ctrl, 0, sizeof(val));
1277 }
1278 }
1279 }
1280 if (isr & FSL_XCVR_IRQ_NEW_UD) {
1281 dev_dbg(dev, "Received new UD block\n");
1282 isr_clr |= FSL_XCVR_IRQ_NEW_UD;
1283 }
1284 if (isr & FSL_XCVR_IRQ_MUTE) {
1285 dev_dbg(dev, "HW mute bit detected\n");
1286 isr_clr |= FSL_XCVR_IRQ_MUTE;
1287 }
1288 if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) {
1289 dev_dbg(dev, "RX/TX FIFO full/empty\n");
1290 isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR;
1291 }
1292 if (isr & FSL_XCVR_IRQ_ARC_MODE) {
1293 dev_dbg(dev, "CMDC SM falls out of eARC mode\n");
1294 isr_clr |= FSL_XCVR_IRQ_ARC_MODE;
1295 }
1296 if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) {
1297 dev_dbg(dev, "DMA read request\n");
1298 isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ;
1299 }
1300 if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) {
1301 dev_dbg(dev, "DMA write request\n");
1302 isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ;
1303 }
1304 if (isr & FSL_XCVR_IRQ_CMDC_STATUS_UPD) {
1305 dev_dbg(dev, "CMDC status update\n");
1306 isr_clr |= FSL_XCVR_IRQ_CMDC_STATUS_UPD;
1307 }
1308 if (isr & FSL_XCVR_IRQ_PREAMBLE_MISMATCH) {
1309 dev_dbg(dev, "Preamble mismatch\n");
1310 isr_clr |= FSL_XCVR_IRQ_PREAMBLE_MISMATCH;
1311 }
1312 if (isr & FSL_XCVR_IRQ_UNEXP_PRE_REC) {
1313 dev_dbg(dev, "Unexpected preamble received\n");
1314 isr_clr |= FSL_XCVR_IRQ_UNEXP_PRE_REC;
1315 }
1316 if (isr & FSL_XCVR_IRQ_M_W_PRE_MISMATCH) {
1317 dev_dbg(dev, "M/W preamble mismatch\n");
1318 isr_clr |= FSL_XCVR_IRQ_M_W_PRE_MISMATCH;
1319 }
1320 if (isr & FSL_XCVR_IRQ_B_PRE_MISMATCH) {
1321 dev_dbg(dev, "B preamble mismatch\n");
1322 isr_clr |= FSL_XCVR_IRQ_B_PRE_MISMATCH;
1323 }
1324
1325 if (isr & (FSL_XCVR_IRQ_PREAMBLE_MISMATCH |
1326 FSL_XCVR_IRQ_UNEXP_PRE_REC |
1327 FSL_XCVR_IRQ_M_W_PRE_MISMATCH |
1328 FSL_XCVR_IRQ_B_PRE_MISMATCH)) {
1329 schedule_work(&xcvr->work_rst);
1330 }
1331
1332 if (isr_clr) {
1333 regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr);
1334 return IRQ_HANDLED;
1335 }
1336
1337 return IRQ_NONE;
1338 }
1339
1340 static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = {
1341 .fw_name = "imx/xcvr/xcvr-imx8mp.bin",
1342 .use_phy = true,
1343 .pll_ver = PLL_MX8MP,
1344 };
1345
1346 static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = {
1347 .spdif_only = true,
1348 .use_edma = true,
1349 };
1350
1351 static const struct fsl_xcvr_soc_data fsl_xcvr_imx95_data = {
1352 .spdif_only = true,
1353 .use_phy = true,
1354 .use_edma = true,
1355 .pll_ver = PLL_MX95,
1356 };
1357
1358 static const struct of_device_id fsl_xcvr_dt_ids[] = {
1359 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
1360 { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data},
1361 { .compatible = "fsl,imx95-xcvr", .data = &fsl_xcvr_imx95_data},
1362 { /* sentinel */ }
1363 };
1364 MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids);
1365
1366 static int fsl_xcvr_probe(struct platform_device *pdev)
1367 {
1368 struct device *dev = &pdev->dev;
1369 struct fsl_xcvr *xcvr;
1370 struct resource *rx_res, *tx_res;
1371 void __iomem *regs;
1372 int ret, irq;
1373
1374 xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL);
1375 if (!xcvr)
1376 return -ENOMEM;
1377
1378 xcvr->pdev = pdev;
1379 xcvr->soc_data = of_device_get_match_data(&pdev->dev);
1380
1381 xcvr->ipg_clk = devm_clk_get(dev, "ipg");
1382 if (IS_ERR(xcvr->ipg_clk)) {
1383 dev_err(dev, "failed to get ipg clock\n");
1384 return PTR_ERR(xcvr->ipg_clk);
1385 }
1386
1387 xcvr->phy_clk = devm_clk_get(dev, "phy");
1388 if (IS_ERR(xcvr->phy_clk)) {
1389 dev_err(dev, "failed to get phy clock\n");
1390 return PTR_ERR(xcvr->phy_clk);
1391 }
1392
1393 xcvr->spba_clk = devm_clk_get(dev, "spba");
1394 if (IS_ERR(xcvr->spba_clk)) {
1395 dev_err(dev, "failed to get spba clock\n");
1396 return PTR_ERR(xcvr->spba_clk);
1397 }
1398
1399 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg");
1400 if (IS_ERR(xcvr->pll_ipg_clk)) {
1401 dev_err(dev, "failed to get pll_ipg clock\n");
1402 return PTR_ERR(xcvr->pll_ipg_clk);
1403 }
1404
1405 fsl_asoc_get_pll_clocks(dev, &xcvr->pll8k_clk,
1406 &xcvr->pll11k_clk);
1407
1408 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram");
1409 if (IS_ERR(xcvr->ram_addr))
1410 return PTR_ERR(xcvr->ram_addr);
1411
1412 regs = devm_platform_ioremap_resource_byname(pdev, "regs");
1413 if (IS_ERR(regs))
1414 return PTR_ERR(regs);
1415
1416 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs,
1417 &fsl_xcvr_regmap_cfg);
1418 if (IS_ERR(xcvr->regmap)) {
1419 dev_err(dev, "failed to init XCVR regmap: %ld\n",
1420 PTR_ERR(xcvr->regmap));
1421 return PTR_ERR(xcvr->regmap);
1422 }
1423
1424 xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
1425 if (IS_ERR(xcvr->reset)) {
1426 dev_err(dev, "failed to get XCVR reset control\n");
1427 return PTR_ERR(xcvr->reset);
1428 }
1429
1430 /* get IRQs */
1431 irq = platform_get_irq(pdev, 0);
1432 if (irq < 0)
1433 return irq;
1434
1435 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr);
1436 if (ret) {
1437 dev_err(dev, "failed to claim IRQ0: %i\n", ret);
1438 return ret;
1439 }
1440
1441 rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo");
1442 tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo");
1443 if (!rx_res || !tx_res) {
1444 dev_err(dev, "could not find rxfifo or txfifo resource\n");
1445 return -EINVAL;
1446 }
1447 xcvr->dma_prms_rx.chan_name = "rx";
1448 xcvr->dma_prms_tx.chan_name = "tx";
1449 xcvr->dma_prms_rx.addr = rx_res->start;
1450 xcvr->dma_prms_tx.addr = tx_res->start;
1451 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX;
1452 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX;
1453
1454 platform_set_drvdata(pdev, xcvr);
1455 pm_runtime_enable(dev);
1456 regcache_cache_only(xcvr->regmap, true);
1457
1458 /*
1459 * Register platform component before registering cpu dai for there
1460 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1461 */
1462 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
1463 if (ret) {
1464 pm_runtime_disable(dev);
1465 dev_err(dev, "failed to pcm register\n");
1466 return ret;
1467 }
1468
1469 ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp,
1470 &fsl_xcvr_dai, 1);
1471 if (ret) {
1472 pm_runtime_disable(dev);
1473 dev_err(dev, "failed to register component %s\n",
1474 fsl_xcvr_comp.name);
1475 }
1476
1477 INIT_WORK(&xcvr->work_rst, reset_rx_work);
1478 spin_lock_init(&xcvr->lock);
1479 return ret;
1480 }
1481
1482 static void fsl_xcvr_remove(struct platform_device *pdev)
1483 {
1484 struct fsl_xcvr *xcvr = dev_get_drvdata(&pdev->dev);
1485
1486 cancel_work_sync(&xcvr->work_rst);
1487 pm_runtime_disable(&pdev->dev);
1488 }
1489
1490 static int fsl_xcvr_runtime_suspend(struct device *dev)
1491 {
1492 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1493 int ret;
1494
1495 if (!xcvr->soc_data->spdif_only) {
1496 /* Assert M0+ reset */
1497 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1498 FSL_XCVR_EXT_CTRL_CORE_RESET,
1499 FSL_XCVR_EXT_CTRL_CORE_RESET);
1500 if (ret < 0)
1501 dev_err(dev, "Failed to assert M0+ core: %d\n", ret);
1502 }
1503
1504 regcache_cache_only(xcvr->regmap, true);
1505
1506 clk_disable_unprepare(xcvr->spba_clk);
1507 clk_disable_unprepare(xcvr->phy_clk);
1508 clk_disable_unprepare(xcvr->pll_ipg_clk);
1509 clk_disable_unprepare(xcvr->ipg_clk);
1510
1511 return 0;
1512 }
1513
1514 static int fsl_xcvr_runtime_resume(struct device *dev)
1515 {
1516 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1517 int ret;
1518
1519 ret = reset_control_assert(xcvr->reset);
1520 if (ret < 0) {
1521 dev_err(dev, "Failed to assert M0+ reset: %d\n", ret);
1522 return ret;
1523 }
1524
1525 ret = clk_prepare_enable(xcvr->ipg_clk);
1526 if (ret) {
1527 dev_err(dev, "failed to start IPG clock.\n");
1528 return ret;
1529 }
1530
1531 ret = clk_prepare_enable(xcvr->pll_ipg_clk);
1532 if (ret) {
1533 dev_err(dev, "failed to start PLL IPG clock.\n");
1534 goto stop_ipg_clk;
1535 }
1536
1537 ret = clk_prepare_enable(xcvr->phy_clk);
1538 if (ret) {
1539 dev_err(dev, "failed to start PHY clock: %d\n", ret);
1540 goto stop_pll_ipg_clk;
1541 }
1542
1543 ret = clk_prepare_enable(xcvr->spba_clk);
1544 if (ret) {
1545 dev_err(dev, "failed to start SPBA clock.\n");
1546 goto stop_phy_clk;
1547 }
1548
1549 regcache_cache_only(xcvr->regmap, false);
1550 regcache_mark_dirty(xcvr->regmap);
1551 ret = regcache_sync(xcvr->regmap);
1552
1553 if (ret) {
1554 dev_err(dev, "failed to sync regcache.\n");
1555 goto stop_spba_clk;
1556 }
1557
1558 if (xcvr->soc_data->spdif_only)
1559 return 0;
1560
1561 ret = reset_control_deassert(xcvr->reset);
1562 if (ret) {
1563 dev_err(dev, "failed to deassert M0+ reset.\n");
1564 goto stop_spba_clk;
1565 }
1566
1567 ret = fsl_xcvr_load_firmware(xcvr);
1568 if (ret) {
1569 dev_err(dev, "failed to load firmware.\n");
1570 goto stop_spba_clk;
1571 }
1572
1573 /* Release M0+ reset */
1574 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1575 FSL_XCVR_EXT_CTRL_CORE_RESET, 0);
1576 if (ret < 0) {
1577 dev_err(dev, "M0+ core release failed: %d\n", ret);
1578 goto stop_spba_clk;
1579 }
1580
1581 /* Let M0+ core complete firmware initialization */
1582 msleep(50);
1583
1584 return 0;
1585
1586 stop_spba_clk:
1587 clk_disable_unprepare(xcvr->spba_clk);
1588 stop_phy_clk:
1589 clk_disable_unprepare(xcvr->phy_clk);
1590 stop_pll_ipg_clk:
1591 clk_disable_unprepare(xcvr->pll_ipg_clk);
1592 stop_ipg_clk:
1593 clk_disable_unprepare(xcvr->ipg_clk);
1594
1595 return ret;
1596 }
1597
1598 static const struct dev_pm_ops fsl_xcvr_pm_ops = {
1599 RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend, fsl_xcvr_runtime_resume, NULL)
1600 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1601 pm_runtime_force_resume)
1602 };
1603
1604 static struct platform_driver fsl_xcvr_driver = {
1605 .probe = fsl_xcvr_probe,
1606 .driver = {
1607 .name = "fsl,imx8mp-audio-xcvr",
1608 .pm = pm_ptr(&fsl_xcvr_pm_ops),
1609 .of_match_table = fsl_xcvr_dt_ids,
1610 },
1611 .remove = fsl_xcvr_remove,
1612 };
1613 module_platform_driver(fsl_xcvr_driver);
1614
1615 MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>");
1616 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver");
1617 MODULE_LICENSE("GPL v2");
Linux Kernel