sound/soc/sof/amd/acp-dsp-offset.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
   2 /*
   3  * This file is provided under a dual BSD/GPLv2 license. When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * Copyright(c) 2021, 2023, 2024 Advanced Micro Devices, Inc. All rights reserved.
   7  *
   8  * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
   9  */
  10
  11 #ifndef _ACP_DSP_IP_OFFSET_H
  12 #define _ACP_DSP_IP_OFFSET_H
  13
  14 /* Registers from ACP_DMA_0 block */
  15 #define ACP_DMA_CNTL_0                          0x00
  16 #define ACP_DMA_DSCR_STRT_IDX_0                 0x20
  17 #define ACP_DMA_DSCR_CNT_0                      0x40
  18 #define ACP_DMA_PRIO_0                          0x60
  19 #define ACP_DMA_CUR_DSCR_0                      0x80
  20 #define ACP_DMA_ERR_STS_0                       0xC0
  21 #define ACP_DMA_DESC_BASE_ADDR                  0xE0
  22 #define ACP_DMA_DESC_MAX_NUM_DSCR               0xE4
  23 #define ACP_DMA_CH_STS                          0xE8
  24 #define ACP_DMA_CH_GROUP                        0xEC
  25 #define ACP_DMA_CH_RST_STS                      0xF0
  26 #define ACP70_DMA_CNTL_0                        0x00
  27 #define ACP70_DMA_DSCR_STRT_IDX_0               0x28
  28 #define ACP70_DMA_DSCR_CNT_0                    0x50
  29 #define ACP70_DMA_PRIO_0                        0x78
  30 #define ACP70_DMA_CUR_DSCR_0                    0xA0
  31 #define ACP70_DMA_ERR_STS_0                     0xF0
  32 #define ACP70_DMA_DESC_BASE_ADDR                0x118
  33 #define ACP70_DMA_DESC_MAX_NUM_DSCR             0x11C
  34 #define ACP70_DMA_CH_STS                        0x120
  35 #define ACP70_DMA_CH_GROUP                      0x124
  36 #define ACP70_DMA_CH_RST_STS                    0x128
  37
  38 /* Registers from ACP_DSP_0 block */
  39 #define ACP_DSP0_RUNSTALL                       0x414
  40
  41 /* Registers from ACP_AXI2AXIATU block */
  42 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1          0xC00
  43 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1          0xC04
  44 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2          0xC08
  45 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2          0xC0C
  46 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3          0xC10
  47 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3          0xC14
  48 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4          0xC18
  49 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4          0xC1C
  50 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5          0xC20
  51 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5          0xC24
  52 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6          0xC28
  53 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6          0xC2C
  54 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7          0xC30
  55 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7          0xC34
  56 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8          0xC38
  57 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8          0xC3C
  58 #define ACPAXI2AXI_ATU_CTRL                     0xC40
  59 #define ACP_SOFT_RESET                          0x1000
  60 #define ACP_CONTROL                             0x1004
  61
  62 #define ACP3X_I2S_PIN_CONFIG                    0x1400
  63 #define ACP5X_I2S_PIN_CONFIG                    0x1400
  64 #define ACP6X_I2S_PIN_CONFIG                    0x1440
  65
  66 /* Registers offsets from ACP_PGFSM block */
  67 #define ACP3X_PGFSM_BASE                        0x141C
  68 #define ACP5X_PGFSM_BASE                        0x1424
  69 #define ACP6X_PGFSM_BASE                        0x1024
  70 #define ACP70_PGFSM_BASE                        ACP6X_PGFSM_BASE
  71 #define PGFSM_CONTROL_OFFSET                    0x0
  72 #define PGFSM_STATUS_OFFSET                     0x4
  73 #define ACP3X_CLKMUX_SEL                        0x1424
  74 #define ACP5X_CLKMUX_SEL                        0x142C
  75 #define ACP6X_CLKMUX_SEL                        0x102C
  76 #define ACP70_CLKMUX_SEL                        ACP6X_CLKMUX_SEL
  77
  78 /* Registers from ACP_INTR block */
  79 #define ACP3X_EXT_INTR_STAT                     0x1808
  80 #define ACP5X_EXT_INTR_STAT                     0x1808
  81 #define ACP6X_EXTERNAL_INTR_ENB                 0x1A00
  82 #define ACP6X_EXTERNAL_INTR_CNTL                0x1A04
  83 #define ACP6X_EXT_INTR_STAT                     0x1A0C
  84 #define ACP6X_EXT_INTR_STAT1                    0x1A10
  85 #define ACP70_EXTERNAL_INTR_ENB                 ACP6X_EXTERNAL_INTR_ENB
  86 #define ACP70_EXTERNAL_INTR_CNTL                ACP6X_EXTERNAL_INTR_CNTL
  87 #define ACP70_EXT_INTR_STAT                     ACP6X_EXT_INTR_STAT
  88 #define ACP70_EXT_INTR_STAT1                    ACP6X_EXT_INTR_STAT1
  89
  90 #define ACP3X_DSP_SW_INTR_BASE                  0x1814
  91 #define ACP5X_DSP_SW_INTR_BASE                  0x1814
  92 #define ACP6X_DSP_SW_INTR_BASE                  0x1808
  93 #define ACP70_DSP_SW_INTR_BASE                  ACP6X_DSP_SW_INTR_BASE
  94 #define DSP_SW_INTR_CNTL_OFFSET                 0x0
  95 #define DSP_SW_INTR_STAT_OFFSET                 0x4
  96 #define DSP_SW_INTR_TRIG_OFFSET                 0x8
  97 #define ACP3X_ERROR_STATUS                      0x18C4
  98 #define ACP6X_ERROR_STATUS                      0x1A4C
  99 #define ACP70_ERROR_STATUS                      ACP6X_ERROR_STATUS
 100 #define ACP3X_AXI2DAGB_SEM_0                    0x1880
 101 #define ACP5X_AXI2DAGB_SEM_0                    0x1884
 102 #define ACP6X_AXI2DAGB_SEM_0                    0x1874
 103 #define ACP70_AXI2DAGB_SEM_0                    ACP6X_AXI2DAGB_SEM_0
 104
 105 /* ACP common registers to report errors related to I2S & SoundWire interfaces */
 106 #define ACP3X_SW_I2S_ERROR_REASON               0x18C8
 107 #define ACP6X_SW0_I2S_ERROR_REASON              0x18B4
 108 #define ACP7X_SW0_I2S_ERROR_REASON              ACP6X_SW0_I2S_ERROR_REASON
 109 #define ACP_SW1_I2S_ERROR_REASON                0x1A50
 110
 111 /* Registers from ACP_SHA block */
 112 #define ACP_SHA_DSP_FW_QUALIFIER                0x1C70
 113 #define ACP_SHA_DMA_CMD                         0x1CB0
 114 #define ACP_SHA_MSG_LENGTH                      0x1CB4
 115 #define ACP_SHA_DMA_STRT_ADDR                   0x1CB8
 116 #define ACP_SHA_DMA_DESTINATION_ADDR            0x1CBC
 117 #define ACP_SHA_DMA_CMD_STS                     0x1CC0
 118 #define ACP_SHA_DMA_ERR_STATUS                  0x1CC4
 119 #define ACP_SHA_TRANSFER_BYTE_CNT               0x1CC8
 120 #define ACP_SHA_DMA_INCLUDE_HDR         0x1CCC
 121 #define ACP_SHA_PSP_ACK                         0x1C74
 122
 123 #define ACP_SCRATCH_REG_0                       0x10000
 124 #define ACP6X_DSP_FUSION_RUNSTALL               0x0644
 125 #define ACP70_DSP_FUSION_RUNSTALL               ACP6X_DSP_FUSION_RUNSTALL
 126
 127 /* Cache window registers */
 128 #define ACP_DSP0_CACHE_OFFSET0                  0x0420
 129 #define ACP_DSP0_CACHE_SIZE0                    0x0424
 130
 131 #define ACP_SW0_EN                              0x3000
 132 #define ACP_SW1_EN                              0x3C00
 133 #endif