sound/soc/tegra/tegra210_mbdrc.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * tegra210_mbdrc.h - Definitions for Tegra210 MBDRC driver
   4  *
   5  * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
   6  *
   7  */
   8
   9 #ifndef __TEGRA210_MBDRC_H__
  10 #define __TEGRA210_MBDRC_H__
  11
  12 #include <linux/platform_device.h>
  13 #include <sound/soc.h>
  14
  15 /* Register offsets from TEGRA210_MBDRC*_BASE */
  16 #define TEGRA210_MBDRC_SOFT_RESET                       0x4
  17 #define TEGRA210_MBDRC_CG                               0x8
  18 #define TEGRA210_MBDRC_STATUS                           0xc
  19 #define TEGRA210_MBDRC_CFG                              0x28
  20 #define TEGRA210_MBDRC_CHANNEL_MASK                     0x2c
  21 #define TEGRA210_MBDRC_MASTER_VOL                       0x30
  22 #define TEGRA210_MBDRC_FAST_FACTOR                      0x34
  23
  24 #define TEGRA210_MBDRC_FILTER_COUNT                     3
  25 #define TEGRA210_MBDRC_FILTER_PARAM_STRIDE              0x4
  26
  27 #define TEGRA210_MBDRC_IIR_CFG                          0x38
  28 #define TEGRA210_MBDRC_IN_ATTACK                        0x44
  29 #define TEGRA210_MBDRC_IN_RELEASE                       0x50
  30 #define TEGRA210_MBDRC_FAST_ATTACK                      0x5c
  31 #define TEGRA210_MBDRC_IN_THRESHOLD                     0x68
  32 #define TEGRA210_MBDRC_OUT_THRESHOLD                    0x74
  33 #define TEGRA210_MBDRC_RATIO_1ST                        0x80
  34 #define TEGRA210_MBDRC_RATIO_2ND                        0x8c
  35 #define TEGRA210_MBDRC_RATIO_3RD                        0x98
  36 #define TEGRA210_MBDRC_RATIO_4TH                        0xa4
  37 #define TEGRA210_MBDRC_RATIO_5TH                        0xb0
  38 #define TEGRA210_MBDRC_MAKEUP_GAIN                      0xbc
  39 #define TEGRA210_MBDRC_INIT_GAIN                        0xc8
  40 #define TEGRA210_MBDRC_GAIN_ATTACK                      0xd4
  41 #define TEGRA210_MBDRC_GAIN_RELEASE                     0xe0
  42 #define TEGRA210_MBDRC_FAST_RELEASE                     0xec
  43 #define TEGRA210_MBDRC_CFG_RAM_CTRL                     0xf8
  44 #define TEGRA210_MBDRC_CFG_RAM_DATA                     0x104
  45
  46 #define TEGRA210_MBDRC_MAX_REG                          (TEGRA210_MBDRC_CFG_RAM_DATA +          \
  47                                                          (TEGRA210_MBDRC_FILTER_PARAM_STRIDE *  \
  48                                                           (TEGRA210_MBDRC_FILTER_COUNT - 1)))
  49
  50 /* Fields for TEGRA210_MBDRC_CFG */
  51 #define TEGRA210_MBDRC_CFG_RMS_OFFSET_SHIFT             16
  52 #define TEGRA210_MBDRC_CFG_RMS_OFFSET_MASK              (0x1ff << TEGRA210_MBDRC_CFG_RMS_OFFSET_SHIFT)
  53
  54 #define TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT               14
  55 #define TEGRA210_MBDRC_CFG_PEAK_RMS_MASK                (0x1 << TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT)
  56 #define TEGRA210_MBDRC_CFG_PEAK                         (1 << TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT)
  57
  58 #define TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT       13
  59 #define TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_MASK        (0x1 << TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT)
  60 #define TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_FLEX        (1 << TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT)
  61
  62 #define TEGRA210_MBDRC_CFG_SHIFT_CTRL_SHIFT             8
  63 #define TEGRA210_MBDRC_CFG_SHIFT_CTRL_MASK              (0x1f << TEGRA210_MBDRC_CFG_SHIFT_CTRL_SHIFT)
  64
  65 #define TEGRA210_MBDRC_CFG_FRAME_SIZE_SHIFT             4
  66 #define TEGRA210_MBDRC_CFG_FRAME_SIZE_MASK              (0xf << TEGRA210_MBDRC_CFG_FRAME_SIZE_SHIFT)
  67
  68 #define TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT             0
  69 #define TEGRA210_MBDRC_CFG_MBDRC_MODE_MASK              (0x3 << TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT)
  70 #define TEGRA210_MBDRC_CFG_MBDRC_MODE_BYPASS            (0 << TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT)
  71
  72 /* Fields for TEGRA210_MBDRC_CHANNEL_MASK */
  73 #define TEGRA210_MBDRC_CHANNEL_MASK_SHIFT               0
  74 #define TEGRA210_MBDRC_CHANNEL_MASK_MASK                (0xff << TEGRA210_MBDRC_CHANNEL_MASK_SHIFT)
  75
  76 /* Fields for TEGRA210_MBDRC_MASTER_VOL */
  77 #define TEGRA210_MBDRC_MASTER_VOL_SHIFT                 23
  78 #define TEGRA210_MBDRC_MASTER_VOL_MIN                   -256
  79 #define TEGRA210_MBDRC_MASTER_VOL_MAX                   256
  80
  81 /* Fields for TEGRA210_MBDRC_FAST_FACTOR */
  82 #define TEGRA210_MBDRC_FAST_FACTOR_RELEASE_SHIFT        16
  83 #define TEGRA210_MBDRC_FAST_FACTOR_RELEASE_MASK         (0xffff << TEGRA210_MBDRC_FAST_FACTOR_RELEASE_SHIFT)
  84
  85 #define TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT         0
  86 #define TEGRA210_MBDRC_FAST_FACTOR_ATTACK_MASK          (0xffff << TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT)
  87
  88 /* Fields for TEGRA210_MBDRC_IIR_CFG */
  89 #define TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_SHIFT         0
  90 #define TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_MASK          (0xf << TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_SHIFT)
  91
  92 /* Fields for TEGRA210_MBDRC_IN_ATTACK */
  93 #define TEGRA210_MBDRC_IN_ATTACK_TC_SHIFT               0
  94 #define TEGRA210_MBDRC_IN_ATTACK_TC_MASK                (0xffffffff << TEGRA210_MBDRC_IN_ATTACK_TC_SHIFT)
  95
  96 /* Fields for TEGRA210_MBDRC_IN_RELEASE */
  97 #define TEGRA210_MBDRC_IN_RELEASE_TC_SHIFT              0
  98 #define TEGRA210_MBDRC_IN_RELEASE_TC_MASK               (0xffffffff << TEGRA210_MBDRC_IN_RELEASE_TC_SHIFT)
  99
 100 /* Fields for TEGRA210_MBDRC_FAST_ATTACK */
 101 #define TEGRA210_MBDRC_FAST_ATTACK_TC_SHIFT             0
 102 #define TEGRA210_MBDRC_FAST_ATTACK_TC_MASK              (0xffffffff << TEGRA210_MBDRC_FAST_ATTACK_TC_SHIFT)
 103
 104 /* Fields for TEGRA210_MBDRC_IN_THRESHOLD / TEGRA210_MBDRC_OUT_THRESHOLD */
 105 #define TEGRA210_MBDRC_THRESH_4TH_SHIFT                 24
 106 #define TEGRA210_MBDRC_THRESH_4TH_MASK                  (0xff << TEGRA210_MBDRC_THRESH_4TH_SHIFT)
 107
 108 #define TEGRA210_MBDRC_THRESH_3RD_SHIFT                 16
 109 #define TEGRA210_MBDRC_THRESH_3RD_MASK                  (0xff << TEGRA210_MBDRC_THRESH_3RD_SHIFT)
 110
 111 #define TEGRA210_MBDRC_THRESH_2ND_SHIFT                 8
 112 #define TEGRA210_MBDRC_THRESH_2ND_MASK                  (0xff << TEGRA210_MBDRC_THRESH_2ND_SHIFT)
 113
 114 #define TEGRA210_MBDRC_THRESH_1ST_SHIFT                 0
 115 #define TEGRA210_MBDRC_THRESH_1ST_MASK                  (0xff << TEGRA210_MBDRC_THRESH_1ST_SHIFT)
 116
 117 /* Fields for TEGRA210_MBDRC_RATIO_1ST */
 118 #define TEGRA210_MBDRC_RATIO_1ST_SHIFT                  0
 119 #define TEGRA210_MBDRC_RATIO_1ST_MASK                   (0xffff << TEGRA210_MBDRC_RATIO_1ST_SHIFT)
 120
 121 /* Fields for TEGRA210_MBDRC_RATIO_2ND */
 122 #define TEGRA210_MBDRC_RATIO_2ND_SHIFT                  0
 123 #define TEGRA210_MBDRC_RATIO_2ND_MASK                   (0xffff << TEGRA210_MBDRC_RATIO_2ND_SHIFT)
 124
 125 /* Fields for TEGRA210_MBDRC_RATIO_3RD */
 126 #define TEGRA210_MBDRC_RATIO_3RD_SHIFT                  0
 127 #define TEGRA210_MBDRC_RATIO_3RD_MASK                   (0xffff << TEGRA210_MBDRC_RATIO_3RD_SHIFT)
 128
 129 /* Fields for TEGRA210_MBDRC_RATIO_4TH */
 130 #define TEGRA210_MBDRC_RATIO_4TH_SHIFT                  0
 131 #define TEGRA210_MBDRC_RATIO_4TH_MASK                   (0xffff << TEGRA210_MBDRC_RATIO_4TH_SHIFT)
 132
 133 /* Fields for TEGRA210_MBDRC_RATIO_5TH */
 134 #define TEGRA210_MBDRC_RATIO_5TH_SHIFT                  0
 135 #define TEGRA210_MBDRC_RATIO_5TH_MASK                   (0xffff << TEGRA210_MBDRC_RATIO_5TH_SHIFT)
 136
 137 /* Fields for TEGRA210_MBDRC_MAKEUP_GAIN */
 138 #define TEGRA210_MBDRC_MAKEUP_GAIN_SHIFT                0
 139 #define TEGRA210_MBDRC_MAKEUP_GAIN_MASK                 (0x3f << TEGRA210_MBDRC_MAKEUP_GAIN_SHIFT)
 140
 141 /* Fields for TEGRA210_MBDRC_INIT_GAIN */
 142 #define TEGRA210_MBDRC_INIT_GAIN_SHIFT                  0
 143 #define TEGRA210_MBDRC_INIT_GAIN_MASK                   (0xffffffff << TEGRA210_MBDRC_INIT_GAIN_SHIFT)
 144
 145 /* Fields for TEGRA210_MBDRC_GAIN_ATTACK */
 146 #define TEGRA210_MBDRC_GAIN_ATTACK_SHIFT                0
 147 #define TEGRA210_MBDRC_GAIN_ATTACK_MASK                 (0xffffffff << TEGRA210_MBDRC_GAIN_ATTACK_SHIFT)
 148
 149 /* Fields for TEGRA210_MBDRC_GAIN_RELEASE */
 150 #define TEGRA210_MBDRC_GAIN_RELEASE_SHIFT               0
 151 #define TEGRA210_MBDRC_GAIN_RELEASE_MASK                (0xffffffff << TEGRA210_MBDRC_GAIN_RELEASE_SHIFT)
 152
 153 /* Fields for TEGRA210_MBDRC_FAST_RELEASE */
 154 #define TEGRA210_MBDRC_FAST_RELEASE_SHIFT               0
 155 #define TEGRA210_MBDRC_FAST_RELEASE_MASK                (0xffffffff << TEGRA210_MBDRC_FAST_RELEASE_SHIFT)
 156
 157 #define TEGRA210_MBDRC_RAM_CTRL_RW_READ                 0
 158 #define TEGRA210_MBDRC_RAM_CTRL_RW_WRITE                (1 << 14)
 159 #define TEGRA210_MBDRC_RAM_CTRL_ADDR_INIT_EN            (1 << 13)
 160 #define TEGRA210_MBDRC_RAM_CTRL_SEQ_ACCESS_EN           (1 << 12)
 161 #define TEGRA210_MBDRC_RAM_CTRL_RAM_ADDR_MASK           0x1ff
 162
 163 /*
 164  * Order and size of each structure element for following structures should not
 165  * be altered size order of elements and their size are based on PEQ co-eff ram
 166  * and shift ram layout.
 167  */
 168 #define TEGRA210_MBDRC_THRESHOLD_NUM                            4
 169 #define TEGRA210_MBDRC_RATIO_NUM                                (TEGRA210_MBDRC_THRESHOLD_NUM + 1)
 170 #define TEGRA210_MBDRC_MAX_BIQUAD_STAGES                        8
 171
 172 /* Order of these enums are same as the order of band specific hw registers */
 173 enum {
 174         MBDRC_LOW_BAND,
 175         MBDRC_MID_BAND,
 176         MBDRC_HIGH_BAND,
 177         MBDRC_NUM_BAND,
 178 };
 179
 180 struct tegra210_mbdrc_band_params {
 181         u32 band;
 182         u32 iir_stages;
 183         u32 in_attack_tc;
 184         u32 in_release_tc;
 185         u32 fast_attack_tc;
 186         u32 in_threshold[TEGRA210_MBDRC_THRESHOLD_NUM];
 187         u32 out_threshold[TEGRA210_MBDRC_THRESHOLD_NUM];
 188         u32 ratio[TEGRA210_MBDRC_RATIO_NUM];
 189         u32 makeup_gain;
 190         u32 gain_init;
 191         u32 gain_attack_tc;
 192         u32 gain_release_tc;
 193         u32 fast_release_tc;
 194         /* For biquad_params[][5] order of coeff is b0, b1, a0, a1, a2 */
 195         u32 biquad_params[TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5];
 196 };
 197
 198 struct tegra210_mbdrc_config {
 199         unsigned int mode;
 200         unsigned int rms_off;
 201         unsigned int peak_rms_mode;
 202         unsigned int filter_structure;
 203         unsigned int shift_ctrl;
 204         unsigned int frame_size;
 205         unsigned int channel_mask;
 206         unsigned int fa_factor; /* Fast attack factor */
 207         unsigned int fr_factor; /* Fast release factor */
 208         struct tegra210_mbdrc_band_params band_params[MBDRC_NUM_BAND];
 209 };
 210
 211 int tegra210_mbdrc_regmap_init(struct platform_device *pdev);
 212 int tegra210_mbdrc_component_init(struct snd_soc_component *cmpnt);
 213 int tegra210_mbdrc_hw_params(struct snd_soc_component *cmpnt);
 214
 215 #endif