drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 /*
   4  * Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/mod_devicetable.h>
   9 #include <linux/module.h>
  10 #include <linux/platform_device.h>
  11 #include <drm/bridge/dw_hdmi.h>
  12 #include <drm/drm_modes.h>
  13
  14 struct imx8mp_hdmi {
  15         struct dw_hdmi_plat_data plat_data;
  16         struct dw_hdmi *dw_hdmi;
  17         struct clk *pixclk;
  18 };
  19
  20 static enum drm_mode_status
  21 imx8mp_hdmi_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
  22                        const struct drm_display_info *info,
  23                        const struct drm_display_mode *mode)
  24 {
  25         struct imx8mp_hdmi *hdmi = (struct imx8mp_hdmi *)data;
  26         long round_rate;
  27
  28         if (mode->clock < 13500)
  29                 return MODE_CLOCK_LOW;
  30
  31         if (mode->clock > 297000)
  32                 return MODE_CLOCK_HIGH;
  33
  34         round_rate = clk_round_rate(hdmi->pixclk, mode->clock * 1000);
  35         /* imx8mp's pixel clock generator (fsl-samsung-hdmi) cannot generate
  36          * all possible frequencies, so allow some tolerance to support more
  37          * modes.
  38          * Allow 0.5% difference allowed in various standards (VESA, CEA861)
  39          * 0.5% = 5/1000 tolerance (mode->clock is 1/1000)
  40          */
  41         if (abs(round_rate - mode->clock * 1000) > mode->clock * 5)
  42                 return MODE_CLOCK_RANGE;
  43
  44         /* We don't support double-clocked and Interlaced modes */
  45         if ((mode->flags & DRM_MODE_FLAG_DBLCLK) ||
  46             (mode->flags & DRM_MODE_FLAG_INTERLACE))
  47                 return MODE_BAD;
  48
  49         return MODE_OK;
  50 }
  51
  52 static int imx8mp_hdmi_phy_init(struct dw_hdmi *dw_hdmi, void *data,
  53                                 const struct drm_display_info *display,
  54                                 const struct drm_display_mode *mode)
  55 {
  56         return 0;
  57 }
  58
  59 static void imx8mp_hdmi_phy_disable(struct dw_hdmi *dw_hdmi, void *data)
  60 {
  61 }
  62
  63 static void im8mp_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
  64 {
  65         /*
  66          * Just release PHY core from reset, all other power management is done
  67          * by the PHY driver.
  68          */
  69         dw_hdmi_phy_gen1_reset(hdmi);
  70
  71         dw_hdmi_phy_setup_hpd(hdmi, data);
  72 }
  73
  74 static const struct dw_hdmi_phy_ops imx8mp_hdmi_phy_ops = {
  75         .init           = imx8mp_hdmi_phy_init,
  76         .disable        = imx8mp_hdmi_phy_disable,
  77         .setup_hpd      = im8mp_hdmi_phy_setup_hpd,
  78         .read_hpd       = dw_hdmi_phy_read_hpd,
  79         .update_hpd     = dw_hdmi_phy_update_hpd,
  80 };
  81
  82 static int imx8mp_dw_hdmi_probe(struct platform_device *pdev)
  83 {
  84         struct device *dev = &pdev->dev;
  85         struct dw_hdmi_plat_data *plat_data;
  86         struct imx8mp_hdmi *hdmi;
  87
  88         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
  89         if (!hdmi)
  90                 return -ENOMEM;
  91
  92         plat_data = &hdmi->plat_data;
  93
  94         hdmi->pixclk = devm_clk_get(dev, "pix");
  95         if (IS_ERR(hdmi->pixclk))
  96                 return dev_err_probe(dev, PTR_ERR(hdmi->pixclk),
  97                                      "Unable to get pixel clock\n");
  98
  99         plat_data->mode_valid = imx8mp_hdmi_mode_valid;
 100         plat_data->phy_ops = &imx8mp_hdmi_phy_ops;
 101         plat_data->phy_name = "SAMSUNG HDMI TX PHY";
 102         plat_data->priv_data = hdmi;
 103         plat_data->phy_force_vendor = true;
 104
 105         hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data);
 106         if (IS_ERR(hdmi->dw_hdmi))
 107                 return PTR_ERR(hdmi->dw_hdmi);
 108
 109         platform_set_drvdata(pdev, hdmi);
 110
 111         return 0;
 112 }
 113
 114 static void imx8mp_dw_hdmi_remove(struct platform_device *pdev)
 115 {
 116         struct imx8mp_hdmi *hdmi = platform_get_drvdata(pdev);
 117
 118         dw_hdmi_remove(hdmi->dw_hdmi);
 119 }
 120
 121 static int imx8mp_dw_hdmi_pm_suspend(struct device *dev)
 122 {
 123         return 0;
 124 }
 125
 126 static int imx8mp_dw_hdmi_pm_resume(struct device *dev)
 127 {
 128         struct imx8mp_hdmi *hdmi = dev_get_drvdata(dev);
 129
 130         dw_hdmi_resume(hdmi->dw_hdmi);
 131
 132         return 0;
 133 }
 134
 135 static const struct dev_pm_ops imx8mp_dw_hdmi_pm_ops = {
 136         SYSTEM_SLEEP_PM_OPS(imx8mp_dw_hdmi_pm_suspend, imx8mp_dw_hdmi_pm_resume)
 137 };
 138
 139 static const struct of_device_id imx8mp_dw_hdmi_of_table[] = {
 140         { .compatible = "fsl,imx8mp-hdmi-tx" },
 141         { /* Sentinel */ }
 142 };
 143 MODULE_DEVICE_TABLE(of, imx8mp_dw_hdmi_of_table);
 144
 145 static struct platform_driver imx8mp_dw_hdmi_platform_driver = {
 146         .probe          = imx8mp_dw_hdmi_probe,
 147         .remove         = imx8mp_dw_hdmi_remove,
 148         .driver         = {
 149                 .name   = "imx8mp-dw-hdmi-tx",
 150                 .of_match_table = imx8mp_dw_hdmi_of_table,
 151                 .pm = pm_ptr(&imx8mp_dw_hdmi_pm_ops),
 152         },
 153 };
 154
 155 module_platform_driver(imx8mp_dw_hdmi_platform_driver);
 156
 157 MODULE_DESCRIPTION("i.MX8MP HDMI encoder driver");
 158 MODULE_LICENSE("GPL");