Get rid of 'remove_new' relic from platform driver struct
[linux.git] / drivers / gpu / drm / mediatek / mtk_dpi_regs.h
blob62bd4931b344e39d92b5758d6699cc6b7f446f65
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Jie Qiu <jie.qiu@mediatek.com>
5 */
6 #ifndef __MTK_DPI_REGS_H
7 #define __MTK_DPI_REGS_H
9 #define DPI_EN 0x00
10 #define EN BIT(0)
12 #define DPI_RET 0x04
13 #define RST BIT(0)
15 #define DPI_INTEN 0x08
16 #define INT_VSYNC_EN BIT(0)
17 #define INT_VDE_EN BIT(1)
18 #define INT_UNDERFLOW_EN BIT(2)
20 #define DPI_INTSTA 0x0C
21 #define INT_VSYNC_STA BIT(0)
22 #define INT_VDE_STA BIT(1)
23 #define INT_UNDERFLOW_STA BIT(2)
25 #define DPI_CON 0x10
26 #define BG_ENABLE BIT(0)
27 #define IN_RB_SWAP BIT(1)
28 #define INTL_EN BIT(2)
29 #define TDFP_EN BIT(3)
30 #define CLPF_EN BIT(4)
31 #define YUV422_EN BIT(5)
32 #define CSC_ENABLE BIT(6)
33 #define R601_SEL BIT(7)
34 #define EMBSYNC_EN BIT(8)
35 #define VS_LODD_EN BIT(16)
36 #define VS_LEVEN_EN BIT(17)
37 #define VS_RODD_EN BIT(18)
38 #define VS_REVEN BIT(19)
39 #define FAKE_DE_LODD BIT(20)
40 #define FAKE_DE_LEVEN BIT(21)
41 #define FAKE_DE_RODD BIT(22)
42 #define FAKE_DE_REVEN BIT(23)
43 #define DPINTF_YUV422_EN BIT(24)
44 #define DPINTF_CSC_ENABLE BIT(26)
45 #define DPINTF_INPUT_2P_EN BIT(29)
47 #define DPI_OUTPUT_SETTING 0x14
48 #define CH_SWAP 0
49 #define DPINTF_CH_SWAP 1
50 #define CH_SWAP_MASK (0x7 << 0)
51 #define SWAP_RGB 0x00
52 #define SWAP_GBR 0x01
53 #define SWAP_BRG 0x02
54 #define SWAP_RBG 0x03
55 #define SWAP_GRB 0x04
56 #define SWAP_BGR 0x05
57 #define BIT_SWAP BIT(3)
58 #define B_MASK BIT(4)
59 #define G_MASK BIT(5)
60 #define R_MASK BIT(6)
61 #define DE_MASK BIT(8)
62 #define HS_MASK BIT(9)
63 #define VS_MASK BIT(10)
64 #define DE_POL BIT(12)
65 #define HSYNC_POL BIT(13)
66 #define VSYNC_POL BIT(14)
67 #define CK_POL BIT(15)
68 #define OEN_OFF BIT(16)
69 #define EDGE_SEL BIT(17)
70 #define OUT_BIT 18
71 #define OUT_BIT_MASK (0x3 << 18)
72 #define OUT_BIT_8 0x00
73 #define OUT_BIT_10 0x01
74 #define OUT_BIT_12 0x02
75 #define OUT_BIT_16 0x03
76 #define YC_MAP 20
77 #define YC_MAP_MASK (0x7 << 20)
78 #define YC_MAP_RGB 0x00
79 #define YC_MAP_CYCY 0x04
80 #define YC_MAP_YCYC 0x05
81 #define YC_MAP_CY 0x06
82 #define YC_MAP_YC 0x07
84 #define DPI_SIZE 0x18
85 #define HSIZE 0
86 #define HSIZE_MASK (0x1FFF << 0)
87 #define DPINTF_HSIZE_MASK (0xFFFF << 0)
88 #define VSIZE 16
89 #define VSIZE_MASK (0x1FFF << 16)
90 #define DPINTF_VSIZE_MASK (0xFFFF << 16)
92 #define DPI_DDR_SETTING 0x1C
93 #define DDR_EN BIT(0)
94 #define DDDR_SEL BIT(1)
95 #define DDR_4PHASE BIT(2)
96 #define DDR_WIDTH (0x3 << 4)
97 #define DDR_PAD_MODE (0x1 << 8)
99 #define DPI_TGEN_HWIDTH 0x20
100 #define HPW 0
101 #define HPW_MASK (0xFFF << 0)
102 #define DPINTF_HPW_MASK (0xFFFF << 0)
104 #define DPI_TGEN_HPORCH 0x24
105 #define HBP 0
106 #define HBP_MASK (0xFFF << 0)
107 #define DPINTF_HBP_MASK (0xFFFF << 0)
108 #define HFP 16
109 #define HFP_MASK (0xFFF << 16)
110 #define DPINTF_HFP_MASK (0xFFFF << 16)
112 #define DPI_TGEN_VWIDTH 0x28
113 #define DPI_TGEN_VPORCH 0x2C
115 #define VSYNC_WIDTH_SHIFT 0
116 #define VSYNC_WIDTH_MASK (0xFFF << 0)
117 #define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0)
118 #define VSYNC_HALF_LINE_SHIFT 16
119 #define VSYNC_HALF_LINE_MASK BIT(16)
120 #define VSYNC_BACK_PORCH_SHIFT 0
121 #define VSYNC_BACK_PORCH_MASK (0xFFF << 0)
122 #define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0)
123 #define VSYNC_FRONT_PORCH_SHIFT 16
124 #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16)
125 #define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16)
127 #define DPI_BG_HCNTL 0x30
128 #define BG_RIGHT (0x1FFF << 0)
129 #define BG_LEFT (0x1FFF << 16)
131 #define DPI_BG_VCNTL 0x34
132 #define BG_BOT (0x1FFF << 0)
133 #define BG_TOP (0x1FFF << 16)
135 #define DPI_BG_COLOR 0x38
136 #define BG_B (0xF << 0)
137 #define BG_G (0xF << 8)
138 #define BG_R (0xF << 16)
140 #define DPI_FIFO_CTL 0x3C
141 #define FIFO_VALID_SET (0x1F << 0)
142 #define FIFO_RST_SEL (0x1 << 8)
144 #define DPI_STATUS 0x40
145 #define VCOUNTER (0x1FFF << 0)
146 #define DPI_BUSY BIT(16)
147 #define OUTEN BIT(17)
148 #define FIELD BIT(20)
149 #define TDLR BIT(21)
151 #define DPI_TMODE 0x44
152 #define DPI_OEN_ON BIT(0)
154 #define DPI_CHECKSUM 0x48
155 #define DPI_CHECKSUM_MASK (0xFFFFFF << 0)
156 #define DPI_CHECKSUM_READY BIT(30)
157 #define DPI_CHECKSUM_EN BIT(31)
159 #define DPI_DUMMY 0x50
160 #define DPI_DUMMY_MASK (0xFFFFFFFF << 0)
162 #define DPI_TGEN_VWIDTH_LEVEN 0x68
163 #define DPI_TGEN_VPORCH_LEVEN 0x6C
164 #define DPI_TGEN_VWIDTH_RODD 0x70
165 #define DPI_TGEN_VPORCH_RODD 0x74
166 #define DPI_TGEN_VWIDTH_REVEN 0x78
167 #define DPI_TGEN_VPORCH_REVEN 0x7C
169 #define DPI_ESAV_VTIMING_LODD 0x80
170 #define ESAV_VOFST_LODD (0xFFF << 0)
171 #define ESAV_VWID_LODD (0xFFF << 16)
173 #define DPI_ESAV_VTIMING_LEVEN 0x84
174 #define ESAV_VOFST_LEVEN (0xFFF << 0)
175 #define ESAV_VWID_LEVEN (0xFFF << 16)
177 #define DPI_ESAV_VTIMING_RODD 0x88
178 #define ESAV_VOFST_RODD (0xFFF << 0)
179 #define ESAV_VWID_RODD (0xFFF << 16)
181 #define DPI_ESAV_VTIMING_REVEN 0x8C
182 #define ESAV_VOFST_REVEN (0xFFF << 0)
183 #define ESAV_VWID_REVEN (0xFFF << 16)
185 #define DPI_ESAV_FTIMING 0x90
186 #define ESAV_FOFST_ODD (0xFFF << 0)
187 #define ESAV_FOFST_EVEN (0xFFF << 16)
189 #define DPI_CLPF_SETTING 0x94
190 #define CLPF_TYPE (0x3 << 0)
191 #define ROUND_EN BIT(4)
193 #define DPI_Y_LIMIT 0x98
194 #define Y_LIMINT_BOT 0
195 #define Y_LIMINT_BOT_MASK (0xFFF << 0)
196 #define Y_LIMINT_TOP 16
197 #define Y_LIMINT_TOP_MASK (0xFFF << 16)
199 #define DPI_C_LIMIT 0x9C
200 #define C_LIMIT_BOT 0
201 #define C_LIMIT_BOT_MASK (0xFFF << 0)
202 #define C_LIMIT_TOP 16
203 #define C_LIMIT_TOP_MASK (0xFFF << 16)
205 #define DPI_YUV422_SETTING 0xA0
206 #define UV_SWAP BIT(0)
207 #define CR_DELSEL BIT(4)
208 #define CB_DELSEL BIT(5)
209 #define Y_DELSEL BIT(6)
210 #define DE_DELSEL BIT(7)
212 #define DPI_EMBSYNC_SETTING 0xA4
213 #define EMBSYNC_R_CR_EN BIT(0)
214 #define EMPSYNC_G_Y_EN BIT(1)
215 #define EMPSYNC_B_CB_EN BIT(2)
216 #define ESAV_F_INV BIT(4)
217 #define ESAV_V_INV BIT(5)
218 #define ESAV_H_INV BIT(6)
219 #define ESAV_CODE_MAN BIT(8)
220 #define VS_OUT_SEL (0x7 << 12)
222 #define DPI_ESAV_CODE_SET0 0xA8
223 #define ESAV_CODE0 (0xFFF << 0)
224 #define ESAV_CODE1 (0xFFF << 16)
226 #define DPI_ESAV_CODE_SET1 0xAC
227 #define ESAV_CODE2 (0xFFF << 0)
228 #define ESAV_CODE3_MSB BIT(16)
230 #define EDGE_SEL_EN BIT(5)
231 #define H_FRE_2N BIT(25)
233 #define DPI_MATRIX_SET 0xB4
234 #define INT_MATRIX_SEL_MASK GENMASK(4, 0)
235 #define MATRIX_SEL_RGB_TO_JPEG 0
236 #define MATRIX_SEL_RGB_TO_BT601 2
238 #endif /* __MTK_DPI_REGS_H */