drivers/gpu/drm/panel/panel-simple.c

   1 /*
   2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/gpio/consumer.h>
  26 #include <linux/i2c.h>
  27 #include <linux/media-bus-format.h>
  28 #include <linux/module.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/regulator/consumer.h>
  33
  34 #include <video/display_timing.h>
  35 #include <video/of_display_timing.h>
  36 #include <video/videomode.h>
  37
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_device.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_mipi_dsi.h>
  42 #include <drm/drm_panel.h>
  43 #include <drm/drm_of.h>
  44
  45 /**
  46  * struct panel_desc - Describes a simple panel.
  47  */
  48 struct panel_desc {
  49         /**
  50          * @modes: Pointer to array of fixed modes appropriate for this panel.
  51          *
  52          * If only one mode then this can just be the address of the mode.
  53          * NOTE: cannot be used with "timings" and also if this is specified
  54          * then you cannot override the mode in the device tree.
  55          */
  56         const struct drm_display_mode *modes;
  57
  58         /** @num_modes: Number of elements in modes array. */
  59         unsigned int num_modes;
  60
  61         /**
  62          * @timings: Pointer to array of display timings
  63          *
  64          * NOTE: cannot be used with "modes" and also these will be used to
  65          * validate a device tree override if one is present.
  66          */
  67         const struct display_timing *timings;
  68
  69         /** @num_timings: Number of elements in timings array. */
  70         unsigned int num_timings;
  71
  72         /** @bpc: Bits per color. */
  73         unsigned int bpc;
  74
  75         /** @size: Structure containing the physical size of this panel. */
  76         struct {
  77                 /**
  78                  * @size.width: Width (in mm) of the active display area.
  79                  */
  80                 unsigned int width;
  81
  82                 /**
  83                  * @size.height: Height (in mm) of the active display area.
  84                  */
  85                 unsigned int height;
  86         } size;
  87
  88         /** @delay: Structure containing various delay values for this panel. */
  89         struct {
  90                 /**
  91                  * @delay.prepare: Time for the panel to become ready.
  92                  *
  93                  * The time (in milliseconds) that it takes for the panel to
  94                  * become ready and start receiving video data
  95                  */
  96                 unsigned int prepare;
  97
  98                 /**
  99                  * @delay.enable: Time for the panel to display a valid frame.
 100                  *
 101                  * The time (in milliseconds) that it takes for the panel to
 102                  * display the first valid frame after starting to receive
 103                  * video data.
 104                  */
 105                 unsigned int enable;
 106
 107                 /**
 108                  * @delay.disable: Time for the panel to turn the display off.
 109                  *
 110                  * The time (in milliseconds) that it takes for the panel to
 111                  * turn the display off (no content is visible).
 112                  */
 113                 unsigned int disable;
 114
 115                 /**
 116                  * @delay.unprepare: Time to power down completely.
 117                  *
 118                  * The time (in milliseconds) that it takes for the panel
 119                  * to power itself down completely.
 120                  *
 121                  * This time is used to prevent a future "prepare" from
 122                  * starting until at least this many milliseconds has passed.
 123                  * If at prepare time less time has passed since unprepare
 124                  * finished, the driver waits for the remaining time.
 125                  */
 126                 unsigned int unprepare;
 127         } delay;
 128
 129         /** @bus_format: See MEDIA_BUS_FMT_... defines. */
 130         u32 bus_format;
 131
 132         /** @bus_flags: See DRM_BUS_FLAG_... defines. */
 133         u32 bus_flags;
 134
 135         /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
 136         int connector_type;
 137 };
 138
 139 struct panel_simple {
 140         struct drm_panel base;
 141
 142         ktime_t unprepared_time;
 143
 144         const struct panel_desc *desc;
 145
 146         struct regulator *supply;
 147         struct i2c_adapter *ddc;
 148
 149         struct gpio_desc *enable_gpio;
 150
 151         const struct drm_edid *drm_edid;
 152
 153         struct drm_display_mode override_mode;
 154
 155         enum drm_panel_orientation orientation;
 156 };
 157
 158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
 159 {
 160         return container_of(panel, struct panel_simple, base);
 161 }
 162
 163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
 164                                                    struct drm_connector *connector)
 165 {
 166         struct drm_display_mode *mode;
 167         unsigned int i, num = 0;
 168
 169         for (i = 0; i < panel->desc->num_timings; i++) {
 170                 const struct display_timing *dt = &panel->desc->timings[i];
 171                 struct videomode vm;
 172
 173                 videomode_from_timing(dt, &vm);
 174                 mode = drm_mode_create(connector->dev);
 175                 if (!mode) {
 176                         dev_err(panel->base.dev, "failed to add mode %ux%u\n",
 177                                 dt->hactive.typ, dt->vactive.typ);
 178                         continue;
 179                 }
 180
 181                 drm_display_mode_from_videomode(&vm, mode);
 182
 183                 mode->type |= DRM_MODE_TYPE_DRIVER;
 184
 185                 if (panel->desc->num_timings == 1)
 186                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 187
 188                 drm_mode_probed_add(connector, mode);
 189                 num++;
 190         }
 191
 192         return num;
 193 }
 194
 195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
 196                                                    struct drm_connector *connector)
 197 {
 198         struct drm_display_mode *mode;
 199         unsigned int i, num = 0;
 200
 201         for (i = 0; i < panel->desc->num_modes; i++) {
 202                 const struct drm_display_mode *m = &panel->desc->modes[i];
 203
 204                 mode = drm_mode_duplicate(connector->dev, m);
 205                 if (!mode) {
 206                         dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
 207                                 m->hdisplay, m->vdisplay,
 208                                 drm_mode_vrefresh(m));
 209                         continue;
 210                 }
 211
 212                 mode->type |= DRM_MODE_TYPE_DRIVER;
 213
 214                 if (panel->desc->num_modes == 1)
 215                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 216
 217                 drm_mode_set_name(mode);
 218
 219                 drm_mode_probed_add(connector, mode);
 220                 num++;
 221         }
 222
 223         return num;
 224 }
 225
 226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
 227                                            struct drm_connector *connector)
 228 {
 229         struct drm_display_mode *mode;
 230         bool has_override = panel->override_mode.type;
 231         unsigned int num = 0;
 232
 233         if (!panel->desc)
 234                 return 0;
 235
 236         if (has_override) {
 237                 mode = drm_mode_duplicate(connector->dev,
 238                                           &panel->override_mode);
 239                 if (mode) {
 240                         drm_mode_probed_add(connector, mode);
 241                         num = 1;
 242                 } else {
 243                         dev_err(panel->base.dev, "failed to add override mode\n");
 244                 }
 245         }
 246
 247         /* Only add timings if override was not there or failed to validate */
 248         if (num == 0 && panel->desc->num_timings)
 249                 num = panel_simple_get_timings_modes(panel, connector);
 250
 251         /*
 252          * Only add fixed modes if timings/override added no mode.
 253          *
 254          * We should only ever have either the display timings specified
 255          * or a fixed mode. Anything else is rather bogus.
 256          */
 257         WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
 258         if (num == 0)
 259                 num = panel_simple_get_display_modes(panel, connector);
 260
 261         connector->display_info.bpc = panel->desc->bpc;
 262         connector->display_info.width_mm = panel->desc->size.width;
 263         connector->display_info.height_mm = panel->desc->size.height;
 264         if (panel->desc->bus_format)
 265                 drm_display_info_set_bus_formats(&connector->display_info,
 266                                                  &panel->desc->bus_format, 1);
 267         connector->display_info.bus_flags = panel->desc->bus_flags;
 268
 269         return num;
 270 }
 271
 272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
 273 {
 274         ktime_t now_ktime, min_ktime;
 275
 276         if (!min_ms)
 277                 return;
 278
 279         min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
 280         now_ktime = ktime_get_boottime();
 281
 282         if (ktime_before(now_ktime, min_ktime))
 283                 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
 284 }
 285
 286 static int panel_simple_disable(struct drm_panel *panel)
 287 {
 288         struct panel_simple *p = to_panel_simple(panel);
 289
 290         if (p->desc->delay.disable)
 291                 msleep(p->desc->delay.disable);
 292
 293         return 0;
 294 }
 295
 296 static int panel_simple_suspend(struct device *dev)
 297 {
 298         struct panel_simple *p = dev_get_drvdata(dev);
 299
 300         gpiod_set_value_cansleep(p->enable_gpio, 0);
 301         regulator_disable(p->supply);
 302         p->unprepared_time = ktime_get_boottime();
 303
 304         drm_edid_free(p->drm_edid);
 305         p->drm_edid = NULL;
 306
 307         return 0;
 308 }
 309
 310 static int panel_simple_unprepare(struct drm_panel *panel)
 311 {
 312         int ret;
 313
 314         pm_runtime_mark_last_busy(panel->dev);
 315         ret = pm_runtime_put_autosuspend(panel->dev);
 316         if (ret < 0)
 317                 return ret;
 318
 319         return 0;
 320 }
 321
 322 static int panel_simple_resume(struct device *dev)
 323 {
 324         struct panel_simple *p = dev_get_drvdata(dev);
 325         int err;
 326
 327         panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
 328
 329         err = regulator_enable(p->supply);
 330         if (err < 0) {
 331                 dev_err(dev, "failed to enable supply: %d\n", err);
 332                 return err;
 333         }
 334
 335         gpiod_set_value_cansleep(p->enable_gpio, 1);
 336
 337         if (p->desc->delay.prepare)
 338                 msleep(p->desc->delay.prepare);
 339
 340         return 0;
 341 }
 342
 343 static int panel_simple_prepare(struct drm_panel *panel)
 344 {
 345         int ret;
 346
 347         ret = pm_runtime_get_sync(panel->dev);
 348         if (ret < 0) {
 349                 pm_runtime_put_autosuspend(panel->dev);
 350                 return ret;
 351         }
 352
 353         return 0;
 354 }
 355
 356 static int panel_simple_enable(struct drm_panel *panel)
 357 {
 358         struct panel_simple *p = to_panel_simple(panel);
 359
 360         if (p->desc->delay.enable)
 361                 msleep(p->desc->delay.enable);
 362
 363         return 0;
 364 }
 365
 366 static int panel_simple_get_modes(struct drm_panel *panel,
 367                                   struct drm_connector *connector)
 368 {
 369         struct panel_simple *p = to_panel_simple(panel);
 370         int num = 0;
 371
 372         /* probe EDID if a DDC bus is available */
 373         if (p->ddc) {
 374                 pm_runtime_get_sync(panel->dev);
 375
 376                 if (!p->drm_edid)
 377                         p->drm_edid = drm_edid_read_ddc(connector, p->ddc);
 378
 379                 drm_edid_connector_update(connector, p->drm_edid);
 380
 381                 num += drm_edid_connector_add_modes(connector);
 382
 383                 pm_runtime_mark_last_busy(panel->dev);
 384                 pm_runtime_put_autosuspend(panel->dev);
 385         }
 386
 387         /* add hard-coded panel modes */
 388         num += panel_simple_get_non_edid_modes(p, connector);
 389
 390         /*
 391          * TODO: Remove once all drm drivers call
 392          * drm_connector_set_orientation_from_panel()
 393          */
 394         drm_connector_set_panel_orientation(connector, p->orientation);
 395
 396         return num;
 397 }
 398
 399 static int panel_simple_get_timings(struct drm_panel *panel,
 400                                     unsigned int num_timings,
 401                                     struct display_timing *timings)
 402 {
 403         struct panel_simple *p = to_panel_simple(panel);
 404         unsigned int i;
 405
 406         if (p->desc->num_timings < num_timings)
 407                 num_timings = p->desc->num_timings;
 408
 409         if (timings)
 410                 for (i = 0; i < num_timings; i++)
 411                         timings[i] = p->desc->timings[i];
 412
 413         return p->desc->num_timings;
 414 }
 415
 416 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
 417 {
 418         struct panel_simple *p = to_panel_simple(panel);
 419
 420         return p->orientation;
 421 }
 422
 423 static const struct drm_panel_funcs panel_simple_funcs = {
 424         .disable = panel_simple_disable,
 425         .unprepare = panel_simple_unprepare,
 426         .prepare = panel_simple_prepare,
 427         .enable = panel_simple_enable,
 428         .get_modes = panel_simple_get_modes,
 429         .get_orientation = panel_simple_get_orientation,
 430         .get_timings = panel_simple_get_timings,
 431 };
 432
 433 static struct panel_desc panel_dpi;
 434
 435 static int panel_dpi_probe(struct device *dev,
 436                            struct panel_simple *panel)
 437 {
 438         struct display_timing *timing;
 439         const struct device_node *np;
 440         struct panel_desc *desc;
 441         unsigned int bus_flags;
 442         struct videomode vm;
 443         int ret;
 444
 445         np = dev->of_node;
 446         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
 447         if (!desc)
 448                 return -ENOMEM;
 449
 450         timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 451         if (!timing)
 452                 return -ENOMEM;
 453
 454         ret = of_get_display_timing(np, "panel-timing", timing);
 455         if (ret < 0) {
 456                 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
 457                         np);
 458                 return ret;
 459         }
 460
 461         desc->timings = timing;
 462         desc->num_timings = 1;
 463
 464         of_property_read_u32(np, "width-mm", &desc->size.width);
 465         of_property_read_u32(np, "height-mm", &desc->size.height);
 466
 467         /* Extract bus_flags from display_timing */
 468         bus_flags = 0;
 469         vm.flags = timing->flags;
 470         drm_bus_flags_from_videomode(&vm, &bus_flags);
 471         desc->bus_flags = bus_flags;
 472
 473         /* We do not know the connector for the DT node, so guess it */
 474         desc->connector_type = DRM_MODE_CONNECTOR_DPI;
 475
 476         panel->desc = desc;
 477
 478         return 0;
 479 }
 480
 481 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
 482         (to_check->field.typ >= bounds->field.min && \
 483          to_check->field.typ <= bounds->field.max)
 484 static void panel_simple_parse_panel_timing_node(struct device *dev,
 485                                                  struct panel_simple *panel,
 486                                                  const struct display_timing *ot)
 487 {
 488         const struct panel_desc *desc = panel->desc;
 489         struct videomode vm;
 490         unsigned int i;
 491
 492         if (WARN_ON(desc->num_modes)) {
 493                 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
 494                 return;
 495         }
 496         if (WARN_ON(!desc->num_timings)) {
 497                 dev_err(dev, "Reject override mode: no timings specified\n");
 498                 return;
 499         }
 500
 501         for (i = 0; i < panel->desc->num_timings; i++) {
 502                 const struct display_timing *dt = &panel->desc->timings[i];
 503
 504                 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
 505                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
 506                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
 507                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
 508                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
 509                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
 510                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
 511                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
 512                         continue;
 513
 514                 if (ot->flags != dt->flags)
 515                         continue;
 516
 517                 videomode_from_timing(ot, &vm);
 518                 drm_display_mode_from_videomode(&vm, &panel->override_mode);
 519                 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
 520                                              DRM_MODE_TYPE_PREFERRED;
 521                 break;
 522         }
 523
 524         if (WARN_ON(!panel->override_mode.type))
 525                 dev_err(dev, "Reject override mode: No display_timing found\n");
 526 }
 527
 528 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev,
 529                                                              struct panel_simple *panel)
 530 {
 531         int ret, bpc;
 532
 533         ret = drm_of_lvds_get_data_mapping(dev->of_node);
 534         if (ret < 0) {
 535                 if (ret == -EINVAL)
 536                         dev_warn(dev, "Ignore invalid data-mapping property\n");
 537
 538                 /*
 539                  * Ignore non-existing or malformatted property, fallback to
 540                  * default data-mapping, and return 0.
 541                  */
 542                 return 0;
 543         }
 544
 545         switch (ret) {
 546         default:
 547                 WARN_ON(1);
 548                 fallthrough;
 549         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
 550                 fallthrough;
 551         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
 552                 bpc = 8;
 553                 break;
 554         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
 555                 bpc = 6;
 556         }
 557
 558         if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) {
 559                 struct panel_desc *override_desc;
 560
 561                 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL);
 562                 if (!override_desc)
 563                         return -ENOMEM;
 564
 565                 override_desc->bus_format = ret;
 566                 override_desc->bpc = bpc;
 567                 panel->desc = override_desc;
 568         }
 569
 570         return 0;
 571 }
 572
 573 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 574 {
 575         struct panel_simple *panel;
 576         struct display_timing dt;
 577         struct device_node *ddc;
 578         int connector_type;
 579         u32 bus_flags;
 580         int err;
 581
 582         panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
 583         if (!panel)
 584                 return -ENOMEM;
 585
 586         panel->desc = desc;
 587
 588         panel->supply = devm_regulator_get(dev, "power");
 589         if (IS_ERR(panel->supply))
 590                 return PTR_ERR(panel->supply);
 591
 592         panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
 593                                                      GPIOD_OUT_LOW);
 594         if (IS_ERR(panel->enable_gpio))
 595                 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
 596                                      "failed to request GPIO\n");
 597
 598         err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
 599         if (err) {
 600                 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
 601                 return err;
 602         }
 603
 604         ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
 605         if (ddc) {
 606                 panel->ddc = of_find_i2c_adapter_by_node(ddc);
 607                 of_node_put(ddc);
 608
 609                 if (!panel->ddc)
 610                         return -EPROBE_DEFER;
 611         }
 612
 613         if (desc == &panel_dpi) {
 614                 /* Handle the generic panel-dpi binding */
 615                 err = panel_dpi_probe(dev, panel);
 616                 if (err)
 617                         goto free_ddc;
 618                 desc = panel->desc;
 619         } else {
 620                 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
 621                         panel_simple_parse_panel_timing_node(dev, panel, &dt);
 622         }
 623
 624         if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 625                 /* Optional data-mapping property for overriding bus format */
 626                 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel);
 627                 if (err)
 628                         goto free_ddc;
 629         }
 630
 631         connector_type = desc->connector_type;
 632         /* Catch common mistakes for panels. */
 633         switch (connector_type) {
 634         case 0:
 635                 dev_warn(dev, "Specify missing connector_type\n");
 636                 connector_type = DRM_MODE_CONNECTOR_DPI;
 637                 break;
 638         case DRM_MODE_CONNECTOR_LVDS:
 639                 WARN_ON(desc->bus_flags &
 640                         ~(DRM_BUS_FLAG_DE_LOW |
 641                           DRM_BUS_FLAG_DE_HIGH |
 642                           DRM_BUS_FLAG_DATA_MSB_TO_LSB |
 643                           DRM_BUS_FLAG_DATA_LSB_TO_MSB));
 644                 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
 645                         desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
 646                         desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
 647                 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
 648                         desc->bpc != 6);
 649                 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
 650                          desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
 651                         desc->bpc != 8);
 652                 break;
 653         case DRM_MODE_CONNECTOR_eDP:
 654                 dev_warn(dev, "eDP panels moved to panel-edp\n");
 655                 err = -EINVAL;
 656                 goto free_ddc;
 657         case DRM_MODE_CONNECTOR_DSI:
 658                 if (desc->bpc != 6 && desc->bpc != 8)
 659                         dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
 660                 break;
 661         case DRM_MODE_CONNECTOR_DPI:
 662                 bus_flags = DRM_BUS_FLAG_DE_LOW |
 663                             DRM_BUS_FLAG_DE_HIGH |
 664                             DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
 665                             DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
 666                             DRM_BUS_FLAG_DATA_MSB_TO_LSB |
 667                             DRM_BUS_FLAG_DATA_LSB_TO_MSB |
 668                             DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
 669                             DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
 670                 if (desc->bus_flags & ~bus_flags)
 671                         dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
 672                 if (!(desc->bus_flags & bus_flags))
 673                         dev_warn(dev, "Specify missing bus_flags\n");
 674                 if (desc->bus_format == 0)
 675                         dev_warn(dev, "Specify missing bus_format\n");
 676                 if (desc->bpc != 6 && desc->bpc != 8)
 677                         dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
 678                 break;
 679         default:
 680                 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
 681                 connector_type = DRM_MODE_CONNECTOR_DPI;
 682                 break;
 683         }
 684
 685         dev_set_drvdata(dev, panel);
 686
 687         /*
 688          * We use runtime PM for prepare / unprepare since those power the panel
 689          * on and off and those can be very slow operations. This is important
 690          * to optimize powering the panel on briefly to read the EDID before
 691          * fully enabling the panel.
 692          */
 693         pm_runtime_enable(dev);
 694         pm_runtime_set_autosuspend_delay(dev, 1000);
 695         pm_runtime_use_autosuspend(dev);
 696
 697         drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
 698
 699         err = drm_panel_of_backlight(&panel->base);
 700         if (err) {
 701                 dev_err_probe(dev, err, "Could not find backlight\n");
 702                 goto disable_pm_runtime;
 703         }
 704
 705         drm_panel_add(&panel->base);
 706
 707         return 0;
 708
 709 disable_pm_runtime:
 710         pm_runtime_dont_use_autosuspend(dev);
 711         pm_runtime_disable(dev);
 712 free_ddc:
 713         if (panel->ddc)
 714                 put_device(&panel->ddc->dev);
 715
 716         return err;
 717 }
 718
 719 static void panel_simple_shutdown(struct device *dev)
 720 {
 721         struct panel_simple *panel = dev_get_drvdata(dev);
 722
 723         /*
 724          * NOTE: the following two calls don't really belong here. It is the
 725          * responsibility of a correctly written DRM modeset driver to call
 726          * drm_atomic_helper_shutdown() at shutdown time and that should
 727          * cause the panel to be disabled / unprepared if needed. For now,
 728          * however, we'll keep these calls due to the sheer number of
 729          * different DRM modeset drivers used with panel-simple. Once we've
 730          * confirmed that all DRM modeset drivers using this panel properly
 731          * call drm_atomic_helper_shutdown() we can simply delete the two
 732          * calls below.
 733          *
 734          * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW
 735          * PANEL DRIVERS.
 736          *
 737          * FIXME: If we're still haven't figured out if all DRM modeset
 738          * drivers properly call drm_atomic_helper_shutdown() but we _have_
 739          * managed to make sure that DRM modeset drivers get their shutdown()
 740          * callback before the panel's shutdown() callback (perhaps using
 741          * device link), we could add a WARN_ON here to help move forward.
 742          */
 743         if (panel->base.enabled)
 744                 drm_panel_disable(&panel->base);
 745         if (panel->base.prepared)
 746                 drm_panel_unprepare(&panel->base);
 747 }
 748
 749 static void panel_simple_remove(struct device *dev)
 750 {
 751         struct panel_simple *panel = dev_get_drvdata(dev);
 752
 753         drm_panel_remove(&panel->base);
 754         panel_simple_shutdown(dev);
 755
 756         pm_runtime_dont_use_autosuspend(dev);
 757         pm_runtime_disable(dev);
 758         if (panel->ddc)
 759                 put_device(&panel->ddc->dev);
 760 }
 761
 762 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
 763         .clock = 71100,
 764         .hdisplay = 1280,
 765         .hsync_start = 1280 + 40,
 766         .hsync_end = 1280 + 40 + 80,
 767         .htotal = 1280 + 40 + 80 + 40,
 768         .vdisplay = 800,
 769         .vsync_start = 800 + 3,
 770         .vsync_end = 800 + 3 + 10,
 771         .vtotal = 800 + 3 + 10 + 10,
 772         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 773 };
 774
 775 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
 776         .modes = &ampire_am_1280800n3tzqw_t00h_mode,
 777         .num_modes = 1,
 778         .bpc = 8,
 779         .size = {
 780                 .width = 217,
 781                 .height = 136,
 782         },
 783         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
 784         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 785         .connector_type = DRM_MODE_CONNECTOR_LVDS,
 786 };
 787
 788 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
 789         .clock = 9000,
 790         .hdisplay = 480,
 791         .hsync_start = 480 + 2,
 792         .hsync_end = 480 + 2 + 41,
 793         .htotal = 480 + 2 + 41 + 2,
 794         .vdisplay = 272,
 795         .vsync_start = 272 + 2,
 796         .vsync_end = 272 + 2 + 10,
 797         .vtotal = 272 + 2 + 10 + 2,
 798         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 799 };
 800
 801 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
 802         .modes = &ampire_am_480272h3tmqw_t01h_mode,
 803         .num_modes = 1,
 804         .bpc = 8,
 805         .size = {
 806                 .width = 99,
 807                 .height = 58,
 808         },
 809         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 810 };
 811
 812 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
 813         .clock = 33333,
 814         .hdisplay = 800,
 815         .hsync_start = 800 + 0,
 816         .hsync_end = 800 + 0 + 255,
 817         .htotal = 800 + 0 + 255 + 0,
 818         .vdisplay = 480,
 819         .vsync_start = 480 + 2,
 820         .vsync_end = 480 + 2 + 45,
 821         .vtotal = 480 + 2 + 45 + 0,
 822         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 823 };
 824
 825 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
 826         .pixelclock = { 29930000, 33260000, 36590000 },
 827         .hactive = { 800, 800, 800 },
 828         .hfront_porch = { 1, 40, 168 },
 829         .hback_porch = { 88, 88, 88 },
 830         .hsync_len = { 1, 128, 128 },
 831         .vactive = { 480, 480, 480 },
 832         .vfront_porch = { 1, 35, 37 },
 833         .vback_porch = { 8, 8, 8 },
 834         .vsync_len = { 1, 2, 2 },
 835         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
 836                  DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
 837                  DISPLAY_FLAGS_SYNC_POSEDGE,
 838 };
 839
 840 static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
 841         .timings = &ampire_am_800480l1tmqw_t00h_timing,
 842         .num_timings = 1,
 843         .bpc = 8,
 844         .size = {
 845                 .width = 111,
 846                 .height = 67,
 847         },
 848         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 849         .bus_flags = DRM_BUS_FLAG_DE_HIGH |
 850                      DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
 851                      DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
 852         .connector_type = DRM_MODE_CONNECTOR_DPI,
 853 };
 854
 855 static const struct panel_desc ampire_am800480r3tmqwa1h = {
 856         .modes = &ampire_am800480r3tmqwa1h_mode,
 857         .num_modes = 1,
 858         .bpc = 6,
 859         .size = {
 860                 .width = 152,
 861                 .height = 91,
 862         },
 863         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 864 };
 865
 866 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
 867         .pixelclock = { 34500000, 39600000, 50400000 },
 868         .hactive = { 800, 800, 800 },
 869         .hfront_porch = { 12, 112, 312 },
 870         .hback_porch = { 87, 87, 48 },
 871         .hsync_len = { 1, 1, 40 },
 872         .vactive = { 600, 600, 600 },
 873         .vfront_porch = { 1, 21, 61 },
 874         .vback_porch = { 38, 38, 19 },
 875         .vsync_len = { 1, 1, 20 },
 876         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
 877                 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
 878                 DISPLAY_FLAGS_SYNC_POSEDGE,
 879 };
 880
 881 static const struct panel_desc ampire_am800600p5tmqwtb8h = {
 882         .timings = &ampire_am800600p5tmqw_tb8h_timing,
 883         .num_timings = 1,
 884         .bpc = 6,
 885         .size = {
 886                 .width = 162,
 887                 .height = 122,
 888         },
 889         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 890         .bus_flags = DRM_BUS_FLAG_DE_HIGH |
 891                 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
 892                 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
 893         .connector_type = DRM_MODE_CONNECTOR_DPI,
 894 };
 895
 896 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
 897         .pixelclock = { 26400000, 33300000, 46800000 },
 898         .hactive = { 800, 800, 800 },
 899         .hfront_porch = { 16, 210, 354 },
 900         .hback_porch = { 45, 36, 6 },
 901         .hsync_len = { 1, 10, 40 },
 902         .vactive = { 480, 480, 480 },
 903         .vfront_porch = { 7, 22, 147 },
 904         .vback_porch = { 22, 13, 3 },
 905         .vsync_len = { 1, 10, 20 },
 906         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
 907                 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
 908 };
 909
 910 static const struct panel_desc armadeus_st0700_adapt = {
 911         .timings = &santek_st0700i5y_rbslw_f_timing,
 912         .num_timings = 1,
 913         .bpc = 6,
 914         .size = {
 915                 .width = 154,
 916                 .height = 86,
 917         },
 918         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 919         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
 920 };
 921
 922 static const struct drm_display_mode auo_b101aw03_mode = {
 923         .clock = 51450,
 924         .hdisplay = 1024,
 925         .hsync_start = 1024 + 156,
 926         .hsync_end = 1024 + 156 + 8,
 927         .htotal = 1024 + 156 + 8 + 156,
 928         .vdisplay = 600,
 929         .vsync_start = 600 + 16,
 930         .vsync_end = 600 + 16 + 6,
 931         .vtotal = 600 + 16 + 6 + 16,
 932 };
 933
 934 static const struct panel_desc auo_b101aw03 = {
 935         .modes = &auo_b101aw03_mode,
 936         .num_modes = 1,
 937         .bpc = 6,
 938         .size = {
 939                 .width = 223,
 940                 .height = 125,
 941         },
 942         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
 943         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
 944         .connector_type = DRM_MODE_CONNECTOR_LVDS,
 945 };
 946
 947 static const struct drm_display_mode auo_b101xtn01_mode = {
 948         .clock = 72000,
 949         .hdisplay = 1366,
 950         .hsync_start = 1366 + 20,
 951         .hsync_end = 1366 + 20 + 70,
 952         .htotal = 1366 + 20 + 70,
 953         .vdisplay = 768,
 954         .vsync_start = 768 + 14,
 955         .vsync_end = 768 + 14 + 42,
 956         .vtotal = 768 + 14 + 42,
 957         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 958 };
 959
 960 static const struct panel_desc auo_b101xtn01 = {
 961         .modes = &auo_b101xtn01_mode,
 962         .num_modes = 1,
 963         .bpc = 6,
 964         .size = {
 965                 .width = 223,
 966                 .height = 125,
 967         },
 968 };
 969
 970 static const struct drm_display_mode auo_b116xw03_mode = {
 971         .clock = 70589,
 972         .hdisplay = 1366,
 973         .hsync_start = 1366 + 40,
 974         .hsync_end = 1366 + 40 + 40,
 975         .htotal = 1366 + 40 + 40 + 32,
 976         .vdisplay = 768,
 977         .vsync_start = 768 + 10,
 978         .vsync_end = 768 + 10 + 12,
 979         .vtotal = 768 + 10 + 12 + 6,
 980         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 981 };
 982
 983 static const struct panel_desc auo_b116xw03 = {
 984         .modes = &auo_b116xw03_mode,
 985         .num_modes = 1,
 986         .bpc = 6,
 987         .size = {
 988                 .width = 256,
 989                 .height = 144,
 990         },
 991         .delay = {
 992                 .prepare = 1,
 993                 .enable = 200,
 994                 .disable = 200,
 995                 .unprepare = 500,
 996         },
 997         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
 998         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
 999         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1000 };
1001
1002 static const struct display_timing auo_g070vvn01_timings = {
1003         .pixelclock = { 33300000, 34209000, 45000000 },
1004         .hactive = { 800, 800, 800 },
1005         .hfront_porch = { 20, 40, 200 },
1006         .hback_porch = { 87, 40, 1 },
1007         .hsync_len = { 1, 48, 87 },
1008         .vactive = { 480, 480, 480 },
1009         .vfront_porch = { 5, 13, 200 },
1010         .vback_porch = { 31, 31, 29 },
1011         .vsync_len = { 1, 1, 3 },
1012 };
1013
1014 static const struct panel_desc auo_g070vvn01 = {
1015         .timings = &auo_g070vvn01_timings,
1016         .num_timings = 1,
1017         .bpc = 8,
1018         .size = {
1019                 .width = 152,
1020                 .height = 91,
1021         },
1022         .delay = {
1023                 .prepare = 200,
1024                 .enable = 50,
1025                 .disable = 50,
1026                 .unprepare = 1000,
1027         },
1028 };
1029
1030 static const struct drm_display_mode auo_g101evn010_mode = {
1031         .clock = 68930,
1032         .hdisplay = 1280,
1033         .hsync_start = 1280 + 82,
1034         .hsync_end = 1280 + 82 + 2,
1035         .htotal = 1280 + 82 + 2 + 84,
1036         .vdisplay = 800,
1037         .vsync_start = 800 + 8,
1038         .vsync_end = 800 + 8 + 2,
1039         .vtotal = 800 + 8 + 2 + 6,
1040 };
1041
1042 static const struct panel_desc auo_g101evn010 = {
1043         .modes = &auo_g101evn010_mode,
1044         .num_modes = 1,
1045         .bpc = 6,
1046         .size = {
1047                 .width = 216,
1048                 .height = 135,
1049         },
1050         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1051         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1052 };
1053
1054 static const struct drm_display_mode auo_g104sn02_mode = {
1055         .clock = 40000,
1056         .hdisplay = 800,
1057         .hsync_start = 800 + 40,
1058         .hsync_end = 800 + 40 + 216,
1059         .htotal = 800 + 40 + 216 + 128,
1060         .vdisplay = 600,
1061         .vsync_start = 600 + 10,
1062         .vsync_end = 600 + 10 + 35,
1063         .vtotal = 600 + 10 + 35 + 2,
1064 };
1065
1066 static const struct panel_desc auo_g104sn02 = {
1067         .modes = &auo_g104sn02_mode,
1068         .num_modes = 1,
1069         .bpc = 8,
1070         .size = {
1071                 .width = 211,
1072                 .height = 158,
1073         },
1074         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1075         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1076 };
1077
1078 static const struct drm_display_mode auo_g104stn01_mode = {
1079         .clock = 40000,
1080         .hdisplay = 800,
1081         .hsync_start = 800 + 40,
1082         .hsync_end = 800 + 40 + 88,
1083         .htotal = 800 + 40 + 88 + 128,
1084         .vdisplay = 600,
1085         .vsync_start = 600 + 1,
1086         .vsync_end = 600 + 1 + 23,
1087         .vtotal = 600 + 1 + 23 + 4,
1088 };
1089
1090 static const struct panel_desc auo_g104stn01 = {
1091         .modes = &auo_g104stn01_mode,
1092         .num_modes = 1,
1093         .bpc = 8,
1094         .size = {
1095                 .width = 211,
1096                 .height = 158,
1097         },
1098         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1099         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1100 };
1101
1102 static const struct display_timing auo_g121ean01_timing = {
1103         .pixelclock = { 60000000, 74400000, 90000000 },
1104         .hactive = { 1280, 1280, 1280 },
1105         .hfront_porch = { 20, 50, 100 },
1106         .hback_porch = { 20, 50, 100 },
1107         .hsync_len = { 30, 100, 200 },
1108         .vactive = { 800, 800, 800 },
1109         .vfront_porch = { 2, 10, 25 },
1110         .vback_porch = { 2, 10, 25 },
1111         .vsync_len = { 4, 18, 50 },
1112 };
1113
1114 static const struct panel_desc auo_g121ean01 = {
1115         .timings = &auo_g121ean01_timing,
1116         .num_timings = 1,
1117         .bpc = 8,
1118         .size = {
1119                 .width = 261,
1120                 .height = 163,
1121         },
1122         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1123         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1124 };
1125
1126 static const struct display_timing auo_g133han01_timings = {
1127         .pixelclock = { 134000000, 141200000, 149000000 },
1128         .hactive = { 1920, 1920, 1920 },
1129         .hfront_porch = { 39, 58, 77 },
1130         .hback_porch = { 59, 88, 117 },
1131         .hsync_len = { 28, 42, 56 },
1132         .vactive = { 1080, 1080, 1080 },
1133         .vfront_porch = { 3, 8, 11 },
1134         .vback_porch = { 5, 14, 19 },
1135         .vsync_len = { 4, 14, 19 },
1136 };
1137
1138 static const struct panel_desc auo_g133han01 = {
1139         .timings = &auo_g133han01_timings,
1140         .num_timings = 1,
1141         .bpc = 8,
1142         .size = {
1143                 .width = 293,
1144                 .height = 165,
1145         },
1146         .delay = {
1147                 .prepare = 200,
1148                 .enable = 50,
1149                 .disable = 50,
1150                 .unprepare = 1000,
1151         },
1152         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1153         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1154 };
1155
1156 static const struct display_timing auo_g156han04_timings = {
1157         .pixelclock = { 137000000, 141000000, 146000000 },
1158         .hactive = { 1920, 1920, 1920 },
1159         .hfront_porch = { 60, 60, 60 },
1160         .hback_porch = { 90, 92, 111 },
1161         .hsync_len =  { 32, 32, 32 },
1162         .vactive = { 1080, 1080, 1080 },
1163         .vfront_porch = { 12, 12, 12 },
1164         .vback_porch = { 24, 36, 56 },
1165         .vsync_len = { 8, 8, 8 },
1166 };
1167
1168 static const struct panel_desc auo_g156han04 = {
1169         .timings = &auo_g156han04_timings,
1170         .num_timings = 1,
1171         .bpc = 8,
1172         .size = {
1173                 .width = 344,
1174                 .height = 194,
1175         },
1176         .delay = {
1177                 .prepare = 50,          /* T2 */
1178                 .enable = 200,          /* T3 */
1179                 .disable = 110,         /* T10 */
1180                 .unprepare = 1000,      /* T13 */
1181         },
1182         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1183         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1184         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1185 };
1186
1187 static const struct drm_display_mode auo_g156xtn01_mode = {
1188         .clock = 76000,
1189         .hdisplay = 1366,
1190         .hsync_start = 1366 + 33,
1191         .hsync_end = 1366 + 33 + 67,
1192         .htotal = 1560,
1193         .vdisplay = 768,
1194         .vsync_start = 768 + 4,
1195         .vsync_end = 768 + 4 + 4,
1196         .vtotal = 806,
1197 };
1198
1199 static const struct panel_desc auo_g156xtn01 = {
1200         .modes = &auo_g156xtn01_mode,
1201         .num_modes = 1,
1202         .bpc = 8,
1203         .size = {
1204                 .width = 344,
1205                 .height = 194,
1206         },
1207         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1208         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1209 };
1210
1211 static const struct display_timing auo_g185han01_timings = {
1212         .pixelclock = { 120000000, 144000000, 175000000 },
1213         .hactive = { 1920, 1920, 1920 },
1214         .hfront_porch = { 36, 120, 148 },
1215         .hback_porch = { 24, 88, 108 },
1216         .hsync_len = { 20, 48, 64 },
1217         .vactive = { 1080, 1080, 1080 },
1218         .vfront_porch = { 6, 10, 40 },
1219         .vback_porch = { 2, 5, 20 },
1220         .vsync_len = { 2, 5, 20 },
1221 };
1222
1223 static const struct panel_desc auo_g185han01 = {
1224         .timings = &auo_g185han01_timings,
1225         .num_timings = 1,
1226         .bpc = 8,
1227         .size = {
1228                 .width = 409,
1229                 .height = 230,
1230         },
1231         .delay = {
1232                 .prepare = 50,
1233                 .enable = 200,
1234                 .disable = 110,
1235                 .unprepare = 1000,
1236         },
1237         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1238         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1239 };
1240
1241 static const struct display_timing auo_g190ean01_timings = {
1242         .pixelclock = { 90000000, 108000000, 135000000 },
1243         .hactive = { 1280, 1280, 1280 },
1244         .hfront_porch = { 126, 184, 1266 },
1245         .hback_porch = { 84, 122, 844 },
1246         .hsync_len = { 70, 102, 704 },
1247         .vactive = { 1024, 1024, 1024 },
1248         .vfront_porch = { 4, 26, 76 },
1249         .vback_porch = { 2, 8, 25 },
1250         .vsync_len = { 2, 8, 25 },
1251 };
1252
1253 static const struct panel_desc auo_g190ean01 = {
1254         .timings = &auo_g190ean01_timings,
1255         .num_timings = 1,
1256         .bpc = 8,
1257         .size = {
1258                 .width = 376,
1259                 .height = 301,
1260         },
1261         .delay = {
1262                 .prepare = 50,
1263                 .enable = 200,
1264                 .disable = 110,
1265                 .unprepare = 1000,
1266         },
1267         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1268         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1269 };
1270
1271 static const struct display_timing auo_p320hvn03_timings = {
1272         .pixelclock = { 106000000, 148500000, 164000000 },
1273         .hactive = { 1920, 1920, 1920 },
1274         .hfront_porch = { 25, 50, 130 },
1275         .hback_porch = { 25, 50, 130 },
1276         .hsync_len = { 20, 40, 105 },
1277         .vactive = { 1080, 1080, 1080 },
1278         .vfront_porch = { 8, 17, 150 },
1279         .vback_porch = { 8, 17, 150 },
1280         .vsync_len = { 4, 11, 100 },
1281 };
1282
1283 static const struct panel_desc auo_p320hvn03 = {
1284         .timings = &auo_p320hvn03_timings,
1285         .num_timings = 1,
1286         .bpc = 8,
1287         .size = {
1288                 .width = 698,
1289                 .height = 393,
1290         },
1291         .delay = {
1292                 .prepare = 1,
1293                 .enable = 450,
1294                 .unprepare = 500,
1295         },
1296         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1297         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1298 };
1299
1300 static const struct drm_display_mode auo_t215hvn01_mode = {
1301         .clock = 148800,
1302         .hdisplay = 1920,
1303         .hsync_start = 1920 + 88,
1304         .hsync_end = 1920 + 88 + 44,
1305         .htotal = 1920 + 88 + 44 + 148,
1306         .vdisplay = 1080,
1307         .vsync_start = 1080 + 4,
1308         .vsync_end = 1080 + 4 + 5,
1309         .vtotal = 1080 + 4 + 5 + 36,
1310 };
1311
1312 static const struct panel_desc auo_t215hvn01 = {
1313         .modes = &auo_t215hvn01_mode,
1314         .num_modes = 1,
1315         .bpc = 8,
1316         .size = {
1317                 .width = 430,
1318                 .height = 270,
1319         },
1320         .delay = {
1321                 .disable = 5,
1322                 .unprepare = 1000,
1323         },
1324         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1325         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1326 };
1327
1328 static const struct drm_display_mode avic_tm070ddh03_mode = {
1329         .clock = 51200,
1330         .hdisplay = 1024,
1331         .hsync_start = 1024 + 160,
1332         .hsync_end = 1024 + 160 + 4,
1333         .htotal = 1024 + 160 + 4 + 156,
1334         .vdisplay = 600,
1335         .vsync_start = 600 + 17,
1336         .vsync_end = 600 + 17 + 1,
1337         .vtotal = 600 + 17 + 1 + 17,
1338 };
1339
1340 static const struct panel_desc avic_tm070ddh03 = {
1341         .modes = &avic_tm070ddh03_mode,
1342         .num_modes = 1,
1343         .bpc = 8,
1344         .size = {
1345                 .width = 154,
1346                 .height = 90,
1347         },
1348         .delay = {
1349                 .prepare = 20,
1350                 .enable = 200,
1351                 .disable = 200,
1352         },
1353 };
1354
1355 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1356         .clock = 30000,
1357         .hdisplay = 800,
1358         .hsync_start = 800 + 40,
1359         .hsync_end = 800 + 40 + 48,
1360         .htotal = 800 + 40 + 48 + 40,
1361         .vdisplay = 480,
1362         .vsync_start = 480 + 13,
1363         .vsync_end = 480 + 13 + 3,
1364         .vtotal = 480 + 13 + 3 + 29,
1365 };
1366
1367 static const struct panel_desc bananapi_s070wv20_ct16 = {
1368         .modes = &bananapi_s070wv20_ct16_mode,
1369         .num_modes = 1,
1370         .bpc = 6,
1371         .size = {
1372                 .width = 154,
1373                 .height = 86,
1374         },
1375 };
1376
1377 static const struct drm_display_mode boe_bp101wx1_100_mode = {
1378         .clock = 78945,
1379         .hdisplay = 1280,
1380         .hsync_start = 1280 + 0,
1381         .hsync_end = 1280 + 0 + 2,
1382         .htotal = 1280 + 62 + 0 + 2,
1383         .vdisplay = 800,
1384         .vsync_start = 800 + 8,
1385         .vsync_end = 800 + 8 + 2,
1386         .vtotal = 800 + 6 + 8 + 2,
1387 };
1388
1389 static const struct panel_desc boe_bp082wx1_100 = {
1390         .modes = &boe_bp101wx1_100_mode,
1391         .num_modes = 1,
1392         .bpc = 8,
1393         .size = {
1394                 .width = 177,
1395                 .height = 110,
1396         },
1397         .delay = {
1398                 .enable = 50,
1399                 .disable = 50,
1400         },
1401         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1402         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1403         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1404 };
1405
1406 static const struct panel_desc boe_bp101wx1_100 = {
1407         .modes = &boe_bp101wx1_100_mode,
1408         .num_modes = 1,
1409         .bpc = 8,
1410         .size = {
1411                 .width = 217,
1412                 .height = 136,
1413         },
1414         .delay = {
1415                 .enable = 50,
1416                 .disable = 50,
1417         },
1418         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1419         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1420         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1421 };
1422
1423 static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1424         .pixelclock = { 69922000, 71000000, 72293000 },
1425         .hactive = { 1280, 1280, 1280 },
1426         .hfront_porch = { 48, 48, 48 },
1427         .hback_porch = { 80, 80, 80 },
1428         .hsync_len = { 32, 32, 32 },
1429         .vactive = { 800, 800, 800 },
1430         .vfront_porch = { 3, 3, 3 },
1431         .vback_porch = { 14, 14, 14 },
1432         .vsync_len = { 6, 6, 6 },
1433 };
1434
1435 static const struct panel_desc boe_ev121wxm_n10_1850 = {
1436         .timings = &boe_ev121wxm_n10_1850_timing,
1437         .num_timings = 1,
1438         .bpc = 8,
1439         .size = {
1440                 .width = 261,
1441                 .height = 163,
1442         },
1443         .delay = {
1444                 .prepare = 9,
1445                 .enable = 300,
1446                 .unprepare = 300,
1447                 .disable = 560,
1448         },
1449         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1450         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1451         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1452 };
1453
1454 static const struct drm_display_mode boe_hv070wsa_mode = {
1455         .clock = 42105,
1456         .hdisplay = 1024,
1457         .hsync_start = 1024 + 30,
1458         .hsync_end = 1024 + 30 + 30,
1459         .htotal = 1024 + 30 + 30 + 30,
1460         .vdisplay = 600,
1461         .vsync_start = 600 + 10,
1462         .vsync_end = 600 + 10 + 10,
1463         .vtotal = 600 + 10 + 10 + 10,
1464 };
1465
1466 static const struct panel_desc boe_hv070wsa = {
1467         .modes = &boe_hv070wsa_mode,
1468         .num_modes = 1,
1469         .bpc = 8,
1470         .size = {
1471                 .width = 154,
1472                 .height = 90,
1473         },
1474         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1475         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1476         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1477 };
1478
1479 static const struct display_timing cct_cmt430b19n00_timing = {
1480         .pixelclock = { 8000000, 9000000, 12000000 },
1481         .hactive = { 480, 480, 480 },
1482         .hfront_porch = { 2, 8, 75 },
1483         .hback_porch = { 3, 43, 43 },
1484         .hsync_len = { 2, 4, 75 },
1485         .vactive = { 272, 272, 272 },
1486         .vfront_porch = { 2, 8, 37 },
1487         .vback_porch = { 2, 12, 12 },
1488         .vsync_len = { 2, 4, 37 },
1489         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW
1490 };
1491
1492 static const struct panel_desc cct_cmt430b19n00 = {
1493         .timings = &cct_cmt430b19n00_timing,
1494         .num_timings = 1,
1495         .bpc = 8,
1496         .size = {
1497                 .width = 95,
1498                 .height = 53,
1499         },
1500         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1501         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1502         .connector_type = DRM_MODE_CONNECTOR_DPI,
1503 };
1504
1505 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1506         .clock = 9000,
1507         .hdisplay = 480,
1508         .hsync_start = 480 + 5,
1509         .hsync_end = 480 + 5 + 5,
1510         .htotal = 480 + 5 + 5 + 40,
1511         .vdisplay = 272,
1512         .vsync_start = 272 + 8,
1513         .vsync_end = 272 + 8 + 8,
1514         .vtotal = 272 + 8 + 8 + 8,
1515         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1516 };
1517
1518 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1519         .modes = &cdtech_s043wq26h_ct7_mode,
1520         .num_modes = 1,
1521         .bpc = 8,
1522         .size = {
1523                 .width = 95,
1524                 .height = 54,
1525         },
1526         .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1527 };
1528
1529 /* S070PWS19HP-FC21 2017/04/22 */
1530 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1531         .clock = 51200,
1532         .hdisplay = 1024,
1533         .hsync_start = 1024 + 160,
1534         .hsync_end = 1024 + 160 + 20,
1535         .htotal = 1024 + 160 + 20 + 140,
1536         .vdisplay = 600,
1537         .vsync_start = 600 + 12,
1538         .vsync_end = 600 + 12 + 3,
1539         .vtotal = 600 + 12 + 3 + 20,
1540         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1541 };
1542
1543 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1544         .modes = &cdtech_s070pws19hp_fc21_mode,
1545         .num_modes = 1,
1546         .bpc = 6,
1547         .size = {
1548                 .width = 154,
1549                 .height = 86,
1550         },
1551         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1552         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1553         .connector_type = DRM_MODE_CONNECTOR_DPI,
1554 };
1555
1556 /* S070SWV29HG-DC44 2017/09/21 */
1557 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1558         .clock = 33300,
1559         .hdisplay = 800,
1560         .hsync_start = 800 + 210,
1561         .hsync_end = 800 + 210 + 2,
1562         .htotal = 800 + 210 + 2 + 44,
1563         .vdisplay = 480,
1564         .vsync_start = 480 + 22,
1565         .vsync_end = 480 + 22 + 2,
1566         .vtotal = 480 + 22 + 2 + 21,
1567         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1568 };
1569
1570 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1571         .modes = &cdtech_s070swv29hg_dc44_mode,
1572         .num_modes = 1,
1573         .bpc = 6,
1574         .size = {
1575                 .width = 154,
1576                 .height = 86,
1577         },
1578         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1579         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1580         .connector_type = DRM_MODE_CONNECTOR_DPI,
1581 };
1582
1583 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1584         .clock = 35000,
1585         .hdisplay = 800,
1586         .hsync_start = 800 + 40,
1587         .hsync_end = 800 + 40 + 40,
1588         .htotal = 800 + 40 + 40 + 48,
1589         .vdisplay = 480,
1590         .vsync_start = 480 + 29,
1591         .vsync_end = 480 + 29 + 13,
1592         .vtotal = 480 + 29 + 13 + 3,
1593         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1594 };
1595
1596 static const struct panel_desc cdtech_s070wv95_ct16 = {
1597         .modes = &cdtech_s070wv95_ct16_mode,
1598         .num_modes = 1,
1599         .bpc = 8,
1600         .size = {
1601                 .width = 154,
1602                 .height = 85,
1603         },
1604 };
1605
1606 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1607         .pixelclock = { 68900000, 71100000, 73400000 },
1608         .hactive = { 1280, 1280, 1280 },
1609         .hfront_porch = { 65, 80, 95 },
1610         .hback_porch = { 64, 79, 94 },
1611         .hsync_len = { 1, 1, 1 },
1612         .vactive = { 800, 800, 800 },
1613         .vfront_porch = { 7, 11, 14 },
1614         .vback_porch = { 7, 11, 14 },
1615         .vsync_len = { 1, 1, 1 },
1616         .flags = DISPLAY_FLAGS_DE_HIGH,
1617 };
1618
1619 static const struct panel_desc chefree_ch101olhlwh_002 = {
1620         .timings = &chefree_ch101olhlwh_002_timing,
1621         .num_timings = 1,
1622         .bpc = 8,
1623         .size = {
1624                 .width = 217,
1625                 .height = 135,
1626         },
1627         .delay = {
1628                 .enable = 200,
1629                 .disable = 200,
1630         },
1631         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1632         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1633         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1634 };
1635
1636 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1637         .clock = 66770,
1638         .hdisplay = 800,
1639         .hsync_start = 800 + 49,
1640         .hsync_end = 800 + 49 + 33,
1641         .htotal = 800 + 49 + 33 + 17,
1642         .vdisplay = 1280,
1643         .vsync_start = 1280 + 1,
1644         .vsync_end = 1280 + 1 + 7,
1645         .vtotal = 1280 + 1 + 7 + 15,
1646         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1647 };
1648
1649 static const struct panel_desc chunghwa_claa070wp03xg = {
1650         .modes = &chunghwa_claa070wp03xg_mode,
1651         .num_modes = 1,
1652         .bpc = 6,
1653         .size = {
1654                 .width = 94,
1655                 .height = 150,
1656         },
1657         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1658         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1659         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1660 };
1661
1662 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1663         .clock = 72070,
1664         .hdisplay = 1366,
1665         .hsync_start = 1366 + 58,
1666         .hsync_end = 1366 + 58 + 58,
1667         .htotal = 1366 + 58 + 58 + 58,
1668         .vdisplay = 768,
1669         .vsync_start = 768 + 4,
1670         .vsync_end = 768 + 4 + 4,
1671         .vtotal = 768 + 4 + 4 + 4,
1672 };
1673
1674 static const struct panel_desc chunghwa_claa101wa01a = {
1675         .modes = &chunghwa_claa101wa01a_mode,
1676         .num_modes = 1,
1677         .bpc = 6,
1678         .size = {
1679                 .width = 220,
1680                 .height = 120,
1681         },
1682         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1683         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1684         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1685 };
1686
1687 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1688         .clock = 69300,
1689         .hdisplay = 1366,
1690         .hsync_start = 1366 + 48,
1691         .hsync_end = 1366 + 48 + 32,
1692         .htotal = 1366 + 48 + 32 + 20,
1693         .vdisplay = 768,
1694         .vsync_start = 768 + 16,
1695         .vsync_end = 768 + 16 + 8,
1696         .vtotal = 768 + 16 + 8 + 16,
1697 };
1698
1699 static const struct panel_desc chunghwa_claa101wb01 = {
1700         .modes = &chunghwa_claa101wb01_mode,
1701         .num_modes = 1,
1702         .bpc = 6,
1703         .size = {
1704                 .width = 223,
1705                 .height = 125,
1706         },
1707         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1708         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1709         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1710 };
1711
1712 static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1713         .pixelclock = { 5000000, 9000000, 12000000 },
1714         .hactive = { 480, 480, 480 },
1715         .hfront_porch = { 12, 12, 12 },
1716         .hback_porch = { 12, 12, 12 },
1717         .hsync_len = { 21, 21, 21 },
1718         .vactive = { 272, 272, 272 },
1719         .vfront_porch = { 4, 4, 4 },
1720         .vback_porch = { 4, 4, 4 },
1721         .vsync_len = { 8, 8, 8 },
1722 };
1723
1724 static const struct panel_desc dataimage_fg040346dsswbg04 = {
1725         .timings = &dataimage_fg040346dsswbg04_timing,
1726         .num_timings = 1,
1727         .bpc = 8,
1728         .size = {
1729                 .width = 95,
1730                 .height = 54,
1731         },
1732         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1733         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1734         .connector_type = DRM_MODE_CONNECTOR_DPI,
1735 };
1736
1737 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1738         .pixelclock = { 68900000, 71110000, 73400000 },
1739         .hactive = { 1280, 1280, 1280 },
1740         .vactive = { 800, 800, 800 },
1741         .hback_porch = { 100, 100, 100 },
1742         .hfront_porch = { 100, 100, 100 },
1743         .vback_porch = { 5, 5, 5 },
1744         .vfront_porch = { 5, 5, 5 },
1745         .hsync_len = { 24, 24, 24 },
1746         .vsync_len = { 3, 3, 3 },
1747         .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1748                  DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1749 };
1750
1751 static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1752         .timings = &dataimage_fg1001l0dsswmg01_timing,
1753         .num_timings = 1,
1754         .bpc = 8,
1755         .size = {
1756                 .width = 217,
1757                 .height = 136,
1758         },
1759 };
1760
1761 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1762         .clock = 33260,
1763         .hdisplay = 800,
1764         .hsync_start = 800 + 40,
1765         .hsync_end = 800 + 40 + 128,
1766         .htotal = 800 + 40 + 128 + 88,
1767         .vdisplay = 480,
1768         .vsync_start = 480 + 10,
1769         .vsync_end = 480 + 10 + 2,
1770         .vtotal = 480 + 10 + 2 + 33,
1771         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1772 };
1773
1774 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1775         .modes = &dataimage_scf0700c48ggu18_mode,
1776         .num_modes = 1,
1777         .bpc = 8,
1778         .size = {
1779                 .width = 152,
1780                 .height = 91,
1781         },
1782         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1783         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1784 };
1785
1786 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1787         .pixelclock = { 45000000, 51200000, 57000000 },
1788         .hactive = { 1024, 1024, 1024 },
1789         .hfront_porch = { 100, 106, 113 },
1790         .hback_porch = { 100, 106, 113 },
1791         .hsync_len = { 100, 108, 114 },
1792         .vactive = { 600, 600, 600 },
1793         .vfront_porch = { 8, 11, 15 },
1794         .vback_porch = { 8, 11, 15 },
1795         .vsync_len = { 9, 13, 15 },
1796         .flags = DISPLAY_FLAGS_DE_HIGH,
1797 };
1798
1799 static const struct panel_desc dlc_dlc0700yzg_1 = {
1800         .timings = &dlc_dlc0700yzg_1_timing,
1801         .num_timings = 1,
1802         .bpc = 6,
1803         .size = {
1804                 .width = 154,
1805                 .height = 86,
1806         },
1807         .delay = {
1808                 .prepare = 30,
1809                 .enable = 200,
1810                 .disable = 200,
1811         },
1812         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1813         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1814 };
1815
1816 static const struct display_timing dlc_dlc1010gig_timing = {
1817         .pixelclock = { 68900000, 71100000, 73400000 },
1818         .hactive = { 1280, 1280, 1280 },
1819         .hfront_porch = { 43, 53, 63 },
1820         .hback_porch = { 43, 53, 63 },
1821         .hsync_len = { 44, 54, 64 },
1822         .vactive = { 800, 800, 800 },
1823         .vfront_porch = { 5, 8, 11 },
1824         .vback_porch = { 5, 8, 11 },
1825         .vsync_len = { 5, 7, 11 },
1826         .flags = DISPLAY_FLAGS_DE_HIGH,
1827 };
1828
1829 static const struct panel_desc dlc_dlc1010gig = {
1830         .timings = &dlc_dlc1010gig_timing,
1831         .num_timings = 1,
1832         .bpc = 8,
1833         .size = {
1834                 .width = 216,
1835                 .height = 135,
1836         },
1837         .delay = {
1838                 .prepare = 60,
1839                 .enable = 150,
1840                 .disable = 100,
1841                 .unprepare = 60,
1842         },
1843         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1844         .connector_type = DRM_MODE_CONNECTOR_LVDS,
1845 };
1846
1847 static const struct drm_display_mode edt_et035012dm6_mode = {
1848         .clock = 6500,
1849         .hdisplay = 320,
1850         .hsync_start = 320 + 20,
1851         .hsync_end = 320 + 20 + 30,
1852         .htotal = 320 + 20 + 68,
1853         .vdisplay = 240,
1854         .vsync_start = 240 + 4,
1855         .vsync_end = 240 + 4 + 4,
1856         .vtotal = 240 + 4 + 4 + 14,
1857         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1858 };
1859
1860 static const struct panel_desc edt_et035012dm6 = {
1861         .modes = &edt_et035012dm6_mode,
1862         .num_modes = 1,
1863         .bpc = 8,
1864         .size = {
1865                 .width = 70,
1866                 .height = 52,
1867         },
1868         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1869         .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1870 };
1871
1872 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1873         .clock = 6520,
1874         .hdisplay = 320,
1875         .hsync_start = 320 + 20,
1876         .hsync_end = 320 + 20 + 68,
1877         .htotal = 320 + 20 + 68,
1878         .vdisplay = 240,
1879         .vsync_start = 240 + 4,
1880         .vsync_end = 240 + 4 + 18,
1881         .vtotal = 240 + 4 + 18,
1882         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1883 };
1884
1885 static const struct panel_desc edt_etm0350g0dh6 = {
1886         .modes = &edt_etm0350g0dh6_mode,
1887         .num_modes = 1,
1888         .bpc = 6,
1889         .size = {
1890                 .width = 70,
1891                 .height = 53,
1892         },
1893         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1894         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1895         .connector_type = DRM_MODE_CONNECTOR_DPI,
1896 };
1897
1898 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1899         .clock = 10870,
1900         .hdisplay = 480,
1901         .hsync_start = 480 + 8,
1902         .hsync_end = 480 + 8 + 4,
1903         .htotal = 480 + 8 + 4 + 41,
1904
1905         /*
1906          * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1907          * fb_align
1908          */
1909
1910         .vdisplay = 288,
1911         .vsync_start = 288 + 2,
1912         .vsync_end = 288 + 2 + 4,
1913         .vtotal = 288 + 2 + 4 + 10,
1914 };
1915
1916 static const struct panel_desc edt_etm043080dh6gp = {
1917         .modes = &edt_etm043080dh6gp_mode,
1918         .num_modes = 1,
1919         .bpc = 8,
1920         .size = {
1921                 .width = 100,
1922                 .height = 65,
1923         },
1924         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1925         .connector_type = DRM_MODE_CONNECTOR_DPI,
1926 };
1927
1928 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1929         .clock = 9000,
1930         .hdisplay = 480,
1931         .hsync_start = 480 + 2,
1932         .hsync_end = 480 + 2 + 41,
1933         .htotal = 480 + 2 + 41 + 2,
1934         .vdisplay = 272,
1935         .vsync_start = 272 + 2,
1936         .vsync_end = 272 + 2 + 10,
1937         .vtotal = 272 + 2 + 10 + 2,
1938         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1939 };
1940
1941 static const struct panel_desc edt_etm0430g0dh6 = {
1942         .modes = &edt_etm0430g0dh6_mode,
1943         .num_modes = 1,
1944         .bpc = 6,
1945         .size = {
1946                 .width = 95,
1947                 .height = 54,
1948         },
1949         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1950         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1951         .connector_type = DRM_MODE_CONNECTOR_DPI,
1952 };
1953
1954 static const struct drm_display_mode edt_et057090dhu_mode = {
1955         .clock = 25175,
1956         .hdisplay = 640,
1957         .hsync_start = 640 + 16,
1958         .hsync_end = 640 + 16 + 30,
1959         .htotal = 640 + 16 + 30 + 114,
1960         .vdisplay = 480,
1961         .vsync_start = 480 + 10,
1962         .vsync_end = 480 + 10 + 3,
1963         .vtotal = 480 + 10 + 3 + 32,
1964         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1965 };
1966
1967 static const struct panel_desc edt_et057090dhu = {
1968         .modes = &edt_et057090dhu_mode,
1969         .num_modes = 1,
1970         .bpc = 6,
1971         .size = {
1972                 .width = 115,
1973                 .height = 86,
1974         },
1975         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1976         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1977         .connector_type = DRM_MODE_CONNECTOR_DPI,
1978 };
1979
1980 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1981         .clock = 33260,
1982         .hdisplay = 800,
1983         .hsync_start = 800 + 40,
1984         .hsync_end = 800 + 40 + 128,
1985         .htotal = 800 + 40 + 128 + 88,
1986         .vdisplay = 480,
1987         .vsync_start = 480 + 10,
1988         .vsync_end = 480 + 10 + 2,
1989         .vtotal = 480 + 10 + 2 + 33,
1990         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1991 };
1992
1993 static const struct panel_desc edt_etm0700g0dh6 = {
1994         .modes = &edt_etm0700g0dh6_mode,
1995         .num_modes = 1,
1996         .bpc = 6,
1997         .size = {
1998                 .width = 152,
1999                 .height = 91,
2000         },
2001         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2002         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2003         .connector_type = DRM_MODE_CONNECTOR_DPI,
2004 };
2005
2006 static const struct panel_desc edt_etm0700g0bdh6 = {
2007         .modes = &edt_etm0700g0dh6_mode,
2008         .num_modes = 1,
2009         .bpc = 6,
2010         .size = {
2011                 .width = 152,
2012                 .height = 91,
2013         },
2014         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2015         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2016         .connector_type = DRM_MODE_CONNECTOR_DPI,
2017 };
2018
2019 static const struct display_timing edt_etml0700y5dha_timing = {
2020         .pixelclock = { 40800000, 51200000, 67200000 },
2021         .hactive = { 1024, 1024, 1024 },
2022         .hfront_porch = { 30, 106, 125 },
2023         .hback_porch = { 30, 106, 125 },
2024         .hsync_len = { 30, 108, 126 },
2025         .vactive = { 600, 600, 600 },
2026         .vfront_porch = { 3, 12, 67},
2027         .vback_porch = { 3, 12, 67 },
2028         .vsync_len = { 4, 11, 66 },
2029         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2030                  DISPLAY_FLAGS_DE_HIGH,
2031 };
2032
2033 static const struct panel_desc edt_etml0700y5dha = {
2034         .timings = &edt_etml0700y5dha_timing,
2035         .num_timings = 1,
2036         .bpc = 8,
2037         .size = {
2038                 .width = 155,
2039                 .height = 86,
2040         },
2041         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2042         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2043 };
2044
2045 static const struct display_timing edt_etml1010g3dra_timing = {
2046         .pixelclock = { 66300000, 72400000, 78900000 },
2047         .hactive = { 1280, 1280, 1280 },
2048         .hfront_porch = { 12, 72, 132 },
2049         .hback_porch = { 86, 86, 86 },
2050         .hsync_len = { 2, 2, 2 },
2051         .vactive = { 800, 800, 800 },
2052         .vfront_porch = { 1, 15, 49 },
2053         .vback_porch = { 21, 21, 21 },
2054         .vsync_len = { 2, 2, 2 },
2055         .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
2056                  DISPLAY_FLAGS_DE_HIGH,
2057 };
2058
2059 static const struct panel_desc edt_etml1010g3dra = {
2060         .timings = &edt_etml1010g3dra_timing,
2061         .num_timings = 1,
2062         .bpc = 8,
2063         .size = {
2064                 .width = 216,
2065                 .height = 135,
2066         },
2067         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2068         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2069         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2070 };
2071
2072 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
2073         .clock = 25175,
2074         .hdisplay = 640,
2075         .hsync_start = 640,
2076         .hsync_end = 640 + 16,
2077         .htotal = 640 + 16 + 30 + 114,
2078         .vdisplay = 480,
2079         .vsync_start = 480 + 10,
2080         .vsync_end = 480 + 10 + 3,
2081         .vtotal = 480 + 10 + 3 + 35,
2082         .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
2083 };
2084
2085 static const struct panel_desc edt_etmv570g2dhu = {
2086         .modes = &edt_etmv570g2dhu_mode,
2087         .num_modes = 1,
2088         .bpc = 6,
2089         .size = {
2090                 .width = 115,
2091                 .height = 86,
2092         },
2093         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2094         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2095         .connector_type = DRM_MODE_CONNECTOR_DPI,
2096 };
2097
2098 static const struct display_timing eink_vb3300_kca_timing = {
2099         .pixelclock = { 40000000, 40000000, 40000000 },
2100         .hactive = { 334, 334, 334 },
2101         .hfront_porch = { 1, 1, 1 },
2102         .hback_porch = { 1, 1, 1 },
2103         .hsync_len = { 1, 1, 1 },
2104         .vactive = { 1405, 1405, 1405 },
2105         .vfront_porch = { 1, 1, 1 },
2106         .vback_porch = { 1, 1, 1 },
2107         .vsync_len = { 1, 1, 1 },
2108         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2109                  DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
2110 };
2111
2112 static const struct panel_desc eink_vb3300_kca = {
2113         .timings = &eink_vb3300_kca_timing,
2114         .num_timings = 1,
2115         .bpc = 6,
2116         .size = {
2117                 .width = 157,
2118                 .height = 209,
2119         },
2120         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2121         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2122         .connector_type = DRM_MODE_CONNECTOR_DPI,
2123 };
2124
2125 static const struct display_timing evervision_vgg644804_timing = {
2126         .pixelclock = { 25175000, 25175000, 25175000 },
2127         .hactive = { 640, 640, 640 },
2128         .hfront_porch = { 16, 16, 16 },
2129         .hback_porch = { 82, 114, 170 },
2130         .hsync_len = { 5, 30, 30 },
2131         .vactive = { 480, 480, 480 },
2132         .vfront_porch = { 10, 10, 10 },
2133         .vback_porch = { 30, 32, 34 },
2134         .vsync_len = { 1, 3, 5 },
2135         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2136                  DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2137                  DISPLAY_FLAGS_SYNC_POSEDGE,
2138 };
2139
2140 static const struct panel_desc evervision_vgg644804 = {
2141         .timings = &evervision_vgg644804_timing,
2142         .num_timings = 1,
2143         .bpc = 8,
2144         .size = {
2145                 .width = 115,
2146                 .height = 86,
2147         },
2148         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2149         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2150 };
2151
2152 static const struct display_timing evervision_vgg804821_timing = {
2153         .pixelclock = { 27600000, 33300000, 50000000 },
2154         .hactive = { 800, 800, 800 },
2155         .hfront_porch = { 40, 66, 70 },
2156         .hback_porch = { 40, 67, 70 },
2157         .hsync_len = { 40, 67, 70 },
2158         .vactive = { 480, 480, 480 },
2159         .vfront_porch = { 6, 10, 10 },
2160         .vback_porch = { 7, 11, 11 },
2161         .vsync_len = { 7, 11, 11 },
2162         .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
2163                  DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2164                  DISPLAY_FLAGS_SYNC_NEGEDGE,
2165 };
2166
2167 static const struct panel_desc evervision_vgg804821 = {
2168         .timings = &evervision_vgg804821_timing,
2169         .num_timings = 1,
2170         .bpc = 8,
2171         .size = {
2172                 .width = 108,
2173                 .height = 64,
2174         },
2175         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2176         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2177 };
2178
2179 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
2180         .clock = 32260,
2181         .hdisplay = 800,
2182         .hsync_start = 800 + 168,
2183         .hsync_end = 800 + 168 + 64,
2184         .htotal = 800 + 168 + 64 + 88,
2185         .vdisplay = 480,
2186         .vsync_start = 480 + 37,
2187         .vsync_end = 480 + 37 + 2,
2188         .vtotal = 480 + 37 + 2 + 8,
2189 };
2190
2191 static const struct panel_desc foxlink_fl500wvr00_a0t = {
2192         .modes = &foxlink_fl500wvr00_a0t_mode,
2193         .num_modes = 1,
2194         .bpc = 8,
2195         .size = {
2196                 .width = 108,
2197                 .height = 65,
2198         },
2199         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2200 };
2201
2202 static const struct drm_display_mode frida_frd350h54004_modes[] = {
2203         { /* 60 Hz */
2204                 .clock = 6000,
2205                 .hdisplay = 320,
2206                 .hsync_start = 320 + 44,
2207                 .hsync_end = 320 + 44 + 16,
2208                 .htotal = 320 + 44 + 16 + 20,
2209                 .vdisplay = 240,
2210                 .vsync_start = 240 + 2,
2211                 .vsync_end = 240 + 2 + 6,
2212                 .vtotal = 240 + 2 + 6 + 2,
2213                 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2214         },
2215         { /* 50 Hz */
2216                 .clock = 5400,
2217                 .hdisplay = 320,
2218                 .hsync_start = 320 + 56,
2219                 .hsync_end = 320 + 56 + 16,
2220                 .htotal = 320 + 56 + 16 + 40,
2221                 .vdisplay = 240,
2222                 .vsync_start = 240 + 2,
2223                 .vsync_end = 240 + 2 + 6,
2224                 .vtotal = 240 + 2 + 6 + 2,
2225                 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2226         },
2227 };
2228
2229 static const struct panel_desc frida_frd350h54004 = {
2230         .modes = frida_frd350h54004_modes,
2231         .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2232         .bpc = 8,
2233         .size = {
2234                 .width = 77,
2235                 .height = 64,
2236         },
2237         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2238         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2239         .connector_type = DRM_MODE_CONNECTOR_DPI,
2240 };
2241
2242 static const struct drm_display_mode friendlyarm_hd702e_mode = {
2243         .clock          = 67185,
2244         .hdisplay       = 800,
2245         .hsync_start    = 800 + 20,
2246         .hsync_end      = 800 + 20 + 24,
2247         .htotal         = 800 + 20 + 24 + 20,
2248         .vdisplay       = 1280,
2249         .vsync_start    = 1280 + 4,
2250         .vsync_end      = 1280 + 4 + 8,
2251         .vtotal         = 1280 + 4 + 8 + 4,
2252         .flags          = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2253 };
2254
2255 static const struct panel_desc friendlyarm_hd702e = {
2256         .modes = &friendlyarm_hd702e_mode,
2257         .num_modes = 1,
2258         .size = {
2259                 .width  = 94,
2260                 .height = 151,
2261         },
2262 };
2263
2264 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2265         .clock = 9000,
2266         .hdisplay = 480,
2267         .hsync_start = 480 + 5,
2268         .hsync_end = 480 + 5 + 1,
2269         .htotal = 480 + 5 + 1 + 40,
2270         .vdisplay = 272,
2271         .vsync_start = 272 + 8,
2272         .vsync_end = 272 + 8 + 1,
2273         .vtotal = 272 + 8 + 1 + 8,
2274 };
2275
2276 static const struct panel_desc giantplus_gpg482739qs5 = {
2277         .modes = &giantplus_gpg482739qs5_mode,
2278         .num_modes = 1,
2279         .bpc = 8,
2280         .size = {
2281                 .width = 95,
2282                 .height = 54,
2283         },
2284         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2285 };
2286
2287 static const struct display_timing giantplus_gpm940b0_timing = {
2288         .pixelclock = { 13500000, 27000000, 27500000 },
2289         .hactive = { 320, 320, 320 },
2290         .hfront_porch = { 14, 686, 718 },
2291         .hback_porch = { 50, 70, 255 },
2292         .hsync_len = { 1, 1, 1 },
2293         .vactive = { 240, 240, 240 },
2294         .vfront_porch = { 1, 1, 179 },
2295         .vback_porch = { 1, 21, 31 },
2296         .vsync_len = { 1, 1, 6 },
2297         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2298 };
2299
2300 static const struct panel_desc giantplus_gpm940b0 = {
2301         .timings = &giantplus_gpm940b0_timing,
2302         .num_timings = 1,
2303         .bpc = 8,
2304         .size = {
2305                 .width = 60,
2306                 .height = 45,
2307         },
2308         .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2309         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2310 };
2311
2312 static const struct display_timing hannstar_hsd070pww1_timing = {
2313         .pixelclock = { 64300000, 71100000, 82000000 },
2314         .hactive = { 1280, 1280, 1280 },
2315         .hfront_porch = { 1, 1, 10 },
2316         .hback_porch = { 1, 1, 10 },
2317         /*
2318          * According to the data sheet, the minimum horizontal blanking interval
2319          * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2320          * minimum working horizontal blanking interval to be 60 clocks.
2321          */
2322         .hsync_len = { 58, 158, 661 },
2323         .vactive = { 800, 800, 800 },
2324         .vfront_porch = { 1, 1, 10 },
2325         .vback_porch = { 1, 1, 10 },
2326         .vsync_len = { 1, 21, 203 },
2327         .flags = DISPLAY_FLAGS_DE_HIGH,
2328 };
2329
2330 static const struct panel_desc hannstar_hsd070pww1 = {
2331         .timings = &hannstar_hsd070pww1_timing,
2332         .num_timings = 1,
2333         .bpc = 6,
2334         .size = {
2335                 .width = 151,
2336                 .height = 94,
2337         },
2338         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2339         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2340 };
2341
2342 static const struct display_timing hannstar_hsd100pxn1_timing = {
2343         .pixelclock = { 55000000, 65000000, 75000000 },
2344         .hactive = { 1024, 1024, 1024 },
2345         .hfront_porch = { 40, 40, 40 },
2346         .hback_porch = { 220, 220, 220 },
2347         .hsync_len = { 20, 60, 100 },
2348         .vactive = { 768, 768, 768 },
2349         .vfront_porch = { 7, 7, 7 },
2350         .vback_porch = { 21, 21, 21 },
2351         .vsync_len = { 10, 10, 10 },
2352         .flags = DISPLAY_FLAGS_DE_HIGH,
2353 };
2354
2355 static const struct panel_desc hannstar_hsd100pxn1 = {
2356         .timings = &hannstar_hsd100pxn1_timing,
2357         .num_timings = 1,
2358         .bpc = 6,
2359         .size = {
2360                 .width = 203,
2361                 .height = 152,
2362         },
2363         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2364         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2365 };
2366
2367 static const struct display_timing hannstar_hsd101pww2_timing = {
2368         .pixelclock = { 64300000, 71100000, 82000000 },
2369         .hactive = { 1280, 1280, 1280 },
2370         .hfront_porch = { 1, 1, 10 },
2371         .hback_porch = { 1, 1, 10 },
2372         .hsync_len = { 58, 158, 661 },
2373         .vactive = { 800, 800, 800 },
2374         .vfront_porch = { 1, 1, 10 },
2375         .vback_porch = { 1, 1, 10 },
2376         .vsync_len = { 1, 21, 203 },
2377         .flags = DISPLAY_FLAGS_DE_HIGH,
2378 };
2379
2380 static const struct panel_desc hannstar_hsd101pww2 = {
2381         .timings = &hannstar_hsd101pww2_timing,
2382         .num_timings = 1,
2383         .bpc = 8,
2384         .size = {
2385                 .width = 217,
2386                 .height = 136,
2387         },
2388         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2389         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2390 };
2391
2392 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2393         .clock = 33333,
2394         .hdisplay = 800,
2395         .hsync_start = 800 + 85,
2396         .hsync_end = 800 + 85 + 86,
2397         .htotal = 800 + 85 + 86 + 85,
2398         .vdisplay = 480,
2399         .vsync_start = 480 + 16,
2400         .vsync_end = 480 + 16 + 13,
2401         .vtotal = 480 + 16 + 13 + 16,
2402 };
2403
2404 static const struct panel_desc hitachi_tx23d38vm0caa = {
2405         .modes = &hitachi_tx23d38vm0caa_mode,
2406         .num_modes = 1,
2407         .bpc = 6,
2408         .size = {
2409                 .width = 195,
2410                 .height = 117,
2411         },
2412         .delay = {
2413                 .enable = 160,
2414                 .disable = 160,
2415         },
2416 };
2417
2418 static const struct drm_display_mode innolux_at043tn24_mode = {
2419         .clock = 9000,
2420         .hdisplay = 480,
2421         .hsync_start = 480 + 2,
2422         .hsync_end = 480 + 2 + 41,
2423         .htotal = 480 + 2 + 41 + 2,
2424         .vdisplay = 272,
2425         .vsync_start = 272 + 2,
2426         .vsync_end = 272 + 2 + 10,
2427         .vtotal = 272 + 2 + 10 + 2,
2428         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2429 };
2430
2431 static const struct panel_desc innolux_at043tn24 = {
2432         .modes = &innolux_at043tn24_mode,
2433         .num_modes = 1,
2434         .bpc = 8,
2435         .size = {
2436                 .width = 95,
2437                 .height = 54,
2438         },
2439         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2440         .connector_type = DRM_MODE_CONNECTOR_DPI,
2441         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2442 };
2443
2444 static const struct drm_display_mode innolux_at070tn92_mode = {
2445         .clock = 33333,
2446         .hdisplay = 800,
2447         .hsync_start = 800 + 210,
2448         .hsync_end = 800 + 210 + 20,
2449         .htotal = 800 + 210 + 20 + 46,
2450         .vdisplay = 480,
2451         .vsync_start = 480 + 22,
2452         .vsync_end = 480 + 22 + 10,
2453         .vtotal = 480 + 22 + 23 + 10,
2454 };
2455
2456 static const struct panel_desc innolux_at070tn92 = {
2457         .modes = &innolux_at070tn92_mode,
2458         .num_modes = 1,
2459         .size = {
2460                 .width = 154,
2461                 .height = 86,
2462         },
2463         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2464 };
2465
2466 static const struct display_timing innolux_g070ace_l01_timing = {
2467         .pixelclock = { 25200000, 35000000, 35700000 },
2468         .hactive = { 800, 800, 800 },
2469         .hfront_porch = { 30, 32, 87 },
2470         .hback_porch = { 30, 32, 87 },
2471         .hsync_len = { 1, 1, 1 },
2472         .vactive = { 480, 480, 480 },
2473         .vfront_porch = { 3, 3, 3 },
2474         .vback_porch = { 13, 13, 13 },
2475         .vsync_len = { 1, 1, 4 },
2476         .flags = DISPLAY_FLAGS_DE_HIGH,
2477 };
2478
2479 static const struct panel_desc innolux_g070ace_l01 = {
2480         .timings = &innolux_g070ace_l01_timing,
2481         .num_timings = 1,
2482         .bpc = 8,
2483         .size = {
2484                 .width = 152,
2485                 .height = 91,
2486         },
2487         .delay = {
2488                 .prepare = 10,
2489                 .enable = 50,
2490                 .disable = 50,
2491                 .unprepare = 500,
2492         },
2493         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2494         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2495         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2496 };
2497
2498 static const struct display_timing innolux_g070y2_l01_timing = {
2499         .pixelclock = { 28000000, 29500000, 32000000 },
2500         .hactive = { 800, 800, 800 },
2501         .hfront_porch = { 61, 91, 141 },
2502         .hback_porch = { 60, 90, 140 },
2503         .hsync_len = { 12, 12, 12 },
2504         .vactive = { 480, 480, 480 },
2505         .vfront_porch = { 4, 9, 30 },
2506         .vback_porch = { 4, 8, 28 },
2507         .vsync_len = { 2, 2, 2 },
2508         .flags = DISPLAY_FLAGS_DE_HIGH,
2509 };
2510
2511 static const struct panel_desc innolux_g070y2_l01 = {
2512         .timings = &innolux_g070y2_l01_timing,
2513         .num_timings = 1,
2514         .bpc = 8,
2515         .size = {
2516                 .width = 152,
2517                 .height = 91,
2518         },
2519         .delay = {
2520                 .prepare = 10,
2521                 .enable = 100,
2522                 .disable = 100,
2523                 .unprepare = 800,
2524         },
2525         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2526         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2527         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2528 };
2529
2530 static const struct display_timing innolux_g070ace_lh3_timing = {
2531         .pixelclock = { 25200000, 25400000, 35700000 },
2532         .hactive = { 800, 800, 800 },
2533         .hfront_porch = { 30, 32, 87 },
2534         .hback_porch = { 29, 31, 86 },
2535         .hsync_len = { 1, 1, 1 },
2536         .vactive = { 480, 480, 480 },
2537         .vfront_porch = { 4, 5, 65 },
2538         .vback_porch = { 3, 4, 65 },
2539         .vsync_len = { 1, 1, 1 },
2540         .flags = DISPLAY_FLAGS_DE_HIGH,
2541 };
2542
2543 static const struct panel_desc innolux_g070ace_lh3 = {
2544         .timings = &innolux_g070ace_lh3_timing,
2545         .num_timings = 1,
2546         .bpc = 8,
2547         .size = {
2548                 .width = 152,
2549                 .height = 91,
2550         },
2551         .delay = {
2552                 .prepare = 10,
2553                 .enable = 450,
2554                 .disable = 200,
2555                 .unprepare = 510,
2556         },
2557         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2558         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2559         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2560 };
2561
2562 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2563         .clock = 33333,
2564         .hdisplay = 800,
2565         .hsync_start = 800 + 210,
2566         .hsync_end = 800 + 210 + 20,
2567         .htotal = 800 + 210 + 20 + 46,
2568         .vdisplay = 480,
2569         .vsync_start = 480 + 22,
2570         .vsync_end = 480 + 22 + 10,
2571         .vtotal = 480 + 22 + 23 + 10,
2572 };
2573
2574 static const struct panel_desc innolux_g070y2_t02 = {
2575         .modes = &innolux_g070y2_t02_mode,
2576         .num_modes = 1,
2577         .bpc = 8,
2578         .size = {
2579                 .width = 152,
2580                 .height = 92,
2581         },
2582         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2583         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2584         .connector_type = DRM_MODE_CONNECTOR_DPI,
2585 };
2586
2587 static const struct display_timing innolux_g101ice_l01_timing = {
2588         .pixelclock = { 60400000, 71100000, 74700000 },
2589         .hactive = { 1280, 1280, 1280 },
2590         .hfront_porch = { 30, 60, 70 },
2591         .hback_porch = { 30, 60, 70 },
2592         .hsync_len = { 22, 40, 60 },
2593         .vactive = { 800, 800, 800 },
2594         .vfront_porch = { 3, 8, 14 },
2595         .vback_porch = { 3, 8, 14 },
2596         .vsync_len = { 4, 7, 12 },
2597         .flags = DISPLAY_FLAGS_DE_HIGH,
2598 };
2599
2600 static const struct panel_desc innolux_g101ice_l01 = {
2601         .timings = &innolux_g101ice_l01_timing,
2602         .num_timings = 1,
2603         .bpc = 8,
2604         .size = {
2605                 .width = 217,
2606                 .height = 135,
2607         },
2608         .delay = {
2609                 .enable = 200,
2610                 .disable = 200,
2611         },
2612         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2613         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2614         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2615 };
2616
2617 static const struct display_timing innolux_g121i1_l01_timing = {
2618         .pixelclock = { 67450000, 71000000, 74550000 },
2619         .hactive = { 1280, 1280, 1280 },
2620         .hfront_porch = { 40, 80, 160 },
2621         .hback_porch = { 39, 79, 159 },
2622         .hsync_len = { 1, 1, 1 },
2623         .vactive = { 800, 800, 800 },
2624         .vfront_porch = { 5, 11, 100 },
2625         .vback_porch = { 4, 11, 99 },
2626         .vsync_len = { 1, 1, 1 },
2627 };
2628
2629 static const struct panel_desc innolux_g121i1_l01 = {
2630         .timings = &innolux_g121i1_l01_timing,
2631         .num_timings = 1,
2632         .bpc = 6,
2633         .size = {
2634                 .width = 261,
2635                 .height = 163,
2636         },
2637         .delay = {
2638                 .enable = 200,
2639                 .disable = 20,
2640         },
2641         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2642         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2643 };
2644
2645 static const struct display_timing innolux_g121x1_l03_timings = {
2646         .pixelclock = { 57500000, 64900000, 74400000 },
2647         .hactive = { 1024, 1024, 1024 },
2648         .hfront_porch = { 90, 140, 190 },
2649         .hback_porch = { 90, 140, 190 },
2650         .hsync_len = { 36, 40, 60 },
2651         .vactive = { 768, 768, 768 },
2652         .vfront_porch = { 2, 15, 30 },
2653         .vback_porch = { 2, 15, 30 },
2654         .vsync_len = { 2, 8, 20 },
2655         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2656 };
2657
2658 static const struct panel_desc innolux_g121x1_l03 = {
2659         .timings = &innolux_g121x1_l03_timings,
2660         .num_timings = 1,
2661         .bpc = 6,
2662         .size = {
2663                 .width = 246,
2664                 .height = 185,
2665         },
2666         .delay = {
2667                 .enable = 200,
2668                 .unprepare = 200,
2669                 .disable = 400,
2670         },
2671         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2672         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2673         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2674 };
2675
2676 static const struct panel_desc innolux_g121xce_l01 = {
2677         .timings = &innolux_g121x1_l03_timings,
2678         .num_timings = 1,
2679         .bpc = 8,
2680         .size = {
2681                 .width = 246,
2682                 .height = 185,
2683         },
2684         .delay = {
2685                 .enable = 200,
2686                 .unprepare = 200,
2687                 .disable = 400,
2688         },
2689         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2690         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2691         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2692 };
2693
2694 static const struct display_timing innolux_g156hce_l01_timings = {
2695         .pixelclock = { 120000000, 141860000, 150000000 },
2696         .hactive = { 1920, 1920, 1920 },
2697         .hfront_porch = { 80, 90, 100 },
2698         .hback_porch = { 80, 90, 100 },
2699         .hsync_len = { 20, 30, 30 },
2700         .vactive = { 1080, 1080, 1080 },
2701         .vfront_porch = { 3, 10, 20 },
2702         .vback_porch = { 3, 10, 20 },
2703         .vsync_len = { 4, 10, 10 },
2704 };
2705
2706 static const struct panel_desc innolux_g156hce_l01 = {
2707         .timings = &innolux_g156hce_l01_timings,
2708         .num_timings = 1,
2709         .bpc = 8,
2710         .size = {
2711                 .width = 344,
2712                 .height = 194,
2713         },
2714         .delay = {
2715                 .prepare = 1,           /* T1+T2 */
2716                 .enable = 450,          /* T5 */
2717                 .disable = 200,         /* T6 */
2718                 .unprepare = 10,        /* T3+T7 */
2719         },
2720         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2721         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2722         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2723 };
2724
2725 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2726         .clock = 69300,
2727         .hdisplay = 1366,
2728         .hsync_start = 1366 + 16,
2729         .hsync_end = 1366 + 16 + 34,
2730         .htotal = 1366 + 16 + 34 + 50,
2731         .vdisplay = 768,
2732         .vsync_start = 768 + 2,
2733         .vsync_end = 768 + 2 + 6,
2734         .vtotal = 768 + 2 + 6 + 12,
2735 };
2736
2737 static const struct panel_desc innolux_n156bge_l21 = {
2738         .modes = &innolux_n156bge_l21_mode,
2739         .num_modes = 1,
2740         .bpc = 6,
2741         .size = {
2742                 .width = 344,
2743                 .height = 193,
2744         },
2745         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2746         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2747         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2748 };
2749
2750 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2751         .clock = 51501,
2752         .hdisplay = 1024,
2753         .hsync_start = 1024 + 128,
2754         .hsync_end = 1024 + 128 + 64,
2755         .htotal = 1024 + 128 + 64 + 128,
2756         .vdisplay = 600,
2757         .vsync_start = 600 + 16,
2758         .vsync_end = 600 + 16 + 4,
2759         .vtotal = 600 + 16 + 4 + 16,
2760 };
2761
2762 static const struct panel_desc innolux_zj070na_01p = {
2763         .modes = &innolux_zj070na_01p_mode,
2764         .num_modes = 1,
2765         .bpc = 6,
2766         .size = {
2767                 .width = 154,
2768                 .height = 90,
2769         },
2770 };
2771
2772 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2773         .pixelclock = { 5580000, 5850000, 6200000 },
2774         .hactive = { 320, 320, 320 },
2775         .hfront_porch = { 30, 30, 30 },
2776         .hback_porch = { 30, 30, 30 },
2777         .hsync_len = { 1, 5, 17 },
2778         .vactive = { 240, 240, 240 },
2779         .vfront_porch = { 6, 6, 6 },
2780         .vback_porch = { 5, 5, 5 },
2781         .vsync_len = { 1, 2, 11 },
2782         .flags = DISPLAY_FLAGS_DE_HIGH,
2783 };
2784
2785 static const struct panel_desc koe_tx14d24vm1bpa = {
2786         .timings = &koe_tx14d24vm1bpa_timing,
2787         .num_timings = 1,
2788         .bpc = 6,
2789         .size = {
2790                 .width = 115,
2791                 .height = 86,
2792         },
2793 };
2794
2795 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2796         .pixelclock = { 151820000, 156720000, 159780000 },
2797         .hactive = { 1920, 1920, 1920 },
2798         .hfront_porch = { 105, 130, 142 },
2799         .hback_porch = { 45, 70, 82 },
2800         .hsync_len = { 30, 30, 30 },
2801         .vactive = { 1200, 1200, 1200},
2802         .vfront_porch = { 3, 5, 10 },
2803         .vback_porch = { 2, 5, 10 },
2804         .vsync_len = { 5, 5, 5 },
2805         .flags = DISPLAY_FLAGS_DE_HIGH,
2806 };
2807
2808 static const struct panel_desc koe_tx26d202vm0bwa = {
2809         .timings = &koe_tx26d202vm0bwa_timing,
2810         .num_timings = 1,
2811         .bpc = 8,
2812         .size = {
2813                 .width = 217,
2814                 .height = 136,
2815         },
2816         .delay = {
2817                 .prepare = 1000,
2818                 .enable = 1000,
2819                 .unprepare = 1000,
2820                 .disable = 1000,
2821         },
2822         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2823         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2824         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2825 };
2826
2827 static const struct display_timing koe_tx31d200vm0baa_timing = {
2828         .pixelclock = { 39600000, 43200000, 48000000 },
2829         .hactive = { 1280, 1280, 1280 },
2830         .hfront_porch = { 16, 36, 56 },
2831         .hback_porch = { 16, 36, 56 },
2832         .hsync_len = { 8, 8, 8 },
2833         .vactive = { 480, 480, 480 },
2834         .vfront_porch = { 6, 21, 33 },
2835         .vback_porch = { 6, 21, 33 },
2836         .vsync_len = { 8, 8, 8 },
2837         .flags = DISPLAY_FLAGS_DE_HIGH,
2838 };
2839
2840 static const struct panel_desc koe_tx31d200vm0baa = {
2841         .timings = &koe_tx31d200vm0baa_timing,
2842         .num_timings = 1,
2843         .bpc = 6,
2844         .size = {
2845                 .width = 292,
2846                 .height = 109,
2847         },
2848         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2849         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2850 };
2851
2852 static const struct display_timing kyo_tcg121xglp_timing = {
2853         .pixelclock = { 52000000, 65000000, 71000000 },
2854         .hactive = { 1024, 1024, 1024 },
2855         .hfront_porch = { 2, 2, 2 },
2856         .hback_porch = { 2, 2, 2 },
2857         .hsync_len = { 86, 124, 244 },
2858         .vactive = { 768, 768, 768 },
2859         .vfront_porch = { 2, 2, 2 },
2860         .vback_porch = { 2, 2, 2 },
2861         .vsync_len = { 6, 34, 73 },
2862         .flags = DISPLAY_FLAGS_DE_HIGH,
2863 };
2864
2865 static const struct panel_desc kyo_tcg121xglp = {
2866         .timings = &kyo_tcg121xglp_timing,
2867         .num_timings = 1,
2868         .bpc = 8,
2869         .size = {
2870                 .width = 246,
2871                 .height = 184,
2872         },
2873         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2874         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2875 };
2876
2877 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2878         .clock = 7000,
2879         .hdisplay = 320,
2880         .hsync_start = 320 + 20,
2881         .hsync_end = 320 + 20 + 30,
2882         .htotal = 320 + 20 + 30 + 38,
2883         .vdisplay = 240,
2884         .vsync_start = 240 + 4,
2885         .vsync_end = 240 + 4 + 3,
2886         .vtotal = 240 + 4 + 3 + 15,
2887 };
2888
2889 static const struct panel_desc lemaker_bl035_rgb_002 = {
2890         .modes = &lemaker_bl035_rgb_002_mode,
2891         .num_modes = 1,
2892         .size = {
2893                 .width = 70,
2894                 .height = 52,
2895         },
2896         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2897         .bus_flags = DRM_BUS_FLAG_DE_LOW,
2898 };
2899
2900 static const struct display_timing lg_lb070wv8_timing = {
2901         .pixelclock = { 31950000, 33260000, 34600000 },
2902         .hactive = { 800, 800, 800 },
2903         .hfront_porch = { 88, 88, 88 },
2904         .hback_porch = { 88, 88, 88 },
2905         .hsync_len = { 80, 80, 80 },
2906         .vactive = { 480, 480, 480 },
2907         .vfront_porch = { 10, 10, 10 },
2908         .vback_porch = { 10, 10, 10 },
2909         .vsync_len = { 25, 25, 25 },
2910 };
2911
2912 static const struct panel_desc lg_lb070wv8 = {
2913         .timings = &lg_lb070wv8_timing,
2914         .num_timings = 1,
2915         .bpc = 8,
2916         .size = {
2917                 .width = 151,
2918                 .height = 91,
2919         },
2920         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2921         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2922 };
2923
2924 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = {
2925         .clock = 155127,
2926         .hdisplay = 1920,
2927         .hsync_start = 1920 + 128,
2928         .hsync_end = 1920 + 128 + 20,
2929         .htotal = 1920 + 128 + 20 + 12,
2930         .vdisplay = 1200,
2931         .vsync_start = 1200 + 19,
2932         .vsync_end = 1200 + 19 + 4,
2933         .vtotal = 1200 + 19 + 4 + 20,
2934 };
2935
2936 static const struct panel_desc lincolntech_lcd185_101ct = {
2937         .modes = &lincolntech_lcd185_101ct_mode,
2938         .bpc = 8,
2939         .num_modes = 1,
2940         .size = {
2941                 .width = 217,
2942                 .height = 136,
2943         },
2944         .delay = {
2945                 .prepare = 50,
2946                 .disable = 50,
2947         },
2948         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2949         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2950         .connector_type = DRM_MODE_CONNECTOR_LVDS,
2951 };
2952
2953 static const struct display_timing logictechno_lt161010_2nh_timing = {
2954         .pixelclock = { 26400000, 33300000, 46800000 },
2955         .hactive = { 800, 800, 800 },
2956         .hfront_porch = { 16, 210, 354 },
2957         .hback_porch = { 46, 46, 46 },
2958         .hsync_len = { 1, 20, 40 },
2959         .vactive = { 480, 480, 480 },
2960         .vfront_porch = { 7, 22, 147 },
2961         .vback_porch = { 23, 23, 23 },
2962         .vsync_len = { 1, 10, 20 },
2963         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2964                  DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2965                  DISPLAY_FLAGS_SYNC_POSEDGE,
2966 };
2967
2968 static const struct panel_desc logictechno_lt161010_2nh = {
2969         .timings = &logictechno_lt161010_2nh_timing,
2970         .num_timings = 1,
2971         .bpc = 6,
2972         .size = {
2973                 .width = 154,
2974                 .height = 86,
2975         },
2976         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2977         .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2978                      DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2979                      DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2980         .connector_type = DRM_MODE_CONNECTOR_DPI,
2981 };
2982
2983 static const struct display_timing logictechno_lt170410_2whc_timing = {
2984         .pixelclock = { 68900000, 71100000, 73400000 },
2985         .hactive = { 1280, 1280, 1280 },
2986         .hfront_porch = { 23, 60, 71 },
2987         .hback_porch = { 23, 60, 71 },
2988         .hsync_len = { 15, 40, 47 },
2989         .vactive = { 800, 800, 800 },
2990         .vfront_porch = { 5, 7, 10 },
2991         .vback_porch = { 5, 7, 10 },
2992         .vsync_len = { 6, 9, 12 },
2993         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2994                  DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2995                  DISPLAY_FLAGS_SYNC_POSEDGE,
2996 };
2997
2998 static const struct panel_desc logictechno_lt170410_2whc = {
2999         .timings = &logictechno_lt170410_2whc_timing,
3000         .num_timings = 1,
3001         .bpc = 8,
3002         .size = {
3003                 .width = 217,
3004                 .height = 136,
3005         },
3006         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3007         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3008         .connector_type = DRM_MODE_CONNECTOR_LVDS,
3009 };
3010
3011 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
3012         .clock = 33000,
3013         .hdisplay = 800,
3014         .hsync_start = 800 + 112,
3015         .hsync_end = 800 + 112 + 3,
3016         .htotal = 800 + 112 + 3 + 85,
3017         .vdisplay = 480,
3018         .vsync_start = 480 + 38,
3019         .vsync_end = 480 + 38 + 3,
3020         .vtotal = 480 + 38 + 3 + 29,
3021         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3022 };
3023
3024 static const struct panel_desc logictechno_lttd800480070_l2rt = {
3025         .modes = &logictechno_lttd800480070_l2rt_mode,
3026         .num_modes = 1,
3027         .bpc = 8,
3028         .size = {
3029                 .width = 154,
3030                 .height = 86,
3031         },
3032         .delay = {
3033                 .prepare = 45,
3034                 .enable = 100,
3035                 .disable = 100,
3036                 .unprepare = 45
3037         },
3038         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3039         .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3040         .connector_type = DRM_MODE_CONNECTOR_DPI,
3041 };
3042
3043 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
3044         .clock = 33000,
3045         .hdisplay = 800,
3046         .hsync_start = 800 + 154,
3047         .hsync_end = 800 + 154 + 3,
3048         .htotal = 800 + 154 + 3 + 43,
3049         .vdisplay = 480,
3050         .vsync_start = 480 + 47,
3051         .vsync_end = 480 + 47 + 3,
3052         .vtotal = 480 + 47 + 3 + 20,
3053         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3054 };
3055
3056 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
3057         .modes = &logictechno_lttd800480070_l6wh_rt_mode,
3058         .num_modes = 1,
3059         .bpc = 8,
3060         .size = {
3061                 .width = 154,
3062                 .height = 86,
3063         },
3064         .delay = {
3065                 .prepare = 45,
3066                 .enable = 100,
3067                 .disable = 100,
3068                 .unprepare = 45
3069         },
3070         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3071         .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3072         .connector_type = DRM_MODE_CONNECTOR_DPI,
3073 };
3074
3075 static const struct drm_display_mode logicpd_type_28_mode = {
3076         .clock = 9107,
3077         .hdisplay = 480,
3078         .hsync_start = 480 + 3,
3079         .hsync_end = 480 + 3 + 42,
3080         .htotal = 480 + 3 + 42 + 2,
3081
3082         .vdisplay = 272,
3083         .vsync_start = 272 + 2,
3084         .vsync_end = 272 + 2 + 11,
3085         .vtotal = 272 + 2 + 11 + 3,
3086         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3087 };
3088
3089 static const struct panel_desc logicpd_type_28 = {
3090         .modes = &logicpd_type_28_mode,
3091         .num_modes = 1,
3092         .bpc = 8,
3093         .size = {
3094                 .width = 105,
3095                 .height = 67,
3096         },
3097         .delay = {
3098                 .prepare = 200,
3099                 .enable = 200,
3100                 .unprepare = 200,
3101                 .disable = 200,
3102         },
3103         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3104         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3105                      DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
3106         .connector_type = DRM_MODE_CONNECTOR_DPI,
3107 };
3108
3109 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = {
3110         .clock = 150275,
3111         .hdisplay = 1920,
3112         .hsync_start = 1920 + 32,
3113         .hsync_end = 1920 + 32 + 52,
3114         .htotal = 1920 + 32 + 52 + 24,
3115         .vdisplay = 1200,
3116         .vsync_start = 1200 + 24,
3117         .vsync_end = 1200 + 24 + 8,
3118         .vtotal = 1200 + 24 + 8 + 3,
3119 };
3120
3121 static const struct panel_desc microtips_mf_101hiebcaf0_c = {
3122         .modes = &microtips_mf_101hiebcaf0_c_mode,
3123         .bpc = 8,
3124         .num_modes = 1,
3125         .size = {
3126                 .width = 217,
3127                 .height = 136,
3128         },
3129         .delay = {
3130                 .prepare = 50,
3131                 .disable = 50,
3132         },
3133         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3134         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3135         .connector_type = DRM_MODE_CONNECTOR_LVDS,
3136 };
3137
3138 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = {
3139         .clock = 93301,
3140         .hdisplay = 1920,
3141         .hsync_start = 1920 + 72,
3142         .hsync_end = 1920 + 72 + 72,
3143         .htotal = 1920 + 72 + 72 + 72,
3144         .vdisplay = 720,
3145         .vsync_start = 720 + 3,
3146         .vsync_end = 720 + 3 + 3,
3147         .vtotal = 720 + 3 + 3 + 2,
3148 };
3149
3150 static const struct panel_desc microtips_mf_103hieb0ga0 = {
3151         .modes = &microtips_mf_103hieb0ga0_mode,
3152         .bpc = 8,
3153         .num_modes = 1,
3154         .size = {
3155                 .width = 244,
3156                 .height = 92,
3157         },
3158         .delay = {
3159                 .prepare = 50,
3160                 .disable = 50,
3161         },
3162         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3163         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3164         .connector_type = DRM_MODE_CONNECTOR_LVDS,
3165 };
3166
3167 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
3168         .clock = 30400,
3169         .hdisplay = 800,
3170         .hsync_start = 800 + 0,
3171         .hsync_end = 800 + 1,
3172         .htotal = 800 + 0 + 1 + 160,
3173         .vdisplay = 480,
3174         .vsync_start = 480 + 0,
3175         .vsync_end = 480 + 48 + 1,
3176         .vtotal = 480 + 48 + 1 + 0,
3177         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3178 };
3179
3180 static const struct panel_desc mitsubishi_aa070mc01 = {
3181         .modes = &mitsubishi_aa070mc01_mode,
3182         .num_modes = 1,
3183         .bpc = 8,
3184         .size = {
3185                 .width = 152,
3186                 .height = 91,
3187         },
3188
3189         .delay = {
3190                 .enable = 200,
3191                 .unprepare = 200,
3192                 .disable = 400,
3193         },
3194         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3195         .connector_type = DRM_MODE_CONNECTOR_LVDS,
3196         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3197 };
3198
3199 static const struct drm_display_mode mitsubishi_aa084xe01_mode = {
3200         .clock = 56234,
3201         .hdisplay = 1024,
3202         .hsync_start = 1024 + 24,
3203         .hsync_end = 1024 + 24 + 63,
3204         .htotal = 1024 + 24 + 63 + 1,
3205         .vdisplay = 768,
3206         .vsync_start = 768 + 3,
3207         .vsync_end = 768 + 3 + 6,
3208         .vtotal = 768 + 3 + 6 + 1,
3209         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3210 };
3211
3212 static const struct panel_desc mitsubishi_aa084xe01 = {
3213         .modes = &mitsubishi_aa084xe01_mode,
3214         .num_modes = 1,
3215         .bpc = 8,
3216         .size = {
3217                 .width = 1024,
3218                 .height = 768,
3219         },
3220         .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3221         .connector_type = DRM_MODE_CONNECTOR_DPI,
3222         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3223 };
3224
3225 static const struct display_timing multi_inno_mi0700s4t_6_timing = {
3226         .pixelclock = { 29000000, 33000000, 38000000 },
3227         .hactive = { 800, 800, 800 },
3228         .hfront_porch = { 180, 210, 240 },
3229         .hback_porch = { 16, 16, 16 },
3230         .hsync_len = { 30, 30, 30 },
3231         .vactive = { 480, 480, 480 },
3232         .vfront_porch = { 12, 22, 32 },
3233         .vback_porch = { 10, 10, 10 },
3234         .vsync_len = { 13, 13, 13 },
3235         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3236                  DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3237                  DISPLAY_FLAGS_SYNC_POSEDGE,
3238 };
3239
3240 static const struct panel_desc multi_inno_mi0700s4t_6 = {
3241         .timings = &multi_inno_mi0700s4t_6_timing,
3242         .num_timings = 1,
3243         .bpc = 8,
3244         .size = {
3245                 .width = 154,
3246                 .height = 86,
3247         },
3248         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3249         .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3250                      DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3251                      DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3252         .connector_type = DRM_MODE_CONNECTOR_DPI,
3253 };
3254
3255 static const struct display_timing multi_inno_mi0800ft_9_timing = {
3256         .pixelclock = { 32000000, 40000000, 50000000 },
3257         .hactive = { 800, 800, 800 },
3258         .hfront_porch = { 16, 210, 354 },
3259         .hback_porch = { 6, 26, 45 },
3260         .hsync_len = { 1, 20, 40 },
3261         .vactive = { 600, 600, 600 },
3262         .vfront_porch = { 1, 12, 77 },
3263         .vback_porch = { 3, 13, 22 },
3264         .vsync_len = { 1, 10, 20 },
3265         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3266                  DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3267                  DISPLAY_FLAGS_SYNC_POSEDGE,
3268 };
3269
3270 static const struct panel_desc multi_inno_mi0800ft_9 = {
3271         .timings = &multi_inno_mi0800ft_9_timing,
3272         .num_timings = 1,
3273         .bpc = 8,
3274         .size = {
3275                 .width = 162,
3276                 .height = 122,
3277         },
3278         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3279         .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3280                      DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3281                      DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3282         .connector_type = DRM_MODE_CONNECTOR_DPI,
3283 };
3284
3285 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
3286         .pixelclock = { 68900000, 70000000, 73400000 },
3287         .hactive = { 1280, 1280, 1280 },
3288         .hfront_porch = { 30, 60, 71 },
3289         .hback_porch = { 30, 60, 71 },
3290         .hsync_len = { 10, 10, 48 },
3291         .vactive = { 800, 800, 800 },
3292         .vfront_porch = { 5, 10, 10 },
3293         .vback_porch = { 5, 10, 10 },
3294         .vsync_len = { 5, 6, 13 },
3295         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3296                  DISPLAY_FLAGS_DE_HIGH,
3297 };
3298
3299 static const struct panel_desc multi_inno_mi1010ait_1cp = {
3300         .timings = &multi_inno_mi1010ait_1cp_timing,
3301         .num_timings = 1,
3302         .bpc = 8,
3303         .size = {
3304                 .width = 217,
3305                 .height = 136,
3306         },
3307         .delay = {
3308                 .enable = 50,
3309                 .disable = 50,
3310         },
3311         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3312         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3313         .connector_type = DRM_MODE_CONNECTOR_LVDS,
3314 };
3315
3316 static const struct display_timing nec_nl12880bc20_05_timing = {
3317         .pixelclock = { 67000000, 71000000, 75000000 },
3318         .hactive = { 1280, 1280, 1280 },
3319         .hfront_porch = { 2, 30, 30 },
3320         .hback_porch = { 6, 100, 100 },
3321         .hsync_len = { 2, 30, 30 },
3322         .vactive = { 800, 800, 800 },
3323         .vfront_porch = { 5, 5, 5 },
3324         .vback_porch = { 11, 11, 11 },
3325         .vsync_len = { 7, 7, 7 },
3326 };
3327
3328 static const struct panel_desc nec_nl12880bc20_05 = {
3329         .timings = &nec_nl12880bc20_05_timing,
3330         .num_timings = 1,
3331         .bpc = 8,
3332         .size = {
3333                 .width = 261,
3334                 .height = 163,
3335         },
3336         .delay = {
3337                 .enable = 50,
3338                 .disable = 50,
3339         },
3340         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3341         .connector_type = DRM_MODE_CONNECTOR_LVDS,
3342 };
3343
3344 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
3345         .clock = 10870,
3346         .hdisplay = 480,
3347         .hsync_start = 480 + 2,
3348         .hsync_end = 480 + 2 + 41,
3349         .htotal = 480 + 2 + 41 + 2,
3350         .vdisplay = 272,
3351         .vsync_start = 272 + 2,
3352         .vsync_end = 272 + 2 + 4,
3353         .vtotal = 272 + 2 + 4 + 2,
3354         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3355 };
3356
3357 static const struct panel_desc nec_nl4827hc19_05b = {
3358         .modes = &nec_nl4827hc19_05b_mode,
3359         .num_modes = 1,
3360         .bpc = 8,
3361         .size = {
3362                 .width = 95,
3363                 .height = 54,
3364         },
3365         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3366         .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3367 };
3368
3369 static const struct drm_display_mode netron_dy_e231732_mode = {
3370         .clock = 66000,
3371         .hdisplay = 1024,
3372         .hsync_start = 1024 + 160,
3373         .hsync_end = 1024 + 160 + 70,
3374         .htotal = 1024 + 160 + 70 + 90,
3375         .vdisplay = 600,
3376         .vsync_start = 600 + 127,
3377         .vsync_end = 600 + 127 + 20,
3378         .vtotal = 600 + 127 + 20 + 3,
3379 };
3380
3381 static const struct panel_desc netron_dy_e231732 = {
3382         .modes = &netron_dy_e231732_mode,
3383         .num_modes = 1,
3384         .size = {
3385                 .width = 154,
3386                 .height = 87,
3387         },
3388         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3389 };
3390
3391 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3392         .clock = 9000,
3393         .hdisplay = 480,
3394         .hsync_start = 480 + 2,
3395         .hsync_end = 480 + 2 + 41,
3396         .htotal = 480 + 2 + 41 + 2,
3397         .vdisplay = 272,
3398         .vsync_start = 272 + 2,
3399         .vsync_end = 272 + 2 + 10,
3400         .vtotal = 272 + 2 + 10 + 2,
3401         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3402 };
3403
3404 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3405         .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3406         .num_modes = 1,
3407         .bpc = 8,
3408         .size = {
3409                 .width = 95,
3410                 .height = 54,
3411         },
3412         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3413         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3414                      DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3415         .connector_type = DRM_MODE_CONNECTOR_DPI,
3416 };
3417
3418 static const struct display_timing nlt_nl192108ac18_02d_timing = {
3419         .pixelclock = { 130000000, 148350000, 163000000 },
3420         .hactive = { 1920, 1920, 1920 },
3421         .hfront_porch = { 80, 100, 100 },
3422         .hback_porch = { 100, 120, 120 },
3423         .hsync_len = { 50, 60, 60 },
3424         .vactive = { 1080, 1080, 1080 },
3425         .vfront_porch = { 12, 30, 30 },
3426         .vback_porch = { 4, 10, 10 },
3427         .vsync_len = { 4, 5, 5 },
3428 };
3429
3430 static const struct panel_desc nlt_nl192108ac18_02d = {
3431         .timings = &nlt_nl192108ac18_02d_timing,
3432         .num_timings = 1,
3433         .bpc = 8,
3434         .size = {
3435                 .width = 344,
3436                 .height = 194,
3437         },
3438         .delay = {
3439                 .unprepare = 500,
3440         },
3441         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3442         .connector_type = DRM_MODE_CONNECTOR_LVDS,
3443 };
3444
3445 static const struct drm_display_mode nvd_9128_mode = {
3446         .clock = 29500,
3447         .hdisplay = 800,
3448         .hsync_start = 800 + 130,
3449         .hsync_end = 800 + 130 + 98,
3450         .htotal = 800 + 0 + 130 + 98,
3451         .vdisplay = 480,
3452         .vsync_start = 480 + 10,
3453         .vsync_end = 480 + 10 + 50,
3454         .vtotal = 480 + 0 + 10 + 50,
3455 };
3456
3457 static const struct panel_desc nvd_9128 = {
3458         .modes = &nvd_9128_mode,
3459         .num_modes = 1,
3460         .bpc = 8,
3461         .size = {
3462                 .width = 156,
3463                 .height = 88,
3464         },
3465         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3466         .connector_type = DRM_MODE_CONNECTOR_LVDS,
3467 };
3468
3469 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3470         .pixelclock = { 30000000, 30000000, 40000000 },
3471         .hactive = { 800, 800, 800 },
3472         .hfront_porch = { 40, 40, 40 },
3473         .hback_porch = { 40, 40, 40 },
3474         .hsync_len = { 1, 48, 48 },
3475         .vactive = { 480, 480, 480 },
3476         .vfront_porch = { 13, 13, 13 },
3477         .vback_porch = { 29, 29, 29 },
3478         .vsync_len = { 3, 3, 3 },
3479         .flags = DISPLAY_FLAGS_DE_HIGH,
3480 };
3481
3482 static const struct panel_desc okaya_rs800480t_7x0gp = {
3483         .timings = &okaya_rs800480t_7x0gp_timing,
3484         .num_timings = 1,
3485         .bpc = 6,
3486         .size = {
3487                 .width = 154,
3488                 .height = 87,
3489         },
3490         .delay = {
3491                 .prepare = 41,
3492                 .enable = 50,
3493                 .unprepare = 41,
3494                 .disable = 50,
3495         },
3496         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3497 };
3498
3499 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3500         .clock = 9000,
3501         .hdisplay = 480,
3502         .hsync_start = 480 + 5,
3503         .hsync_end = 480 + 5 + 30,
3504         .htotal = 480 + 5 + 30 + 10,
3505         .vdisplay = 272,
3506         .vsync_start = 272 + 8,
3507         .vsync_end = 272 + 8 + 5,
3508         .vtotal = 272 + 8 + 5 + 3,
3509 };
3510
3511 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3512         .modes = &olimex_lcd_olinuxino_43ts_mode,
3513         .num_modes = 1,
3514         .size = {
3515                 .width = 95,
3516                 .height = 54,
3517         },
3518         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3519 };
3520
3521 static const struct display_timing ontat_kd50g21_40nt_a1_timing = {
3522         .pixelclock = { 30000000, 30000000, 50000000 },
3523         .hactive = { 800, 800, 800 },
3524         .hfront_porch = { 1, 40, 255 },
3525         .hback_porch = { 1, 40, 87 },
3526         .hsync_len = { 1, 48, 87 },
3527         .vactive = { 480, 480, 480 },
3528         .vfront_porch = { 1, 13, 255 },
3529         .vback_porch = { 1, 29, 29 },
3530         .vsync_len = { 3, 3, 31 },
3531         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3532                  DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3533 };
3534
3535 static const struct panel_desc ontat_kd50g21_40nt_a1 = {
3536         .timings = &ontat_kd50g21_40nt_a1_timing,
3537         .num_timings = 1,
3538         .bpc = 8,
3539         .size = {
3540                 .width = 108,
3541                 .height = 65,
3542         },
3543         .delay = {
3544                 .prepare = 147,         /* 5 VSDs */
3545                 .enable = 147,          /* 5 VSDs */
3546                 .disable = 88,          /* 3 VSDs */
3547                 .unprepare = 117,       /* 4 VSDs */
3548         },
3549         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3550         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3551         .connector_type = DRM_MODE_CONNECTOR_DPI,
3552 };
3553
3554 /*
3555  * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3556  * pixel clocks, but this is the timing that was being used in the Adafruit
3557  * installation instructions.
3558  */
3559 static const struct drm_display_mode ontat_yx700wv03_mode = {
3560         .clock = 29500,
3561         .hdisplay = 800,
3562         .hsync_start = 824,
3563         .hsync_end = 896,
3564         .htotal = 992,
3565         .vdisplay = 480,
3566         .vsync_start = 483,
3567         .vsync_end = 493,
3568         .vtotal = 500,
3569         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3570 };
3571
3572 /*
3573  * Specification at:
3574  * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3575  */
3576 static const struct panel_desc ontat_yx700wv03 = {
3577         .modes = &ontat_yx700wv03_mode,
3578         .num_modes = 1,
3579         .bpc = 8,
3580         .size = {
3581                 .width = 154,
3582                 .height = 83,
3583         },
3584         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3585 };
3586
3587 static const struct drm_display_mode ortustech_com37h3m_mode  = {
3588         .clock = 22230,
3589         .hdisplay = 480,
3590         .hsync_start = 480 + 40,
3591         .hsync_end = 480 + 40 + 10,
3592         .htotal = 480 + 40 + 10 + 40,
3593         .vdisplay = 640,
3594         .vsync_start = 640 + 4,
3595         .vsync_end = 640 + 4 + 2,
3596         .vtotal = 640 + 4 + 2 + 4,
3597         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3598 };
3599
3600 static const struct panel_desc ortustech_com37h3m = {
3601         .modes = &ortustech_com37h3m_mode,
3602         .num_modes = 1,
3603         .bpc = 8,
3604         .size = {
3605                 .width = 56,    /* 56.16mm */
3606                 .height = 75,   /* 74.88mm */
3607         },
3608         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3609         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3610                      DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3611 };
3612
3613 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
3614         .clock = 25000,
3615         .hdisplay = 480,
3616         .hsync_start = 480 + 10,
3617         .hsync_end = 480 + 10 + 10,
3618         .htotal = 480 + 10 + 10 + 15,
3619         .vdisplay = 800,
3620         .vsync_start = 800 + 3,
3621         .vsync_end = 800 + 3 + 3,
3622         .vtotal = 800 + 3 + 3 + 3,
3623 };
3624
3625 static const struct panel_desc ortustech_com43h4m85ulc = {
3626         .modes = &ortustech_com43h4m85ulc_mode,
3627         .num_modes = 1,
3628         .bpc = 6,
3629         .size = {
3630                 .width = 56,
3631                 .height = 93,
3632         },
3633         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3634         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3635         .connector_type = DRM_MODE_CONNECTOR_DPI,
3636 };
3637
3638 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode  = {
3639         .clock = 33000,
3640         .hdisplay = 800,
3641         .hsync_start = 800 + 210,
3642         .hsync_end = 800 + 210 + 30,
3643         .htotal = 800 + 210 + 30 + 16,
3644         .vdisplay = 480,
3645         .vsync_start = 480 + 22,
3646         .vsync_end = 480 + 22 + 13,
3647         .vtotal = 480 + 22 + 13 + 10,
3648         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3649 };
3650
3651 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3652         .modes = &osddisplays_osd070t1718_19ts_mode,
3653         .num_modes = 1,
3654         .bpc = 8,
3655         .size = {
3656                 .width = 152,
3657                 .height = 91,
3658         },
3659         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3660         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3661                 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3662         .connector_type = DRM_MODE_CONNECTOR_DPI,
3663 };
3664
3665 static const struct drm_display_mode pda_91_00156_a0_mode = {
3666         .clock = 33300,
3667         .hdisplay = 800,
3668         .hsync_start = 800 + 1,
3669         .hsync_end = 800 + 1 + 64,
3670         .htotal = 800 + 1 + 64 + 64,
3671         .vdisplay = 480,
3672         .vsync_start = 480 + 1,
3673         .vsync_end = 480 + 1 + 23,
3674         .vtotal = 480 + 1 + 23 + 22,
3675 };
3676
3677 static const struct panel_desc pda_91_00156_a0  = {
3678         .modes = &pda_91_00156_a0_mode,
3679         .num_modes = 1,
3680         .size = {
3681                 .width = 152,
3682                 .height = 91,
3683         },
3684         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3685 };
3686
3687 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = {
3688         .clock = 66500,
3689         .hdisplay = 1280,
3690         .hsync_start = 1280 + 12,
3691         .hsync_end = 1280 + 12 + 20,
3692         .htotal = 1280 + 12 + 20 + 56,
3693         .vdisplay = 800,
3694         .vsync_start = 800 + 1,
3695         .vsync_end = 800 + 1 + 3,
3696         .vtotal = 800 + 1 + 3 + 20,
3697         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3698 };
3699
3700 static const struct panel_desc powertip_ph128800t006_zhc01 = {
3701         .modes = &powertip_ph128800t006_zhc01_mode,
3702         .num_modes = 1,
3703         .bpc = 8,
3704         .size = {
3705                 .width = 216,
3706                 .height = 135,
3707         },
3708         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3709         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3710         .connector_type = DRM_MODE_CONNECTOR_LVDS,
3711 };
3712
3713 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3714         .clock = 24750,
3715         .hdisplay = 800,
3716         .hsync_start = 800 + 54,
3717         .hsync_end = 800 + 54 + 2,
3718         .htotal = 800 + 54 + 2 + 44,
3719         .vdisplay = 480,
3720         .vsync_start = 480 + 49,
3721         .vsync_end = 480 + 49 + 2,
3722         .vtotal = 480 + 49 + 2 + 22,
3723         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3724 };
3725
3726 static const struct panel_desc powertip_ph800480t013_idf02  = {
3727         .modes = &powertip_ph800480t013_idf02_mode,
3728         .num_modes = 1,
3729         .bpc = 8,
3730         .size = {
3731                 .width = 152,
3732                 .height = 91,
3733         },
3734         .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3735                      DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3736                      DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3737         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3738         .connector_type = DRM_MODE_CONNECTOR_DPI,
3739 };
3740
3741 static const struct drm_display_mode primeview_pm070wl4_mode = {
3742         .clock = 32000,
3743         .hdisplay = 800,
3744         .hsync_start = 800 + 42,
3745         .hsync_end = 800 + 42 + 128,
3746         .htotal = 800 + 42 + 128 + 86,
3747         .vdisplay = 480,
3748         .vsync_start = 480 + 10,
3749         .vsync_end = 480 + 10 + 2,
3750         .vtotal = 480 + 10 + 2 + 33,
3751         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3752 };
3753
3754 static const struct panel_desc primeview_pm070wl4 = {
3755         .modes = &primeview_pm070wl4_mode,
3756         .num_modes = 1,
3757         .bpc = 6,
3758         .size = {
3759                 .width = 152,
3760                 .height = 91,
3761         },
3762         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3763         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3764         .connector_type = DRM_MODE_CONNECTOR_DPI,
3765 };
3766
3767 static const struct drm_display_mode qd43003c0_40_mode = {
3768         .clock = 9000,
3769         .hdisplay = 480,
3770         .hsync_start = 480 + 8,
3771         .hsync_end = 480 + 8 + 4,
3772         .htotal = 480 + 8 + 4 + 39,
3773         .vdisplay = 272,
3774         .vsync_start = 272 + 4,
3775         .vsync_end = 272 + 4 + 10,
3776         .vtotal = 272 + 4 + 10 + 2,
3777 };
3778
3779 static const struct panel_desc qd43003c0_40 = {
3780         .modes = &qd43003c0_40_mode,
3781         .num_modes = 1,
3782         .bpc = 8,
3783         .size = {
3784                 .width = 95,
3785                 .height = 53,
3786         },
3787         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3788 };
3789
3790 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3791         { /* 60 Hz */
3792                 .clock = 10800,
3793                 .hdisplay = 480,
3794                 .hsync_start = 480 + 77,
3795                 .hsync_end = 480 + 77 + 41,
3796                 .htotal = 480 + 77 + 41 + 2,
3797                 .vdisplay = 272,
3798                 .vsync_start = 272 + 16,
3799                 .vsync_end = 272 + 16 + 10,
3800                 .vtotal = 272 + 16 + 10 + 2,
3801                 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3802         },
3803         { /* 50 Hz */
3804                 .clock = 10800,
3805                 .hdisplay = 480,
3806                 .hsync_start = 480 + 17,
3807                 .hsync_end = 480 + 17 + 41,
3808                 .htotal = 480 + 17 + 41 + 2,
3809                 .vdisplay = 272,
3810                 .vsync_start = 272 + 116,
3811                 .vsync_end = 272 + 116 + 10,
3812                 .vtotal = 272 + 116 + 10 + 2,
3813                 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3814         },
3815 };
3816
3817 static const struct panel_desc qishenglong_gopher2b_lcd = {
3818         .modes = qishenglong_gopher2b_lcd_modes,
3819         .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3820         .bpc = 8,
3821         .size = {
3822                 .width = 95,
3823                 .height = 54,
3824         },
3825         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3826         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3827         .connector_type = DRM_MODE_CONNECTOR_DPI,
3828 };
3829
3830 static const struct display_timing rocktech_rk043fn48h_timing = {
3831         .pixelclock = { 6000000, 9000000, 12000000 },
3832         .hactive = { 480, 480, 480 },
3833         .hback_porch = { 8, 43, 43 },
3834         .hfront_porch = { 2, 8, 10 },
3835         .hsync_len = { 1, 1, 1 },
3836         .vactive = { 272, 272, 272 },
3837         .vback_porch = { 2, 12, 26 },
3838         .vfront_porch = { 1, 4, 4 },
3839         .vsync_len = { 1, 10, 10 },
3840         .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
3841                  DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3842                  DISPLAY_FLAGS_SYNC_POSEDGE,
3843 };
3844
3845 static const struct panel_desc rocktech_rk043fn48h = {
3846         .timings = &rocktech_rk043fn48h_timing,
3847         .num_timings = 1,
3848         .bpc = 8,
3849         .size = {
3850                 .width = 95,
3851                 .height = 54,
3852         },
3853         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3854         .connector_type = DRM_MODE_CONNECTOR_DPI,
3855 };
3856
3857 static const struct display_timing rocktech_rk070er9427_timing = {
3858         .pixelclock = { 26400000, 33300000, 46800000 },
3859         .hactive = { 800, 800, 800 },
3860         .hfront_porch = { 16, 210, 354 },
3861         .hback_porch = { 46, 46, 46 },
3862         .hsync_len = { 1, 1, 1 },
3863         .vactive = { 480, 480, 480 },
3864         .vfront_porch = { 7, 22, 147 },
3865         .vback_porch = { 23, 23, 23 },
3866         .vsync_len = { 1, 1, 1 },
3867         .flags = DISPLAY_FLAGS_DE_HIGH,
3868 };
3869
3870 static const struct panel_desc rocktech_rk070er9427 = {
3871         .timings = &rocktech_rk070er9427_timing,
3872         .num_timings = 1,
3873         .bpc = 6,
3874         .size = {
3875                 .width = 154,
3876                 .height = 86,
3877         },
3878         .delay = {
3879                 .prepare = 41,
3880                 .enable = 50,
3881                 .unprepare = 41,
3882                 .disable = 50,
3883         },
3884         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3885 };
3886
3887 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3888         .clock = 71100,
3889         .hdisplay = 1280,
3890         .hsync_start = 1280 + 48,
3891         .hsync_end = 1280 + 48 + 32,
3892         .htotal = 1280 + 48 + 32 + 80,
3893         .vdisplay = 800,
3894         .vsync_start = 800 + 2,
3895         .vsync_end = 800 + 2 + 5,
3896         .vtotal = 800 + 2 + 5 + 16,
3897 };
3898
3899 static const struct panel_desc rocktech_rk101ii01d_ct = {
3900         .modes = &rocktech_rk101ii01d_ct_mode,
3901         .bpc = 8,
3902         .num_modes = 1,
3903         .size = {
3904                 .width = 217,
3905                 .height = 136,
3906         },
3907         .delay = {
3908                 .prepare = 50,
3909                 .disable = 50,
3910         },
3911         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3912         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3913         .connector_type = DRM_MODE_CONNECTOR_LVDS,
3914 };
3915
3916 static const struct display_timing samsung_ltl101al01_timing = {
3917         .pixelclock = { 66663000, 66663000, 66663000 },
3918         .hactive = { 1280, 1280, 1280 },
3919         .hfront_porch = { 18, 18, 18 },
3920         .hback_porch = { 36, 36, 36 },
3921         .hsync_len = { 16, 16, 16 },
3922         .vactive = { 800, 800, 800 },
3923         .vfront_porch = { 4, 4, 4 },
3924         .vback_porch = { 16, 16, 16 },
3925         .vsync_len = { 3, 3, 3 },
3926         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3927 };
3928
3929 static const struct panel_desc samsung_ltl101al01 = {
3930         .timings = &samsung_ltl101al01_timing,
3931         .num_timings = 1,
3932         .bpc = 8,
3933         .size = {
3934                 .width = 217,
3935                 .height = 135,
3936         },
3937         .delay = {
3938                 .prepare = 40,
3939                 .enable = 300,
3940                 .disable = 200,
3941                 .unprepare = 600,
3942         },
3943         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3944         .connector_type = DRM_MODE_CONNECTOR_LVDS,
3945 };
3946
3947 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3948         .clock = 54030,
3949         .hdisplay = 1024,
3950         .hsync_start = 1024 + 24,
3951         .hsync_end = 1024 + 24 + 136,
3952         .htotal = 1024 + 24 + 136 + 160,
3953         .vdisplay = 600,
3954         .vsync_start = 600 + 3,
3955         .vsync_end = 600 + 3 + 6,
3956         .vtotal = 600 + 3 + 6 + 61,
3957 };
3958
3959 static const struct panel_desc samsung_ltn101nt05 = {
3960         .modes = &samsung_ltn101nt05_mode,
3961         .num_modes = 1,
3962         .bpc = 6,
3963         .size = {
3964                 .width = 223,
3965                 .height = 125,
3966         },
3967         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3968         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3969         .connector_type = DRM_MODE_CONNECTOR_LVDS,
3970 };
3971
3972 static const struct display_timing satoz_sat050at40h12r2_timing = {
3973         .pixelclock = {33300000, 33300000, 50000000},
3974         .hactive = {800, 800, 800},
3975         .hfront_porch = {16, 210, 354},
3976         .hback_porch = {46, 46, 46},
3977         .hsync_len = {1, 1, 40},
3978         .vactive = {480, 480, 480},
3979         .vfront_porch = {7, 22, 147},
3980         .vback_porch = {23, 23, 23},
3981         .vsync_len = {1, 1, 20},
3982 };
3983
3984 static const struct panel_desc satoz_sat050at40h12r2 = {
3985         .timings = &satoz_sat050at40h12r2_timing,
3986         .num_timings = 1,
3987         .bpc = 8,
3988         .size = {
3989                 .width = 108,
3990                 .height = 65,
3991         },
3992         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3993         .connector_type = DRM_MODE_CONNECTOR_LVDS,
3994 };
3995
3996 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3997         .clock = 33260,
3998         .hdisplay = 800,
3999         .hsync_start = 800 + 64,
4000         .hsync_end = 800 + 64 + 128,
4001         .htotal = 800 + 64 + 128 + 64,
4002         .vdisplay = 480,
4003         .vsync_start = 480 + 8,
4004         .vsync_end = 480 + 8 + 2,
4005         .vtotal = 480 + 8 + 2 + 35,
4006         .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
4007 };
4008
4009 static const struct panel_desc sharp_lq070y3dg3b = {
4010         .modes = &sharp_lq070y3dg3b_mode,
4011         .num_modes = 1,
4012         .bpc = 8,
4013         .size = {
4014                 .width = 152,   /* 152.4mm */
4015                 .height = 91,   /* 91.4mm */
4016         },
4017         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4018         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
4019                      DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
4020 };
4021
4022 static const struct drm_display_mode sharp_lq035q7db03_mode = {
4023         .clock = 5500,
4024         .hdisplay = 240,
4025         .hsync_start = 240 + 16,
4026         .hsync_end = 240 + 16 + 7,
4027         .htotal = 240 + 16 + 7 + 5,
4028         .vdisplay = 320,
4029         .vsync_start = 320 + 9,
4030         .vsync_end = 320 + 9 + 1,
4031         .vtotal = 320 + 9 + 1 + 7,
4032 };
4033
4034 static const struct panel_desc sharp_lq035q7db03 = {
4035         .modes = &sharp_lq035q7db03_mode,
4036         .num_modes = 1,
4037         .bpc = 6,
4038         .size = {
4039                 .width = 54,
4040                 .height = 72,
4041         },
4042         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4043 };
4044
4045 static const struct display_timing sharp_lq101k1ly04_timing = {
4046         .pixelclock = { 60000000, 65000000, 80000000 },
4047         .hactive = { 1280, 1280, 1280 },
4048         .hfront_porch = { 20, 20, 20 },
4049         .hback_porch = { 20, 20, 20 },
4050         .hsync_len = { 10, 10, 10 },
4051         .vactive = { 800, 800, 800 },
4052         .vfront_porch = { 4, 4, 4 },
4053         .vback_porch = { 4, 4, 4 },
4054         .vsync_len = { 4, 4, 4 },
4055         .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
4056 };
4057
4058 static const struct panel_desc sharp_lq101k1ly04 = {
4059         .timings = &sharp_lq101k1ly04_timing,
4060         .num_timings = 1,
4061         .bpc = 8,
4062         .size = {
4063                 .width = 217,
4064                 .height = 136,
4065         },
4066         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4067         .connector_type = DRM_MODE_CONNECTOR_LVDS,
4068 };
4069
4070 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
4071         { /* 50 Hz */
4072                 .clock = 3000,
4073                 .hdisplay = 240,
4074                 .hsync_start = 240 + 58,
4075                 .hsync_end = 240 + 58 + 1,
4076                 .htotal = 240 + 58 + 1 + 1,
4077                 .vdisplay = 160,
4078                 .vsync_start = 160 + 24,
4079                 .vsync_end = 160 + 24 + 10,
4080                 .vtotal = 160 + 24 + 10 + 6,
4081                 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
4082         },
4083         { /* 60 Hz */
4084                 .clock = 3000,
4085                 .hdisplay = 240,
4086                 .hsync_start = 240 + 8,
4087                 .hsync_end = 240 + 8 + 1,
4088                 .htotal = 240 + 8 + 1 + 1,
4089                 .vdisplay = 160,
4090                 .vsync_start = 160 + 24,
4091                 .vsync_end = 160 + 24 + 10,
4092                 .vtotal = 160 + 24 + 10 + 6,
4093                 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
4094         },
4095 };
4096
4097 static const struct panel_desc sharp_ls020b1dd01d = {
4098         .modes = sharp_ls020b1dd01d_modes,
4099         .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
4100         .bpc = 6,
4101         .size = {
4102                 .width = 42,
4103                 .height = 28,
4104         },
4105         .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
4106         .bus_flags = DRM_BUS_FLAG_DE_HIGH
4107                    | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
4108                    | DRM_BUS_FLAG_SHARP_SIGNALS,
4109 };
4110
4111 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
4112         .clock = 33300,
4113         .hdisplay = 800,
4114         .hsync_start = 800 + 1,
4115         .hsync_end = 800 + 1 + 64,
4116         .htotal = 800 + 1 + 64 + 64,
4117         .vdisplay = 480,
4118         .vsync_start = 480 + 1,
4119         .vsync_end = 480 + 1 + 23,
4120         .vtotal = 480 + 1 + 23 + 22,
4121 };
4122
4123 static const struct panel_desc shelly_sca07010_bfn_lnn = {
4124         .modes = &shelly_sca07010_bfn_lnn_mode,
4125         .num_modes = 1,
4126         .size = {
4127                 .width = 152,
4128                 .height = 91,
4129         },
4130         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4131 };
4132
4133 static const struct drm_display_mode starry_kr070pe2t_mode = {
4134         .clock = 33000,
4135         .hdisplay = 800,
4136         .hsync_start = 800 + 209,
4137         .hsync_end = 800 + 209 + 1,
4138         .htotal = 800 + 209 + 1 + 45,
4139         .vdisplay = 480,
4140         .vsync_start = 480 + 22,
4141         .vsync_end = 480 + 22 + 1,
4142         .vtotal = 480 + 22 + 1 + 22,
4143 };
4144
4145 static const struct panel_desc starry_kr070pe2t = {
4146         .modes = &starry_kr070pe2t_mode,
4147         .num_modes = 1,
4148         .bpc = 8,
4149         .size = {
4150                 .width = 152,
4151                 .height = 86,
4152         },
4153         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4154         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
4155         .connector_type = DRM_MODE_CONNECTOR_DPI,
4156 };
4157
4158 static const struct display_timing startek_kd070wvfpa_mode = {
4159         .pixelclock = { 25200000, 27200000, 30500000 },
4160         .hactive = { 800, 800, 800 },
4161         .hfront_porch = { 19, 44, 115 },
4162         .hback_porch = { 5, 16, 101 },
4163         .hsync_len = { 1, 2, 100 },
4164         .vactive = { 480, 480, 480 },
4165         .vfront_porch = { 5, 43, 67 },
4166         .vback_porch = { 5, 5, 67 },
4167         .vsync_len = { 1, 2, 66 },
4168         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4169                  DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
4170                  DISPLAY_FLAGS_SYNC_POSEDGE,
4171 };
4172
4173 static const struct panel_desc startek_kd070wvfpa = {
4174         .timings = &startek_kd070wvfpa_mode,
4175         .num_timings = 1,
4176         .bpc = 8,
4177         .size = {
4178                 .width = 152,
4179                 .height = 91,
4180         },
4181         .delay = {
4182                 .prepare = 20,
4183                 .enable = 200,
4184                 .disable = 200,
4185         },
4186         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4187         .connector_type = DRM_MODE_CONNECTOR_DPI,
4188         .bus_flags = DRM_BUS_FLAG_DE_HIGH |
4189                      DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
4190                      DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
4191 };
4192
4193 static const struct display_timing tsd_tst043015cmhx_timing = {
4194         .pixelclock = { 5000000, 9000000, 12000000 },
4195         .hactive = { 480, 480, 480 },
4196         .hfront_porch = { 4, 5, 65 },
4197         .hback_porch = { 36, 40, 255 },
4198         .hsync_len = { 1, 1, 1 },
4199         .vactive = { 272, 272, 272 },
4200         .vfront_porch = { 2, 8, 97 },
4201         .vback_porch = { 3, 8, 31 },
4202         .vsync_len = { 1, 1, 1 },
4203
4204         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4205                  DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
4206 };
4207
4208 static const struct panel_desc tsd_tst043015cmhx = {
4209         .timings = &tsd_tst043015cmhx_timing,
4210         .num_timings = 1,
4211         .bpc = 8,
4212         .size = {
4213                 .width = 105,
4214                 .height = 67,
4215         },
4216         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4217         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4218 };
4219
4220 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
4221         .clock = 30000,
4222         .hdisplay = 800,
4223         .hsync_start = 800 + 39,
4224         .hsync_end = 800 + 39 + 47,
4225         .htotal = 800 + 39 + 47 + 39,
4226         .vdisplay = 480,
4227         .vsync_start = 480 + 13,
4228         .vsync_end = 480 + 13 + 2,
4229         .vtotal = 480 + 13 + 2 + 29,
4230 };
4231
4232 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
4233         .modes = &tfc_s9700rtwv43tr_01b_mode,
4234         .num_modes = 1,
4235         .bpc = 8,
4236         .size = {
4237                 .width = 155,
4238                 .height = 90,
4239         },
4240         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4241         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4242 };
4243
4244 static const struct display_timing tianma_tm070jdhg30_timing = {
4245         .pixelclock = { 62600000, 68200000, 78100000 },
4246         .hactive = { 1280, 1280, 1280 },
4247         .hfront_porch = { 15, 64, 159 },
4248         .hback_porch = { 5, 5, 5 },
4249         .hsync_len = { 1, 1, 256 },
4250         .vactive = { 800, 800, 800 },
4251         .vfront_porch = { 3, 40, 99 },
4252         .vback_porch = { 2, 2, 2 },
4253         .vsync_len = { 1, 1, 128 },
4254         .flags = DISPLAY_FLAGS_DE_HIGH,
4255 };
4256
4257 static const struct panel_desc tianma_tm070jdhg30 = {
4258         .timings = &tianma_tm070jdhg30_timing,
4259         .num_timings = 1,
4260         .bpc = 8,
4261         .size = {
4262                 .width = 151,
4263                 .height = 95,
4264         },
4265         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4266         .connector_type = DRM_MODE_CONNECTOR_LVDS,
4267         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4268 };
4269
4270 static const struct panel_desc tianma_tm070jvhg33 = {
4271         .timings = &tianma_tm070jdhg30_timing,
4272         .num_timings = 1,
4273         .bpc = 8,
4274         .size = {
4275                 .width = 150,
4276                 .height = 94,
4277         },
4278         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4279         .connector_type = DRM_MODE_CONNECTOR_LVDS,
4280         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4281 };
4282
4283 static const struct display_timing tianma_tm070rvhg71_timing = {
4284         .pixelclock = { 27700000, 29200000, 39600000 },
4285         .hactive = { 800, 800, 800 },
4286         .hfront_porch = { 12, 40, 212 },
4287         .hback_porch = { 88, 88, 88 },
4288         .hsync_len = { 1, 1, 40 },
4289         .vactive = { 480, 480, 480 },
4290         .vfront_porch = { 1, 13, 88 },
4291         .vback_porch = { 32, 32, 32 },
4292         .vsync_len = { 1, 1, 3 },
4293         .flags = DISPLAY_FLAGS_DE_HIGH,
4294 };
4295
4296 static const struct panel_desc tianma_tm070rvhg71 = {
4297         .timings = &tianma_tm070rvhg71_timing,
4298         .num_timings = 1,
4299         .bpc = 8,
4300         .size = {
4301                 .width = 154,
4302                 .height = 86,
4303         },
4304         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4305         .connector_type = DRM_MODE_CONNECTOR_LVDS,
4306 };
4307
4308 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
4309         {
4310                 .clock = 10000,
4311                 .hdisplay = 320,
4312                 .hsync_start = 320 + 50,
4313                 .hsync_end = 320 + 50 + 6,
4314                 .htotal = 320 + 50 + 6 + 38,
4315                 .vdisplay = 240,
4316                 .vsync_start = 240 + 3,
4317                 .vsync_end = 240 + 3 + 1,
4318                 .vtotal = 240 + 3 + 1 + 17,
4319                 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4320         },
4321 };
4322
4323 static const struct panel_desc ti_nspire_cx_lcd_panel = {
4324         .modes = ti_nspire_cx_lcd_mode,
4325         .num_modes = 1,
4326         .bpc = 8,
4327         .size = {
4328                 .width = 65,
4329                 .height = 49,
4330         },
4331         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4332         .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
4333 };
4334
4335 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
4336         {
4337                 .clock = 10000,
4338                 .hdisplay = 320,
4339                 .hsync_start = 320 + 6,
4340                 .hsync_end = 320 + 6 + 6,
4341                 .htotal = 320 + 6 + 6 + 6,
4342                 .vdisplay = 240,
4343                 .vsync_start = 240 + 0,
4344                 .vsync_end = 240 + 0 + 1,
4345                 .vtotal = 240 + 0 + 1 + 0,
4346                 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4347         },
4348 };
4349
4350 static const struct panel_desc ti_nspire_classic_lcd_panel = {
4351         .modes = ti_nspire_classic_lcd_mode,
4352         .num_modes = 1,
4353         /* The grayscale panel has 8 bit for the color .. Y (black) */
4354         .bpc = 8,
4355         .size = {
4356                 .width = 71,
4357                 .height = 53,
4358         },
4359         /* This is the grayscale bus format */
4360         .bus_format = MEDIA_BUS_FMT_Y8_1X8,
4361         .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4362 };
4363
4364 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
4365         .clock = 79500,
4366         .hdisplay = 1280,
4367         .hsync_start = 1280 + 192,
4368         .hsync_end = 1280 + 192 + 128,
4369         .htotal = 1280 + 192 + 128 + 64,
4370         .vdisplay = 768,
4371         .vsync_start = 768 + 20,
4372         .vsync_end = 768 + 20 + 7,
4373         .vtotal = 768 + 20 + 7 + 3,
4374 };
4375
4376 static const struct panel_desc toshiba_lt089ac29000 = {
4377         .modes = &toshiba_lt089ac29000_mode,
4378         .num_modes = 1,
4379         .size = {
4380                 .width = 194,
4381                 .height = 116,
4382         },
4383         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4384         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4385         .connector_type = DRM_MODE_CONNECTOR_LVDS,
4386 };
4387
4388 static const struct drm_display_mode tpk_f07a_0102_mode = {
4389         .clock = 33260,
4390         .hdisplay = 800,
4391         .hsync_start = 800 + 40,
4392         .hsync_end = 800 + 40 + 128,
4393         .htotal = 800 + 40 + 128 + 88,
4394         .vdisplay = 480,
4395         .vsync_start = 480 + 10,
4396         .vsync_end = 480 + 10 + 2,
4397         .vtotal = 480 + 10 + 2 + 33,
4398 };
4399
4400 static const struct panel_desc tpk_f07a_0102 = {
4401         .modes = &tpk_f07a_0102_mode,
4402         .num_modes = 1,
4403         .size = {
4404                 .width = 152,
4405                 .height = 91,
4406         },
4407         .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
4408 };
4409
4410 static const struct drm_display_mode tpk_f10a_0102_mode = {
4411         .clock = 45000,
4412         .hdisplay = 1024,
4413         .hsync_start = 1024 + 176,
4414         .hsync_end = 1024 + 176 + 5,
4415         .htotal = 1024 + 176 + 5 + 88,
4416         .vdisplay = 600,
4417         .vsync_start = 600 + 20,
4418         .vsync_end = 600 + 20 + 5,
4419         .vtotal = 600 + 20 + 5 + 25,
4420 };
4421
4422 static const struct panel_desc tpk_f10a_0102 = {
4423         .modes = &tpk_f10a_0102_mode,
4424         .num_modes = 1,
4425         .size = {
4426                 .width = 223,
4427                 .height = 125,
4428         },
4429 };
4430
4431 static const struct display_timing urt_umsh_8596md_timing = {
4432         .pixelclock = { 33260000, 33260000, 33260000 },
4433         .hactive = { 800, 800, 800 },
4434         .hfront_porch = { 41, 41, 41 },
4435         .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
4436         .hsync_len = { 71, 128, 128 },
4437         .vactive = { 480, 480, 480 },
4438         .vfront_porch = { 10, 10, 10 },
4439         .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
4440         .vsync_len = { 2, 2, 2 },
4441         .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
4442                 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4443 };
4444
4445 static const struct panel_desc urt_umsh_8596md_lvds = {
4446         .timings = &urt_umsh_8596md_timing,
4447         .num_timings = 1,
4448         .bpc = 6,
4449         .size = {
4450                 .width = 152,
4451                 .height = 91,
4452         },
4453         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4454         .connector_type = DRM_MODE_CONNECTOR_LVDS,
4455 };
4456
4457 static const struct panel_desc urt_umsh_8596md_parallel = {
4458         .timings = &urt_umsh_8596md_timing,
4459         .num_timings = 1,
4460         .bpc = 6,
4461         .size = {
4462                 .width = 152,
4463                 .height = 91,
4464         },
4465         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4466 };
4467
4468 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
4469         .clock = 60000,
4470         .hdisplay = 1024,
4471         .hsync_start = 1024 + 160,
4472         .hsync_end = 1024 + 160 + 100,
4473         .htotal = 1024 + 160 + 100 + 60,
4474         .vdisplay = 600,
4475         .vsync_start = 600 + 12,
4476         .vsync_end = 600 + 12 + 10,
4477         .vtotal = 600 + 12 + 10 + 13,
4478 };
4479
4480 static const struct panel_desc vivax_tpc9150_panel = {
4481         .modes = &vivax_tpc9150_panel_mode,
4482         .num_modes = 1,
4483         .bpc = 6,
4484         .size = {
4485                 .width = 200,
4486                 .height = 115,
4487         },
4488         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4489         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4490         .connector_type = DRM_MODE_CONNECTOR_LVDS,
4491 };
4492
4493 static const struct drm_display_mode vl050_8048nt_c01_mode = {
4494         .clock = 33333,
4495         .hdisplay = 800,
4496         .hsync_start = 800 + 210,
4497         .hsync_end = 800 + 210 + 20,
4498         .htotal = 800 + 210 + 20 + 46,
4499         .vdisplay =  480,
4500         .vsync_start = 480 + 22,
4501         .vsync_end = 480 + 22 + 10,
4502         .vtotal = 480 + 22 + 10 + 23,
4503         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4504 };
4505
4506 static const struct panel_desc vl050_8048nt_c01 = {
4507         .modes = &vl050_8048nt_c01_mode,
4508         .num_modes = 1,
4509         .bpc = 8,
4510         .size = {
4511                 .width = 120,
4512                 .height = 76,
4513         },
4514         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4515         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4516 };
4517
4518 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4519         .clock = 6410,
4520         .hdisplay = 320,
4521         .hsync_start = 320 + 20,
4522         .hsync_end = 320 + 20 + 30,
4523         .htotal = 320 + 20 + 30 + 38,
4524         .vdisplay = 240,
4525         .vsync_start = 240 + 4,
4526         .vsync_end = 240 + 4 + 3,
4527         .vtotal = 240 + 4 + 3 + 15,
4528         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4529 };
4530
4531 static const struct panel_desc winstar_wf35ltiacd = {
4532         .modes = &winstar_wf35ltiacd_mode,
4533         .num_modes = 1,
4534         .bpc = 8,
4535         .size = {
4536                 .width = 70,
4537                 .height = 53,
4538         },
4539         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4540 };
4541
4542 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4543         .clock = 51200,
4544         .hdisplay = 1024,
4545         .hsync_start = 1024 + 100,
4546         .hsync_end = 1024 + 100 + 100,
4547         .htotal = 1024 + 100 + 100 + 120,
4548         .vdisplay = 600,
4549         .vsync_start = 600 + 10,
4550         .vsync_end = 600 + 10 + 10,
4551         .vtotal = 600 + 10 + 10 + 15,
4552         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4553 };
4554
4555 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4556         .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4557         .num_modes = 1,
4558         .bpc = 8,
4559         .size = {
4560                 .width = 154,
4561                 .height = 90,
4562         },
4563         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4564         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4565         .connector_type = DRM_MODE_CONNECTOR_LVDS,
4566 };
4567
4568 static const struct drm_display_mode mchp_ac69t88a_mode = {
4569         .clock = 25000,
4570         .hdisplay = 800,
4571         .hsync_start = 800 + 88,
4572         .hsync_end = 800 + 88 + 5,
4573         .htotal = 800 + 88 + 5 + 40,
4574         .vdisplay = 480,
4575         .vsync_start = 480 + 23,
4576         .vsync_end = 480 + 23 + 5,
4577         .vtotal = 480 + 23 + 5 + 1,
4578 };
4579
4580 static const struct panel_desc mchp_ac69t88a = {
4581         .modes = &mchp_ac69t88a_mode,
4582         .num_modes = 1,
4583         .bpc = 8,
4584         .size = {
4585                 .width = 108,
4586                 .height = 65,
4587         },
4588         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4589         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4590         .connector_type = DRM_MODE_CONNECTOR_LVDS,
4591 };
4592
4593 static const struct drm_display_mode arm_rtsm_mode[] = {
4594         {
4595                 .clock = 65000,
4596                 .hdisplay = 1024,
4597                 .hsync_start = 1024 + 24,
4598                 .hsync_end = 1024 + 24 + 136,
4599                 .htotal = 1024 + 24 + 136 + 160,
4600                 .vdisplay = 768,
4601                 .vsync_start = 768 + 3,
4602                 .vsync_end = 768 + 3 + 6,
4603                 .vtotal = 768 + 3 + 6 + 29,
4604                 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4605         },
4606 };
4607
4608 static const struct panel_desc arm_rtsm = {
4609         .modes = arm_rtsm_mode,
4610         .num_modes = 1,
4611         .bpc = 8,
4612         .size = {
4613                 .width = 400,
4614                 .height = 300,
4615         },
4616         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4617 };
4618
4619 static const struct of_device_id platform_of_match[] = {
4620         {
4621                 .compatible = "ampire,am-1280800n3tzqw-t00h",
4622                 .data = &ampire_am_1280800n3tzqw_t00h,
4623         }, {
4624                 .compatible = "ampire,am-480272h3tmqw-t01h",
4625                 .data = &ampire_am_480272h3tmqw_t01h,
4626         }, {
4627                 .compatible = "ampire,am-800480l1tmqw-t00h",
4628                 .data = &ampire_am_800480l1tmqw_t00h,
4629         }, {
4630                 .compatible = "ampire,am800480r3tmqwa1h",
4631                 .data = &ampire_am800480r3tmqwa1h,
4632         }, {
4633                 .compatible = "ampire,am800600p5tmqw-tb8h",
4634                 .data = &ampire_am800600p5tmqwtb8h,
4635         }, {
4636                 .compatible = "arm,rtsm-display",
4637                 .data = &arm_rtsm,
4638         }, {
4639                 .compatible = "armadeus,st0700-adapt",
4640                 .data = &armadeus_st0700_adapt,
4641         }, {
4642                 .compatible = "auo,b101aw03",
4643                 .data = &auo_b101aw03,
4644         }, {
4645                 .compatible = "auo,b101xtn01",
4646                 .data = &auo_b101xtn01,
4647         }, {
4648                 .compatible = "auo,b116xw03",
4649                 .data = &auo_b116xw03,
4650         }, {
4651                 .compatible = "auo,g070vvn01",
4652                 .data = &auo_g070vvn01,
4653         }, {
4654                 .compatible = "auo,g101evn010",
4655                 .data = &auo_g101evn010,
4656         }, {
4657                 .compatible = "auo,g104sn02",
4658                 .data = &auo_g104sn02,
4659         }, {
4660                 .compatible = "auo,g104stn01",
4661                 .data = &auo_g104stn01,
4662         }, {
4663                 .compatible = "auo,g121ean01",
4664                 .data = &auo_g121ean01,
4665         }, {
4666                 .compatible = "auo,g133han01",
4667                 .data = &auo_g133han01,
4668         }, {
4669                 .compatible = "auo,g156han04",
4670                 .data = &auo_g156han04,
4671         }, {
4672                 .compatible = "auo,g156xtn01",
4673                 .data = &auo_g156xtn01,
4674         }, {
4675                 .compatible = "auo,g185han01",
4676                 .data = &auo_g185han01,
4677         }, {
4678                 .compatible = "auo,g190ean01",
4679                 .data = &auo_g190ean01,
4680         }, {
4681                 .compatible = "auo,p320hvn03",
4682                 .data = &auo_p320hvn03,
4683         }, {
4684                 .compatible = "auo,t215hvn01",
4685                 .data = &auo_t215hvn01,
4686         }, {
4687                 .compatible = "avic,tm070ddh03",
4688                 .data = &avic_tm070ddh03,
4689         }, {
4690                 .compatible = "bananapi,s070wv20-ct16",
4691                 .data = &bananapi_s070wv20_ct16,
4692         }, {
4693                 .compatible = "boe,bp082wx1-100",
4694                 .data = &boe_bp082wx1_100,
4695         }, {
4696                 .compatible = "boe,bp101wx1-100",
4697                 .data = &boe_bp101wx1_100,
4698         }, {
4699                 .compatible = "boe,ev121wxm-n10-1850",
4700                 .data = &boe_ev121wxm_n10_1850,
4701         }, {
4702                 .compatible = "boe,hv070wsa-100",
4703                 .data = &boe_hv070wsa
4704         }, {
4705                 .compatible = "cct,cmt430b19n00",
4706                 .data = &cct_cmt430b19n00,
4707         }, {
4708                 .compatible = "cdtech,s043wq26h-ct7",
4709                 .data = &cdtech_s043wq26h_ct7,
4710         }, {
4711                 .compatible = "cdtech,s070pws19hp-fc21",
4712                 .data = &cdtech_s070pws19hp_fc21,
4713         }, {
4714                 .compatible = "cdtech,s070swv29hg-dc44",
4715                 .data = &cdtech_s070swv29hg_dc44,
4716         }, {
4717                 .compatible = "cdtech,s070wv95-ct16",
4718                 .data = &cdtech_s070wv95_ct16,
4719         }, {
4720                 .compatible = "chefree,ch101olhlwh-002",
4721                 .data = &chefree_ch101olhlwh_002,
4722         }, {
4723                 .compatible = "chunghwa,claa070wp03xg",
4724                 .data = &chunghwa_claa070wp03xg,
4725         }, {
4726                 .compatible = "chunghwa,claa101wa01a",
4727                 .data = &chunghwa_claa101wa01a
4728         }, {
4729                 .compatible = "chunghwa,claa101wb01",
4730                 .data = &chunghwa_claa101wb01
4731         }, {
4732                 .compatible = "dataimage,fg040346dsswbg04",
4733                 .data = &dataimage_fg040346dsswbg04,
4734         }, {
4735                 .compatible = "dataimage,fg1001l0dsswmg01",
4736                 .data = &dataimage_fg1001l0dsswmg01,
4737         }, {
4738                 .compatible = "dataimage,scf0700c48ggu18",
4739                 .data = &dataimage_scf0700c48ggu18,
4740         }, {
4741                 .compatible = "dlc,dlc0700yzg-1",
4742                 .data = &dlc_dlc0700yzg_1,
4743         }, {
4744                 .compatible = "dlc,dlc1010gig",
4745                 .data = &dlc_dlc1010gig,
4746         }, {
4747                 .compatible = "edt,et035012dm6",
4748                 .data = &edt_et035012dm6,
4749         }, {
4750                 .compatible = "edt,etm0350g0dh6",
4751                 .data = &edt_etm0350g0dh6,
4752         }, {
4753                 .compatible = "edt,etm043080dh6gp",
4754                 .data = &edt_etm043080dh6gp,
4755         }, {
4756                 .compatible = "edt,etm0430g0dh6",
4757                 .data = &edt_etm0430g0dh6,
4758         }, {
4759                 .compatible = "edt,et057090dhu",
4760                 .data = &edt_et057090dhu,
4761         }, {
4762                 .compatible = "edt,et070080dh6",
4763                 .data = &edt_etm0700g0dh6,
4764         }, {
4765                 .compatible = "edt,etm0700g0dh6",
4766                 .data = &edt_etm0700g0dh6,
4767         }, {
4768                 .compatible = "edt,etm0700g0bdh6",
4769                 .data = &edt_etm0700g0bdh6,
4770         }, {
4771                 .compatible = "edt,etm0700g0edh6",
4772                 .data = &edt_etm0700g0bdh6,
4773         }, {
4774                 .compatible = "edt,etml0700y5dha",
4775                 .data = &edt_etml0700y5dha,
4776         }, {
4777                 .compatible = "edt,etml1010g3dra",
4778                 .data = &edt_etml1010g3dra,
4779         }, {
4780                 .compatible = "edt,etmv570g2dhu",
4781                 .data = &edt_etmv570g2dhu,
4782         }, {
4783                 .compatible = "eink,vb3300-kca",
4784                 .data = &eink_vb3300_kca,
4785         }, {
4786                 .compatible = "evervision,vgg644804",
4787                 .data = &evervision_vgg644804,
4788         }, {
4789                 .compatible = "evervision,vgg804821",
4790                 .data = &evervision_vgg804821,
4791         }, {
4792                 .compatible = "foxlink,fl500wvr00-a0t",
4793                 .data = &foxlink_fl500wvr00_a0t,
4794         }, {
4795                 .compatible = "frida,frd350h54004",
4796                 .data = &frida_frd350h54004,
4797         }, {
4798                 .compatible = "friendlyarm,hd702e",
4799                 .data = &friendlyarm_hd702e,
4800         }, {
4801                 .compatible = "giantplus,gpg482739qs5",
4802                 .data = &giantplus_gpg482739qs5
4803         }, {
4804                 .compatible = "giantplus,gpm940b0",
4805                 .data = &giantplus_gpm940b0,
4806         }, {
4807                 .compatible = "hannstar,hsd070pww1",
4808                 .data = &hannstar_hsd070pww1,
4809         }, {
4810                 .compatible = "hannstar,hsd100pxn1",
4811                 .data = &hannstar_hsd100pxn1,
4812         }, {
4813                 .compatible = "hannstar,hsd101pww2",
4814                 .data = &hannstar_hsd101pww2,
4815         }, {
4816                 .compatible = "hit,tx23d38vm0caa",
4817                 .data = &hitachi_tx23d38vm0caa
4818         }, {
4819                 .compatible = "innolux,at043tn24",
4820                 .data = &innolux_at043tn24,
4821         }, {
4822                 .compatible = "innolux,at070tn92",
4823                 .data = &innolux_at070tn92,
4824         }, {
4825                 .compatible = "innolux,g070ace-l01",
4826                 .data = &innolux_g070ace_l01,
4827         }, {
4828                 .compatible = "innolux,g070ace-lh3",
4829                 .data = &innolux_g070ace_lh3,
4830         }, {
4831                 .compatible = "innolux,g070y2-l01",
4832                 .data = &innolux_g070y2_l01,
4833         }, {
4834                 .compatible = "innolux,g070y2-t02",
4835                 .data = &innolux_g070y2_t02,
4836         }, {
4837                 .compatible = "innolux,g101ice-l01",
4838                 .data = &innolux_g101ice_l01
4839         }, {
4840                 .compatible = "innolux,g121i1-l01",
4841                 .data = &innolux_g121i1_l01
4842         }, {
4843                 .compatible = "innolux,g121x1-l03",
4844                 .data = &innolux_g121x1_l03,
4845         }, {
4846                 .compatible = "innolux,g121xce-l01",
4847                 .data = &innolux_g121xce_l01,
4848         }, {
4849                 .compatible = "innolux,g156hce-l01",
4850                 .data = &innolux_g156hce_l01,
4851         }, {
4852                 .compatible = "innolux,n156bge-l21",
4853                 .data = &innolux_n156bge_l21,
4854         }, {
4855                 .compatible = "innolux,zj070na-01p",
4856                 .data = &innolux_zj070na_01p,
4857         }, {
4858                 .compatible = "koe,tx14d24vm1bpa",
4859                 .data = &koe_tx14d24vm1bpa,
4860         }, {
4861                 .compatible = "koe,tx26d202vm0bwa",
4862                 .data = &koe_tx26d202vm0bwa,
4863         }, {
4864                 .compatible = "koe,tx31d200vm0baa",
4865                 .data = &koe_tx31d200vm0baa,
4866         }, {
4867                 .compatible = "kyo,tcg121xglp",
4868                 .data = &kyo_tcg121xglp,
4869         }, {
4870                 .compatible = "lemaker,bl035-rgb-002",
4871                 .data = &lemaker_bl035_rgb_002,
4872         }, {
4873                 .compatible = "lg,lb070wv8",
4874                 .data = &lg_lb070wv8,
4875         }, {
4876                 .compatible = "lincolntech,lcd185-101ct",
4877                 .data = &lincolntech_lcd185_101ct,
4878         }, {
4879                 .compatible = "logicpd,type28",
4880                 .data = &logicpd_type_28,
4881         }, {
4882                 .compatible = "logictechno,lt161010-2nhc",
4883                 .data = &logictechno_lt161010_2nh,
4884         }, {
4885                 .compatible = "logictechno,lt161010-2nhr",
4886                 .data = &logictechno_lt161010_2nh,
4887         }, {
4888                 .compatible = "logictechno,lt170410-2whc",
4889                 .data = &logictechno_lt170410_2whc,
4890         }, {
4891                 .compatible = "logictechno,lttd800480070-l2rt",
4892                 .data = &logictechno_lttd800480070_l2rt,
4893         }, {
4894                 .compatible = "logictechno,lttd800480070-l6wh-rt",
4895                 .data = &logictechno_lttd800480070_l6wh_rt,
4896         }, {
4897                 .compatible = "microtips,mf-101hiebcaf0",
4898                 .data = &microtips_mf_101hiebcaf0_c,
4899         }, {
4900                 .compatible = "microtips,mf-103hieb0ga0",
4901                 .data = &microtips_mf_103hieb0ga0,
4902         }, {
4903                 .compatible = "mitsubishi,aa070mc01-ca1",
4904                 .data = &mitsubishi_aa070mc01,
4905         }, {
4906                 .compatible = "mitsubishi,aa084xe01",
4907                 .data = &mitsubishi_aa084xe01,
4908         }, {
4909                 .compatible = "multi-inno,mi0700s4t-6",
4910                 .data = &multi_inno_mi0700s4t_6,
4911         }, {
4912                 .compatible = "multi-inno,mi0800ft-9",
4913                 .data = &multi_inno_mi0800ft_9,
4914         }, {
4915                 .compatible = "multi-inno,mi1010ait-1cp",
4916                 .data = &multi_inno_mi1010ait_1cp,
4917         }, {
4918                 .compatible = "nec,nl12880bc20-05",
4919                 .data = &nec_nl12880bc20_05,
4920         }, {
4921                 .compatible = "nec,nl4827hc19-05b",
4922                 .data = &nec_nl4827hc19_05b,
4923         }, {
4924                 .compatible = "netron-dy,e231732",
4925                 .data = &netron_dy_e231732,
4926         }, {
4927                 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4928                 .data = &newhaven_nhd_43_480272ef_atxl,
4929         }, {
4930                 .compatible = "nlt,nl192108ac18-02d",
4931                 .data = &nlt_nl192108ac18_02d,
4932         }, {
4933                 .compatible = "nvd,9128",
4934                 .data = &nvd_9128,
4935         }, {
4936                 .compatible = "okaya,rs800480t-7x0gp",
4937                 .data = &okaya_rs800480t_7x0gp,
4938         }, {
4939                 .compatible = "olimex,lcd-olinuxino-43-ts",
4940                 .data = &olimex_lcd_olinuxino_43ts,
4941         }, {
4942                 .compatible = "ontat,kd50g21-40nt-a1",
4943                 .data = &ontat_kd50g21_40nt_a1,
4944         }, {
4945                 .compatible = "ontat,yx700wv03",
4946                 .data = &ontat_yx700wv03,
4947         }, {
4948                 .compatible = "ortustech,com37h3m05dtc",
4949                 .data = &ortustech_com37h3m,
4950         }, {
4951                 .compatible = "ortustech,com37h3m99dtc",
4952                 .data = &ortustech_com37h3m,
4953         }, {
4954                 .compatible = "ortustech,com43h4m85ulc",
4955                 .data = &ortustech_com43h4m85ulc,
4956         }, {
4957                 .compatible = "osddisplays,osd070t1718-19ts",
4958                 .data = &osddisplays_osd070t1718_19ts,
4959         }, {
4960                 .compatible = "pda,91-00156-a0",
4961                 .data = &pda_91_00156_a0,
4962         }, {
4963                 .compatible = "powertip,ph128800t006-zhc01",
4964                 .data = &powertip_ph128800t006_zhc01,
4965         }, {
4966                 .compatible = "powertip,ph800480t013-idf02",
4967                 .data = &powertip_ph800480t013_idf02,
4968         }, {
4969                 .compatible = "primeview,pm070wl4",
4970                 .data = &primeview_pm070wl4,
4971         }, {
4972                 .compatible = "qiaodian,qd43003c0-40",
4973                 .data = &qd43003c0_40,
4974         }, {
4975                 .compatible = "qishenglong,gopher2b-lcd",
4976                 .data = &qishenglong_gopher2b_lcd,
4977         }, {
4978                 .compatible = "rocktech,rk043fn48h",
4979                 .data = &rocktech_rk043fn48h,
4980         }, {
4981                 .compatible = "rocktech,rk070er9427",
4982                 .data = &rocktech_rk070er9427,
4983         }, {
4984                 .compatible = "rocktech,rk101ii01d-ct",
4985                 .data = &rocktech_rk101ii01d_ct,
4986         }, {
4987                 .compatible = "samsung,ltl101al01",
4988                 .data = &samsung_ltl101al01,
4989         }, {
4990                 .compatible = "samsung,ltn101nt05",
4991                 .data = &samsung_ltn101nt05,
4992         }, {
4993                 .compatible = "satoz,sat050at40h12r2",
4994                 .data = &satoz_sat050at40h12r2,
4995         }, {
4996                 .compatible = "sharp,lq035q7db03",
4997                 .data = &sharp_lq035q7db03,
4998         }, {
4999                 .compatible = "sharp,lq070y3dg3b",
5000                 .data = &sharp_lq070y3dg3b,
5001         }, {
5002                 .compatible = "sharp,lq101k1ly04",
5003                 .data = &sharp_lq101k1ly04,
5004         }, {
5005                 .compatible = "sharp,ls020b1dd01d",
5006                 .data = &sharp_ls020b1dd01d,
5007         }, {
5008                 .compatible = "shelly,sca07010-bfn-lnn",
5009                 .data = &shelly_sca07010_bfn_lnn,
5010         }, {
5011                 .compatible = "starry,kr070pe2t",
5012                 .data = &starry_kr070pe2t,
5013         }, {
5014                 .compatible = "startek,kd070wvfpa",
5015                 .data = &startek_kd070wvfpa,
5016         }, {
5017                 .compatible = "team-source-display,tst043015cmhx",
5018                 .data = &tsd_tst043015cmhx,
5019         }, {
5020                 .compatible = "tfc,s9700rtwv43tr-01b",
5021                 .data = &tfc_s9700rtwv43tr_01b,
5022         }, {
5023                 .compatible = "tianma,tm070jdhg30",
5024                 .data = &tianma_tm070jdhg30,
5025         }, {
5026                 .compatible = "tianma,tm070jvhg33",
5027                 .data = &tianma_tm070jvhg33,
5028         }, {
5029                 .compatible = "tianma,tm070rvhg71",
5030                 .data = &tianma_tm070rvhg71,
5031         }, {
5032                 .compatible = "ti,nspire-cx-lcd-panel",
5033                 .data = &ti_nspire_cx_lcd_panel,
5034         }, {
5035                 .compatible = "ti,nspire-classic-lcd-panel",
5036                 .data = &ti_nspire_classic_lcd_panel,
5037         }, {
5038                 .compatible = "toshiba,lt089ac29000",
5039                 .data = &toshiba_lt089ac29000,
5040         }, {
5041                 .compatible = "tpk,f07a-0102",
5042                 .data = &tpk_f07a_0102,
5043         }, {
5044                 .compatible = "tpk,f10a-0102",
5045                 .data = &tpk_f10a_0102,
5046         }, {
5047                 .compatible = "urt,umsh-8596md-t",
5048                 .data = &urt_umsh_8596md_parallel,
5049         }, {
5050                 .compatible = "urt,umsh-8596md-1t",
5051                 .data = &urt_umsh_8596md_parallel,
5052         }, {
5053                 .compatible = "urt,umsh-8596md-7t",
5054                 .data = &urt_umsh_8596md_parallel,
5055         }, {
5056                 .compatible = "urt,umsh-8596md-11t",
5057                 .data = &urt_umsh_8596md_lvds,
5058         }, {
5059                 .compatible = "urt,umsh-8596md-19t",
5060                 .data = &urt_umsh_8596md_lvds,
5061         }, {
5062                 .compatible = "urt,umsh-8596md-20t",
5063                 .data = &urt_umsh_8596md_parallel,
5064         }, {
5065                 .compatible = "vivax,tpc9150-panel",
5066                 .data = &vivax_tpc9150_panel,
5067         }, {
5068                 .compatible = "vxt,vl050-8048nt-c01",
5069                 .data = &vl050_8048nt_c01,
5070         }, {
5071                 .compatible = "winstar,wf35ltiacd",
5072                 .data = &winstar_wf35ltiacd,
5073         }, {
5074                 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
5075                 .data = &yes_optoelectronics_ytc700tlag_05_201c,
5076         }, {
5077                 .compatible = "microchip,ac69t88a",
5078                 .data = &mchp_ac69t88a,
5079         }, {
5080                 /* Must be the last entry */
5081                 .compatible = "panel-dpi",
5082                 .data = &panel_dpi,
5083         }, {
5084                 /* sentinel */
5085         }
5086 };
5087 MODULE_DEVICE_TABLE(of, platform_of_match);
5088
5089 static int panel_simple_platform_probe(struct platform_device *pdev)
5090 {
5091         const struct panel_desc *desc;
5092
5093         desc = of_device_get_match_data(&pdev->dev);
5094         if (!desc)
5095                 return -ENODEV;
5096
5097         return panel_simple_probe(&pdev->dev, desc);
5098 }
5099
5100 static void panel_simple_platform_remove(struct platform_device *pdev)
5101 {
5102         panel_simple_remove(&pdev->dev);
5103 }
5104
5105 static void panel_simple_platform_shutdown(struct platform_device *pdev)
5106 {
5107         panel_simple_shutdown(&pdev->dev);
5108 }
5109
5110 static const struct dev_pm_ops panel_simple_pm_ops = {
5111         SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
5112         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5113                                 pm_runtime_force_resume)
5114 };
5115
5116 static struct platform_driver panel_simple_platform_driver = {
5117         .driver = {
5118                 .name = "panel-simple",
5119                 .of_match_table = platform_of_match,
5120                 .pm = &panel_simple_pm_ops,
5121         },
5122         .probe = panel_simple_platform_probe,
5123         .remove = panel_simple_platform_remove,
5124         .shutdown = panel_simple_platform_shutdown,
5125 };
5126
5127 struct panel_desc_dsi {
5128         struct panel_desc desc;
5129
5130         unsigned long flags;
5131         enum mipi_dsi_pixel_format format;
5132         unsigned int lanes;
5133 };
5134
5135 static const struct drm_display_mode auo_b080uan01_mode = {
5136         .clock = 154500,
5137         .hdisplay = 1200,
5138         .hsync_start = 1200 + 62,
5139         .hsync_end = 1200 + 62 + 4,
5140         .htotal = 1200 + 62 + 4 + 62,
5141         .vdisplay = 1920,
5142         .vsync_start = 1920 + 9,
5143         .vsync_end = 1920 + 9 + 2,
5144         .vtotal = 1920 + 9 + 2 + 8,
5145 };
5146
5147 static const struct panel_desc_dsi auo_b080uan01 = {
5148         .desc = {
5149                 .modes = &auo_b080uan01_mode,
5150                 .num_modes = 1,
5151                 .bpc = 8,
5152                 .size = {
5153                         .width = 108,
5154                         .height = 272,
5155                 },
5156                 .connector_type = DRM_MODE_CONNECTOR_DSI,
5157         },
5158         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
5159         .format = MIPI_DSI_FMT_RGB888,
5160         .lanes = 4,
5161 };
5162
5163 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
5164         .clock = 160000,
5165         .hdisplay = 1200,
5166         .hsync_start = 1200 + 120,
5167         .hsync_end = 1200 + 120 + 20,
5168         .htotal = 1200 + 120 + 20 + 21,
5169         .vdisplay = 1920,
5170         .vsync_start = 1920 + 21,
5171         .vsync_end = 1920 + 21 + 3,
5172         .vtotal = 1920 + 21 + 3 + 18,
5173         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
5174 };
5175
5176 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
5177         .desc = {
5178                 .modes = &boe_tv080wum_nl0_mode,
5179                 .num_modes = 1,
5180                 .size = {
5181                         .width = 107,
5182                         .height = 172,
5183                 },
5184                 .connector_type = DRM_MODE_CONNECTOR_DSI,
5185         },
5186         .flags = MIPI_DSI_MODE_VIDEO |
5187                  MIPI_DSI_MODE_VIDEO_BURST |
5188                  MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
5189         .format = MIPI_DSI_FMT_RGB888,
5190         .lanes = 4,
5191 };
5192
5193 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
5194         .clock = 71000,
5195         .hdisplay = 800,
5196         .hsync_start = 800 + 32,
5197         .hsync_end = 800 + 32 + 1,
5198         .htotal = 800 + 32 + 1 + 57,
5199         .vdisplay = 1280,
5200         .vsync_start = 1280 + 28,
5201         .vsync_end = 1280 + 28 + 1,
5202         .vtotal = 1280 + 28 + 1 + 14,
5203 };
5204
5205 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
5206         .desc = {
5207                 .modes = &lg_ld070wx3_sl01_mode,
5208                 .num_modes = 1,
5209                 .bpc = 8,
5210                 .size = {
5211                         .width = 94,
5212                         .height = 151,
5213                 },
5214                 .connector_type = DRM_MODE_CONNECTOR_DSI,
5215         },
5216         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
5217         .format = MIPI_DSI_FMT_RGB888,
5218         .lanes = 4,
5219 };
5220
5221 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
5222         .clock = 67000,
5223         .hdisplay = 720,
5224         .hsync_start = 720 + 12,
5225         .hsync_end = 720 + 12 + 4,
5226         .htotal = 720 + 12 + 4 + 112,
5227         .vdisplay = 1280,
5228         .vsync_start = 1280 + 8,
5229         .vsync_end = 1280 + 8 + 4,
5230         .vtotal = 1280 + 8 + 4 + 12,
5231 };
5232
5233 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
5234         .desc = {
5235                 .modes = &lg_lh500wx1_sd03_mode,
5236                 .num_modes = 1,
5237                 .bpc = 8,
5238                 .size = {
5239                         .width = 62,
5240                         .height = 110,
5241                 },
5242                 .connector_type = DRM_MODE_CONNECTOR_DSI,
5243         },
5244         .flags = MIPI_DSI_MODE_VIDEO,
5245         .format = MIPI_DSI_FMT_RGB888,
5246         .lanes = 4,
5247 };
5248
5249 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
5250         .clock = 157200,
5251         .hdisplay = 1920,
5252         .hsync_start = 1920 + 154,
5253         .hsync_end = 1920 + 154 + 16,
5254         .htotal = 1920 + 154 + 16 + 32,
5255         .vdisplay = 1200,
5256         .vsync_start = 1200 + 17,
5257         .vsync_end = 1200 + 17 + 2,
5258         .vtotal = 1200 + 17 + 2 + 16,
5259 };
5260
5261 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
5262         .desc = {
5263                 .modes = &panasonic_vvx10f004b00_mode,
5264                 .num_modes = 1,
5265                 .bpc = 8,
5266                 .size = {
5267                         .width = 217,
5268                         .height = 136,
5269                 },
5270                 .connector_type = DRM_MODE_CONNECTOR_DSI,
5271         },
5272         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5273                  MIPI_DSI_CLOCK_NON_CONTINUOUS,
5274         .format = MIPI_DSI_FMT_RGB888,
5275         .lanes = 4,
5276 };
5277
5278 static const struct drm_display_mode lg_acx467akm_7_mode = {
5279         .clock = 150000,
5280         .hdisplay = 1080,
5281         .hsync_start = 1080 + 2,
5282         .hsync_end = 1080 + 2 + 2,
5283         .htotal = 1080 + 2 + 2 + 2,
5284         .vdisplay = 1920,
5285         .vsync_start = 1920 + 2,
5286         .vsync_end = 1920 + 2 + 2,
5287         .vtotal = 1920 + 2 + 2 + 2,
5288 };
5289
5290 static const struct panel_desc_dsi lg_acx467akm_7 = {
5291         .desc = {
5292                 .modes = &lg_acx467akm_7_mode,
5293                 .num_modes = 1,
5294                 .bpc = 8,
5295                 .size = {
5296                         .width = 62,
5297                         .height = 110,
5298                 },
5299                 .connector_type = DRM_MODE_CONNECTOR_DSI,
5300         },
5301         .flags = 0,
5302         .format = MIPI_DSI_FMT_RGB888,
5303         .lanes = 4,
5304 };
5305
5306 static const struct drm_display_mode osd101t2045_53ts_mode = {
5307         .clock = 154500,
5308         .hdisplay = 1920,
5309         .hsync_start = 1920 + 112,
5310         .hsync_end = 1920 + 112 + 16,
5311         .htotal = 1920 + 112 + 16 + 32,
5312         .vdisplay = 1200,
5313         .vsync_start = 1200 + 16,
5314         .vsync_end = 1200 + 16 + 2,
5315         .vtotal = 1200 + 16 + 2 + 16,
5316         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
5317 };
5318
5319 static const struct panel_desc_dsi osd101t2045_53ts = {
5320         .desc = {
5321                 .modes = &osd101t2045_53ts_mode,
5322                 .num_modes = 1,
5323                 .bpc = 8,
5324                 .size = {
5325                         .width = 217,
5326                         .height = 136,
5327                 },
5328                 .connector_type = DRM_MODE_CONNECTOR_DSI,
5329         },
5330         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
5331                  MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5332                  MIPI_DSI_MODE_NO_EOT_PACKET,
5333         .format = MIPI_DSI_FMT_RGB888,
5334         .lanes = 4,
5335 };
5336
5337 static const struct of_device_id dsi_of_match[] = {
5338         {
5339                 .compatible = "auo,b080uan01",
5340                 .data = &auo_b080uan01
5341         }, {
5342                 .compatible = "boe,tv080wum-nl0",
5343                 .data = &boe_tv080wum_nl0
5344         }, {
5345                 .compatible = "lg,ld070wx3-sl01",
5346                 .data = &lg_ld070wx3_sl01
5347         }, {
5348                 .compatible = "lg,lh500wx1-sd03",
5349                 .data = &lg_lh500wx1_sd03
5350         }, {
5351                 .compatible = "panasonic,vvx10f004b00",
5352                 .data = &panasonic_vvx10f004b00
5353         }, {
5354                 .compatible = "lg,acx467akm-7",
5355                 .data = &lg_acx467akm_7
5356         }, {
5357                 .compatible = "osddisplays,osd101t2045-53ts",
5358                 .data = &osd101t2045_53ts
5359         }, {
5360                 /* sentinel */
5361         }
5362 };
5363 MODULE_DEVICE_TABLE(of, dsi_of_match);
5364
5365 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
5366 {
5367         const struct panel_desc_dsi *desc;
5368         int err;
5369
5370         desc = of_device_get_match_data(&dsi->dev);
5371         if (!desc)
5372                 return -ENODEV;
5373
5374         err = panel_simple_probe(&dsi->dev, &desc->desc);
5375         if (err < 0)
5376                 return err;
5377
5378         dsi->mode_flags = desc->flags;
5379         dsi->format = desc->format;
5380         dsi->lanes = desc->lanes;
5381
5382         err = mipi_dsi_attach(dsi);
5383         if (err) {
5384                 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
5385
5386                 drm_panel_remove(&panel->base);
5387         }
5388
5389         return err;
5390 }
5391
5392 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
5393 {
5394         int err;
5395
5396         err = mipi_dsi_detach(dsi);
5397         if (err < 0)
5398                 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
5399
5400         panel_simple_remove(&dsi->dev);
5401 }
5402
5403 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
5404 {
5405         panel_simple_shutdown(&dsi->dev);
5406 }
5407
5408 static struct mipi_dsi_driver panel_simple_dsi_driver = {
5409         .driver = {
5410                 .name = "panel-simple-dsi",
5411                 .of_match_table = dsi_of_match,
5412                 .pm = &panel_simple_pm_ops,
5413         },
5414         .probe = panel_simple_dsi_probe,
5415         .remove = panel_simple_dsi_remove,
5416         .shutdown = panel_simple_dsi_shutdown,
5417 };
5418
5419 static int __init panel_simple_init(void)
5420 {
5421         int err;
5422
5423         err = platform_driver_register(&panel_simple_platform_driver);
5424         if (err < 0)
5425                 return err;
5426
5427         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
5428                 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
5429                 if (err < 0)
5430                         goto err_did_platform_register;
5431         }
5432
5433         return 0;
5434
5435 err_did_platform_register:
5436         platform_driver_unregister(&panel_simple_platform_driver);
5437
5438         return err;
5439 }
5440 module_init(panel_simple_init);
5441
5442 static void __exit panel_simple_exit(void)
5443 {
5444         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
5445                 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
5446
5447         platform_driver_unregister(&panel_simple_platform_driver);
5448 }
5449 module_exit(panel_simple_exit);
5450
5451 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
5452 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
5453 MODULE_LICENSE("GPL and additional rights");