drivers/gpu/drm/panfrost/panfrost_device.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
   3 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
   4
   5 #ifndef __PANFROST_DEVICE_H__
   6 #define __PANFROST_DEVICE_H__
   7
   8 #include <linux/atomic.h>
   9 #include <linux/io-pgtable.h>
  10 #include <linux/pm.h>
  11 #include <linux/regulator/consumer.h>
  12 #include <linux/spinlock.h>
  13 #include <drm/drm_device.h>
  14 #include <drm/drm_mm.h>
  15 #include <drm/gpu_scheduler.h>
  16
  17 #include "panfrost_devfreq.h"
  18
  19 struct panfrost_device;
  20 struct panfrost_mmu;
  21 struct panfrost_job_slot;
  22 struct panfrost_job;
  23 struct panfrost_perfcnt;
  24
  25 #define NUM_JOB_SLOTS 3
  26 #define MAX_PM_DOMAINS 5
  27
  28 enum panfrost_drv_comp_bits {
  29         PANFROST_COMP_BIT_GPU,
  30         PANFROST_COMP_BIT_JOB,
  31         PANFROST_COMP_BIT_MMU,
  32         PANFROST_COMP_BIT_MAX
  33 };
  34
  35 /**
  36  * enum panfrost_gpu_pm - Supported kernel power management features
  37  * @GPU_PM_CLK_DIS:  Allow disabling clocks during system suspend
  38  * @GPU_PM_VREG_OFF: Allow turning off regulators during system suspend
  39  */
  40 enum panfrost_gpu_pm {
  41         GPU_PM_CLK_DIS,
  42         GPU_PM_VREG_OFF,
  43 };
  44
  45 struct panfrost_features {
  46         u16 id;
  47         u16 revision;
  48
  49         u64 shader_present;
  50         u64 tiler_present;
  51         u64 l2_present;
  52         u64 stack_present;
  53         u32 as_present;
  54         u32 js_present;
  55
  56         u32 l2_features;
  57         u32 core_features;
  58         u32 tiler_features;
  59         u32 mem_features;
  60         u32 mmu_features;
  61         u32 thread_features;
  62         u32 max_threads;
  63         u32 thread_max_workgroup_sz;
  64         u32 thread_max_barrier_sz;
  65         u32 coherency_features;
  66         u32 afbc_features;
  67         u32 texture_features[4];
  68         u32 js_features[16];
  69
  70         u32 nr_core_groups;
  71         u32 thread_tls_alloc;
  72
  73         unsigned long hw_features[64 / BITS_PER_LONG];
  74         unsigned long hw_issues[64 / BITS_PER_LONG];
  75 };
  76
  77 /*
  78  * Features that cannot be automatically detected and need matching using the
  79  * compatible string, typically SoC-specific.
  80  */
  81 struct panfrost_compatible {
  82         /* Supplies count and names. */
  83         int num_supplies;
  84         const char * const *supply_names;
  85         /*
  86          * Number of power domains required, note that values 0 and 1 are
  87          * handled identically, as only values > 1 need special handling.
  88          */
  89         int num_pm_domains;
  90         /* Only required if num_pm_domains > 1. */
  91         const char * const *pm_domain_names;
  92
  93         /* Vendor implementation quirks callback */
  94         void (*vendor_quirk)(struct panfrost_device *pfdev);
  95
  96         /* Allowed PM features */
  97         u8 pm_features;
  98 };
  99
 100 struct panfrost_device {
 101         struct device *dev;
 102         struct drm_device *ddev;
 103         struct platform_device *pdev;
 104         int gpu_irq;
 105         int mmu_irq;
 106
 107         void __iomem *iomem;
 108         struct clk *clock;
 109         struct clk *bus_clock;
 110         struct regulator_bulk_data *regulators;
 111         struct reset_control *rstc;
 112         /* pm_domains for devices with more than one. */
 113         struct device *pm_domain_devs[MAX_PM_DOMAINS];
 114         struct device_link *pm_domain_links[MAX_PM_DOMAINS];
 115         bool coherent;
 116
 117         struct panfrost_features features;
 118         const struct panfrost_compatible *comp;
 119         DECLARE_BITMAP(is_suspended, PANFROST_COMP_BIT_MAX);
 120
 121         spinlock_t as_lock;
 122         unsigned long as_in_use_mask;
 123         unsigned long as_alloc_mask;
 124         unsigned long as_faulty_mask;
 125         struct list_head as_lru_list;
 126
 127         struct panfrost_job_slot *js;
 128
 129         struct panfrost_job *jobs[NUM_JOB_SLOTS][2];
 130         struct list_head scheduled_jobs;
 131
 132         struct panfrost_perfcnt *perfcnt;
 133         bool profile_mode;
 134
 135         struct mutex sched_lock;
 136
 137         struct {
 138                 struct workqueue_struct *wq;
 139                 struct work_struct work;
 140                 atomic_t pending;
 141         } reset;
 142
 143         struct mutex shrinker_lock;
 144         struct list_head shrinker_list;
 145         struct shrinker *shrinker;
 146
 147         struct panfrost_devfreq pfdevfreq;
 148
 149         struct {
 150                 atomic_t use_count;
 151                 spinlock_t lock;
 152         } cycle_counter;
 153 };
 154
 155 struct panfrost_mmu {
 156         struct panfrost_device *pfdev;
 157         struct kref refcount;
 158         struct io_pgtable_cfg pgtbl_cfg;
 159         struct io_pgtable_ops *pgtbl_ops;
 160         struct drm_mm mm;
 161         spinlock_t mm_lock;
 162         int as;
 163         atomic_t as_count;
 164         struct list_head list;
 165 };
 166
 167 struct panfrost_engine_usage {
 168         unsigned long long elapsed_ns[NUM_JOB_SLOTS];
 169         unsigned long long cycles[NUM_JOB_SLOTS];
 170 };
 171
 172 struct panfrost_file_priv {
 173         struct panfrost_device *pfdev;
 174
 175         struct drm_sched_entity sched_entity[NUM_JOB_SLOTS];
 176
 177         struct panfrost_mmu *mmu;
 178
 179         struct panfrost_engine_usage engine_usage;
 180 };
 181
 182 static inline struct panfrost_device *to_panfrost_device(struct drm_device *ddev)
 183 {
 184         return ddev->dev_private;
 185 }
 186
 187 static inline int panfrost_model_cmp(struct panfrost_device *pfdev, s32 id)
 188 {
 189         s32 match_id = pfdev->features.id;
 190
 191         if (match_id & 0xf000)
 192                 match_id &= 0xf00f;
 193         return match_id - id;
 194 }
 195
 196 static inline bool panfrost_model_is_bifrost(struct panfrost_device *pfdev)
 197 {
 198         return panfrost_model_cmp(pfdev, 0x1000) >= 0;
 199 }
 200
 201 static inline bool panfrost_model_eq(struct panfrost_device *pfdev, s32 id)
 202 {
 203         return !panfrost_model_cmp(pfdev, id);
 204 }
 205
 206 int panfrost_unstable_ioctl_check(void);
 207
 208 int panfrost_device_init(struct panfrost_device *pfdev);
 209 void panfrost_device_fini(struct panfrost_device *pfdev);
 210 void panfrost_device_reset(struct panfrost_device *pfdev);
 211
 212 extern const struct dev_pm_ops panfrost_pm_ops;
 213
 214 enum drm_panfrost_exception_type {
 215         DRM_PANFROST_EXCEPTION_OK = 0x00,
 216         DRM_PANFROST_EXCEPTION_DONE = 0x01,
 217         DRM_PANFROST_EXCEPTION_INTERRUPTED = 0x02,
 218         DRM_PANFROST_EXCEPTION_STOPPED = 0x03,
 219         DRM_PANFROST_EXCEPTION_TERMINATED = 0x04,
 220         DRM_PANFROST_EXCEPTION_KABOOM = 0x05,
 221         DRM_PANFROST_EXCEPTION_EUREKA = 0x06,
 222         DRM_PANFROST_EXCEPTION_ACTIVE = 0x08,
 223         DRM_PANFROST_EXCEPTION_MAX_NON_FAULT = 0x3f,
 224         DRM_PANFROST_EXCEPTION_JOB_CONFIG_FAULT = 0x40,
 225         DRM_PANFROST_EXCEPTION_JOB_POWER_FAULT = 0x41,
 226         DRM_PANFROST_EXCEPTION_JOB_READ_FAULT = 0x42,
 227         DRM_PANFROST_EXCEPTION_JOB_WRITE_FAULT = 0x43,
 228         DRM_PANFROST_EXCEPTION_JOB_AFFINITY_FAULT = 0x44,
 229         DRM_PANFROST_EXCEPTION_JOB_BUS_FAULT = 0x48,
 230         DRM_PANFROST_EXCEPTION_INSTR_INVALID_PC = 0x50,
 231         DRM_PANFROST_EXCEPTION_INSTR_INVALID_ENC = 0x51,
 232         DRM_PANFROST_EXCEPTION_INSTR_TYPE_MISMATCH = 0x52,
 233         DRM_PANFROST_EXCEPTION_INSTR_OPERAND_FAULT = 0x53,
 234         DRM_PANFROST_EXCEPTION_INSTR_TLS_FAULT = 0x54,
 235         DRM_PANFROST_EXCEPTION_INSTR_BARRIER_FAULT = 0x55,
 236         DRM_PANFROST_EXCEPTION_INSTR_ALIGN_FAULT = 0x56,
 237         DRM_PANFROST_EXCEPTION_DATA_INVALID_FAULT = 0x58,
 238         DRM_PANFROST_EXCEPTION_TILE_RANGE_FAULT = 0x59,
 239         DRM_PANFROST_EXCEPTION_ADDR_RANGE_FAULT = 0x5a,
 240         DRM_PANFROST_EXCEPTION_IMPRECISE_FAULT = 0x5b,
 241         DRM_PANFROST_EXCEPTION_OOM = 0x60,
 242         DRM_PANFROST_EXCEPTION_OOM_AFBC = 0x61,
 243         DRM_PANFROST_EXCEPTION_UNKNOWN = 0x7f,
 244         DRM_PANFROST_EXCEPTION_DELAYED_BUS_FAULT = 0x80,
 245         DRM_PANFROST_EXCEPTION_GPU_SHAREABILITY_FAULT = 0x88,
 246         DRM_PANFROST_EXCEPTION_SYS_SHAREABILITY_FAULT = 0x89,
 247         DRM_PANFROST_EXCEPTION_GPU_CACHEABILITY_FAULT = 0x8a,
 248         DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_0 = 0xc0,
 249         DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_1 = 0xc1,
 250         DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_2 = 0xc2,
 251         DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_3 = 0xc3,
 252         DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_4 = 0xc4,
 253         DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_IDENTITY = 0xc7,
 254         DRM_PANFROST_EXCEPTION_PERM_FAULT_0 = 0xc8,
 255         DRM_PANFROST_EXCEPTION_PERM_FAULT_1 = 0xc9,
 256         DRM_PANFROST_EXCEPTION_PERM_FAULT_2 = 0xca,
 257         DRM_PANFROST_EXCEPTION_PERM_FAULT_3 = 0xcb,
 258         DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_0 = 0xd0,
 259         DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_1 = 0xd1,
 260         DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_2 = 0xd2,
 261         DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_3 = 0xd3,
 262         DRM_PANFROST_EXCEPTION_ACCESS_FLAG_0 = 0xd8,
 263         DRM_PANFROST_EXCEPTION_ACCESS_FLAG_1 = 0xd9,
 264         DRM_PANFROST_EXCEPTION_ACCESS_FLAG_2 = 0xda,
 265         DRM_PANFROST_EXCEPTION_ACCESS_FLAG_3 = 0xdb,
 266         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN0 = 0xe0,
 267         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN1 = 0xe1,
 268         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN2 = 0xe2,
 269         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN3 = 0xe3,
 270         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT0 = 0xe4,
 271         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT1 = 0xe5,
 272         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT2 = 0xe6,
 273         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT3 = 0xe7,
 274         DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_0 = 0xe8,
 275         DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_1 = 0xe9,
 276         DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_2 = 0xea,
 277         DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_3 = 0xeb,
 278         DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_0 = 0xec,
 279         DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_1 = 0xed,
 280         DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_2 = 0xee,
 281         DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_3 = 0xef,
 282 };
 283
 284 static inline bool
 285 panfrost_exception_is_fault(u32 exception_code)
 286 {
 287         return exception_code > DRM_PANFROST_EXCEPTION_MAX_NON_FAULT;
 288 }
 289
 290 const char *panfrost_exception_name(u32 exception_code);
 291 bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev,
 292                                     u32 exception_code);
 293
 294 static inline void
 295 panfrost_device_schedule_reset(struct panfrost_device *pfdev)
 296 {
 297         atomic_set(&pfdev->reset.pending, 1);
 298         queue_work(pfdev->reset.wq, &pfdev->reset.work);
 299 }
 300
 301 #endif