drivers/gpu/host1x/dev.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Tegra host1x driver
   4  *
   5  * Copyright (c) 2010-2013, NVIDIA Corporation.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/io.h>
  12 #include <linux/list.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/slab.h>
  19
  20 #include <soc/tegra/common.h>
  21
  22 #define CREATE_TRACE_POINTS
  23 #include <trace/events/host1x.h>
  24 #undef CREATE_TRACE_POINTS
  25
  26 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
  27 #include <asm/dma-iommu.h>
  28 #endif
  29
  30 #include "bus.h"
  31 #include "channel.h"
  32 #include "context.h"
  33 #include "debug.h"
  34 #include "dev.h"
  35 #include "intr.h"
  36
  37 #include "hw/host1x01.h"
  38 #include "hw/host1x02.h"
  39 #include "hw/host1x04.h"
  40 #include "hw/host1x05.h"
  41 #include "hw/host1x06.h"
  42 #include "hw/host1x07.h"
  43 #include "hw/host1x08.h"
  44
  45 void host1x_common_writel(struct host1x *host1x, u32 v, u32 r)
  46 {
  47         writel(v, host1x->common_regs + r);
  48 }
  49
  50 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
  51 {
  52         writel(v, host1x->hv_regs + r);
  53 }
  54
  55 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
  56 {
  57         return readl(host1x->hv_regs + r);
  58 }
  59
  60 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
  61 {
  62         void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  63
  64         writel(v, sync_regs + r);
  65 }
  66
  67 u32 host1x_sync_readl(struct host1x *host1x, u32 r)
  68 {
  69         void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  70
  71         return readl(sync_regs + r);
  72 }
  73
  74 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
  75 {
  76         writel(v, ch->regs + r);
  77 }
  78
  79 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
  80 {
  81         return readl(ch->regs + r);
  82 }
  83
  84 static const struct host1x_info host1x01_info = {
  85         .nb_channels = 8,
  86         .nb_pts = 32,
  87         .nb_mlocks = 16,
  88         .nb_bases = 8,
  89         .init = host1x01_init,
  90         .sync_offset = 0x3000,
  91         .dma_mask = DMA_BIT_MASK(32),
  92         .has_wide_gather = false,
  93         .has_hypervisor = false,
  94         .num_sid_entries = 0,
  95         .sid_table = NULL,
  96         .reserve_vblank_syncpts = true,
  97 };
  98
  99 static const struct host1x_info host1x02_info = {
 100         .nb_channels = 9,
 101         .nb_pts = 32,
 102         .nb_mlocks = 16,
 103         .nb_bases = 12,
 104         .init = host1x02_init,
 105         .sync_offset = 0x3000,
 106         .dma_mask = DMA_BIT_MASK(32),
 107         .has_wide_gather = false,
 108         .has_hypervisor = false,
 109         .num_sid_entries = 0,
 110         .sid_table = NULL,
 111         .reserve_vblank_syncpts = true,
 112 };
 113
 114 static const struct host1x_info host1x04_info = {
 115         .nb_channels = 12,
 116         .nb_pts = 192,
 117         .nb_mlocks = 16,
 118         .nb_bases = 64,
 119         .init = host1x04_init,
 120         .sync_offset = 0x2100,
 121         .dma_mask = DMA_BIT_MASK(34),
 122         .has_wide_gather = false,
 123         .has_hypervisor = false,
 124         .num_sid_entries = 0,
 125         .sid_table = NULL,
 126         .reserve_vblank_syncpts = false,
 127 };
 128
 129 static const struct host1x_info host1x05_info = {
 130         .nb_channels = 14,
 131         .nb_pts = 192,
 132         .nb_mlocks = 16,
 133         .nb_bases = 64,
 134         .init = host1x05_init,
 135         .sync_offset = 0x2100,
 136         .dma_mask = DMA_BIT_MASK(34),
 137         .has_wide_gather = false,
 138         .has_hypervisor = false,
 139         .num_sid_entries = 0,
 140         .sid_table = NULL,
 141         .reserve_vblank_syncpts = false,
 142 };
 143
 144 static const struct host1x_sid_entry tegra186_sid_table[] = {
 145         { /* SE1      */  .base = 0x1ac8, .offset = 0x90,    .limit = 0x90    },
 146         { /* SE2      */  .base = 0x1ad0, .offset = 0x90,    .limit = 0x90    },
 147         { /* SE3      */  .base = 0x1ad8, .offset = 0x90,    .limit = 0x90    },
 148         { /* SE4      */  .base = 0x1ae0, .offset = 0x90,    .limit = 0x90    },
 149         { /* ISP      */  .base = 0x1ae8, .offset = 0x50,    .limit = 0x50    },
 150         { /* VIC      */  .base = 0x1af0, .offset = 0x30,    .limit = 0x34    },
 151         { /* NVENC    */  .base = 0x1af8, .offset = 0x30,    .limit = 0x34    },
 152         { /* NVDEC    */  .base = 0x1b00, .offset = 0x30,    .limit = 0x34    },
 153         { /* NVJPG    */  .base = 0x1b08, .offset = 0x30,    .limit = 0x34    },
 154         { /* TSEC     */  .base = 0x1b10, .offset = 0x30,    .limit = 0x34    },
 155         { /* TSECB    */  .base = 0x1b18, .offset = 0x30,    .limit = 0x34    },
 156         { /* VI 0     */  .base = 0x1b80, .offset = 0x10000, .limit = 0x10000 },
 157         { /* VI 1     */  .base = 0x1b88, .offset = 0x20000, .limit = 0x20000 },
 158         { /* VI 2     */  .base = 0x1b90, .offset = 0x30000, .limit = 0x30000 },
 159         { /* VI 3     */  .base = 0x1b98, .offset = 0x40000, .limit = 0x40000 },
 160         { /* VI 4     */  .base = 0x1ba0, .offset = 0x50000, .limit = 0x50000 },
 161         { /* VI 5     */  .base = 0x1ba8, .offset = 0x60000, .limit = 0x60000 },
 162         { /* VI 6     */  .base = 0x1bb0, .offset = 0x70000, .limit = 0x70000 },
 163         { /* VI 7     */  .base = 0x1bb8, .offset = 0x80000, .limit = 0x80000 },
 164         { /* VI 8     */  .base = 0x1bc0, .offset = 0x90000, .limit = 0x90000 },
 165         { /* VI 9     */  .base = 0x1bc8, .offset = 0xa0000, .limit = 0xa0000 },
 166         { /* VI 10    */  .base = 0x1bd0, .offset = 0xb0000, .limit = 0xb0000 },
 167         { /* VI 11    */  .base = 0x1bd8, .offset = 0xc0000, .limit = 0xc0000 },
 168 };
 169
 170 static const struct host1x_info host1x06_info = {
 171         .nb_channels = 63,
 172         .nb_pts = 576,
 173         .nb_mlocks = 24,
 174         .nb_bases = 16,
 175         .init = host1x06_init,
 176         .sync_offset = 0x0,
 177         .dma_mask = DMA_BIT_MASK(40),
 178         .has_wide_gather = true,
 179         .has_hypervisor = true,
 180         .num_sid_entries = ARRAY_SIZE(tegra186_sid_table),
 181         .sid_table = tegra186_sid_table,
 182         .reserve_vblank_syncpts = false,
 183         .skip_reset_assert = true,
 184 };
 185
 186 static const struct host1x_sid_entry tegra194_sid_table[] = {
 187         { /* SE1          */  .base = 0x1ac8, .offset = 0x90,  .limit = 0x90  },
 188         { /* SE2          */  .base = 0x1ad0, .offset = 0x90,  .limit = 0x90  },
 189         { /* SE3          */  .base = 0x1ad8, .offset = 0x90,  .limit = 0x90  },
 190         { /* SE4          */  .base = 0x1ae0, .offset = 0x90,  .limit = 0x90  },
 191         { /* ISP          */  .base = 0x1ae8, .offset = 0x800, .limit = 0x800 },
 192         { /* VIC          */  .base = 0x1af0, .offset = 0x30,  .limit = 0x34  },
 193         { /* NVENC        */  .base = 0x1af8, .offset = 0x30,  .limit = 0x34  },
 194         { /* NVDEC        */  .base = 0x1b00, .offset = 0x30,  .limit = 0x34  },
 195         { /* NVJPG        */  .base = 0x1b08, .offset = 0x30,  .limit = 0x34  },
 196         { /* TSEC         */  .base = 0x1b10, .offset = 0x30,  .limit = 0x34  },
 197         { /* TSECB        */  .base = 0x1b18, .offset = 0x30,  .limit = 0x34  },
 198         { /* VI           */  .base = 0x1b80, .offset = 0x800, .limit = 0x800 },
 199         { /* VI_THI       */  .base = 0x1b88, .offset = 0x30,  .limit = 0x34  },
 200         { /* ISP_THI      */  .base = 0x1b90, .offset = 0x30,  .limit = 0x34  },
 201         { /* PVA0_CLUSTER */  .base = 0x1b98, .offset = 0x0,   .limit = 0x0   },
 202         { /* PVA0_CLUSTER */  .base = 0x1ba0, .offset = 0x0,   .limit = 0x0   },
 203         { /* NVDLA0       */  .base = 0x1ba8, .offset = 0x30,  .limit = 0x34  },
 204         { /* NVDLA1       */  .base = 0x1bb0, .offset = 0x30,  .limit = 0x34  },
 205         { /* NVENC1       */  .base = 0x1bb8, .offset = 0x30,  .limit = 0x34  },
 206         { /* NVDEC1       */  .base = 0x1bc0, .offset = 0x30,  .limit = 0x34  },
 207 };
 208
 209 static const struct host1x_info host1x07_info = {
 210         .nb_channels = 63,
 211         .nb_pts = 704,
 212         .nb_mlocks = 32,
 213         .nb_bases = 0,
 214         .init = host1x07_init,
 215         .sync_offset = 0x0,
 216         .dma_mask = DMA_BIT_MASK(40),
 217         .has_wide_gather = true,
 218         .has_hypervisor = true,
 219         .num_sid_entries = ARRAY_SIZE(tegra194_sid_table),
 220         .sid_table = tegra194_sid_table,
 221         .reserve_vblank_syncpts = false,
 222 };
 223
 224 /*
 225  * Tegra234 has two stream ID protection tables, one for setting stream IDs
 226  * through the channel path via SETSTREAMID, and one for setting them via
 227  * MMIO. We program each engine's data stream ID in the channel path table
 228  * and firmware stream ID in the MMIO path table.
 229  */
 230 static const struct host1x_sid_entry tegra234_sid_table[] = {
 231         { /* SE1 MMIO     */  .base = 0x1650, .offset = 0x90,  .limit = 0x90  },
 232         { /* SE1 ch       */  .base = 0x1730, .offset = 0x90,  .limit = 0x90  },
 233         { /* SE2 MMIO     */  .base = 0x1658, .offset = 0x90,  .limit = 0x90  },
 234         { /* SE2 ch       */  .base = 0x1738, .offset = 0x90,  .limit = 0x90  },
 235         { /* SE4 MMIO     */  .base = 0x1660, .offset = 0x90,  .limit = 0x90  },
 236         { /* SE4 ch       */  .base = 0x1740, .offset = 0x90,  .limit = 0x90  },
 237         { /* ISP MMIO     */  .base = 0x1680, .offset = 0x800, .limit = 0x800 },
 238         { /* VIC MMIO     */  .base = 0x1688, .offset = 0x34,  .limit = 0x34  },
 239         { /* VIC ch       */  .base = 0x17b8, .offset = 0x30,  .limit = 0x30  },
 240         { /* NVENC MMIO   */  .base = 0x1690, .offset = 0x34,  .limit = 0x34  },
 241         { /* NVENC ch     */  .base = 0x17c0, .offset = 0x30,  .limit = 0x30  },
 242         { /* NVDEC MMIO   */  .base = 0x1698, .offset = 0x34,  .limit = 0x34  },
 243         { /* NVDEC ch     */  .base = 0x17c8, .offset = 0x30,  .limit = 0x30  },
 244         { /* NVJPG MMIO   */  .base = 0x16a0, .offset = 0x34,  .limit = 0x34  },
 245         { /* NVJPG ch     */  .base = 0x17d0, .offset = 0x30,  .limit = 0x30  },
 246         { /* TSEC MMIO    */  .base = 0x16a8, .offset = 0x30,  .limit = 0x34  },
 247         { /* NVJPG1 MMIO  */  .base = 0x16b0, .offset = 0x34,  .limit = 0x34  },
 248         { /* NVJPG1 ch    */  .base = 0x17a8, .offset = 0x30,  .limit = 0x30  },
 249         { /* VI MMIO      */  .base = 0x16b8, .offset = 0x800, .limit = 0x800 },
 250         { /* VI_THI MMIO  */  .base = 0x16c0, .offset = 0x30,  .limit = 0x34  },
 251         { /* ISP_THI MMIO */  .base = 0x16c8, .offset = 0x30,  .limit = 0x34  },
 252         { /* NVDLA MMIO   */  .base = 0x16d8, .offset = 0x30,  .limit = 0x34  },
 253         { /* NVDLA ch     */  .base = 0x17e0, .offset = 0x30,  .limit = 0x34  },
 254         { /* NVDLA1 MMIO  */  .base = 0x16e0, .offset = 0x30,  .limit = 0x34  },
 255         { /* NVDLA1 ch    */  .base = 0x17e8, .offset = 0x30,  .limit = 0x34  },
 256         { /* OFA MMIO     */  .base = 0x16e8, .offset = 0x34,  .limit = 0x34  },
 257         { /* OFA ch       */  .base = 0x1768, .offset = 0x30,  .limit = 0x30  },
 258         { /* VI2 MMIO     */  .base = 0x16f0, .offset = 0x800, .limit = 0x800 },
 259         { /* VI2_THI MMIO */  .base = 0x16f8, .offset = 0x30,  .limit = 0x34  },
 260 };
 261
 262 static const struct host1x_info host1x08_info = {
 263         .nb_channels = 63,
 264         .nb_pts = 1024,
 265         .nb_mlocks = 24,
 266         .nb_bases = 0,
 267         .init = host1x08_init,
 268         .sync_offset = 0x0,
 269         .dma_mask = DMA_BIT_MASK(40),
 270         .has_wide_gather = true,
 271         .has_hypervisor = true,
 272         .has_common = true,
 273         .num_sid_entries = ARRAY_SIZE(tegra234_sid_table),
 274         .sid_table = tegra234_sid_table,
 275         .streamid_vm_table = { 0x1004, 128 },
 276         .classid_vm_table = { 0x1404, 25 },
 277         .mmio_vm_table = { 0x1504, 25 },
 278         .reserve_vblank_syncpts = false,
 279 };
 280
 281 static const struct of_device_id host1x_of_match[] = {
 282         { .compatible = "nvidia,tegra234-host1x", .data = &host1x08_info, },
 283         { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
 284         { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
 285         { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
 286         { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
 287         { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
 288         { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
 289         { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
 290         { },
 291 };
 292 MODULE_DEVICE_TABLE(of, host1x_of_match);
 293
 294 static void host1x_setup_virtualization_tables(struct host1x *host)
 295 {
 296         const struct host1x_info *info = host->info;
 297         unsigned int i;
 298
 299         if (!info->has_hypervisor)
 300                 return;
 301
 302         for (i = 0; i < info->num_sid_entries; i++) {
 303                 const struct host1x_sid_entry *entry = &info->sid_table[i];
 304
 305                 host1x_hypervisor_writel(host, entry->offset, entry->base);
 306                 host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
 307         }
 308
 309         for (i = 0; i < info->streamid_vm_table.count; i++) {
 310                 /* Allow access to all stream IDs to all VMs. */
 311                 host1x_hypervisor_writel(host, 0xff, info->streamid_vm_table.base + 4 * i);
 312         }
 313
 314         for (i = 0; i < info->classid_vm_table.count; i++) {
 315                 /* Allow access to all classes to all VMs. */
 316                 host1x_hypervisor_writel(host, 0xff, info->classid_vm_table.base + 4 * i);
 317         }
 318
 319         for (i = 0; i < info->mmio_vm_table.count; i++) {
 320                 /* Use VM1 (that's us) as originator VMID for engine MMIO accesses. */
 321                 host1x_hypervisor_writel(host, 0x1, info->mmio_vm_table.base + 4 * i);
 322         }
 323 }
 324
 325 static bool host1x_wants_iommu(struct host1x *host1x)
 326 {
 327         /* Our IOMMU usage policy doesn't currently play well with GART */
 328         if (of_machine_is_compatible("nvidia,tegra20"))
 329                 return false;
 330
 331         /*
 332          * If we support addressing a maximum of 32 bits of physical memory
 333          * and if the host1x firewall is enabled, there's no need to enable
 334          * IOMMU support. This can happen for example on Tegra20, Tegra30
 335          * and Tegra114.
 336          *
 337          * Tegra124 and later can address up to 34 bits of physical memory and
 338          * many platforms come equipped with more than 2 GiB of system memory,
 339          * which requires crossing the 4 GiB boundary. But there's a catch: on
 340          * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can
 341          * only address up to 32 bits of memory in GATHER opcodes, which means
 342          * that command buffers need to either be in the first 2 GiB of system
 343          * memory (which could quickly lead to memory exhaustion), or command
 344          * buffers need to be treated differently from other buffers (which is
 345          * not possible with the current ABI).
 346          *
 347          * A third option is to use the IOMMU in these cases to make sure all
 348          * buffers will be mapped into a 32-bit IOVA space that host1x can
 349          * address. This allows all of the system memory to be used and works
 350          * within the limitations of the host1x on these SoCs.
 351          *
 352          * In summary, default to enable IOMMU on Tegra124 and later. For any
 353          * of the earlier SoCs, only use the IOMMU for additional safety when
 354          * the host1x firewall is disabled.
 355          */
 356         if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) {
 357                 if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
 358                         return false;
 359         }
 360
 361         return true;
 362 }
 363
 364 static struct iommu_domain *host1x_iommu_attach(struct host1x *host)
 365 {
 366         struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev);
 367         int err;
 368
 369 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
 370         if (host->dev->archdata.mapping) {
 371                 struct dma_iommu_mapping *mapping =
 372                                 to_dma_iommu_mapping(host->dev);
 373                 arm_iommu_detach_device(host->dev);
 374                 arm_iommu_release_mapping(mapping);
 375
 376                 domain = iommu_get_domain_for_dev(host->dev);
 377         }
 378 #endif
 379
 380         /*
 381          * We may not always want to enable IOMMU support (for example if the
 382          * host1x firewall is already enabled and we don't support addressing
 383          * more than 32 bits of physical memory), so check for that first.
 384          *
 385          * Similarly, if host1x is already attached to an IOMMU (via the DMA
 386          * API), don't try to attach again.
 387          */
 388         if (!host1x_wants_iommu(host) || domain)
 389                 return domain;
 390
 391         host->group = iommu_group_get(host->dev);
 392         if (host->group) {
 393                 struct iommu_domain_geometry *geometry;
 394                 dma_addr_t start, end;
 395                 unsigned long order;
 396
 397                 err = iova_cache_get();
 398                 if (err < 0)
 399                         goto put_group;
 400
 401                 host->domain = iommu_paging_domain_alloc(host->dev);
 402                 if (IS_ERR(host->domain)) {
 403                         err = PTR_ERR(host->domain);
 404                         host->domain = NULL;
 405                         goto put_cache;
 406                 }
 407
 408                 err = iommu_attach_group(host->domain, host->group);
 409                 if (err) {
 410                         if (err == -ENODEV)
 411                                 err = 0;
 412
 413                         goto free_domain;
 414                 }
 415
 416                 geometry = &host->domain->geometry;
 417                 start = geometry->aperture_start & host->info->dma_mask;
 418                 end = geometry->aperture_end & host->info->dma_mask;
 419
 420                 order = __ffs(host->domain->pgsize_bitmap);
 421                 init_iova_domain(&host->iova, 1UL << order, start >> order);
 422                 host->iova_end = end;
 423
 424                 domain = host->domain;
 425         }
 426
 427         return domain;
 428
 429 free_domain:
 430         iommu_domain_free(host->domain);
 431         host->domain = NULL;
 432 put_cache:
 433         iova_cache_put();
 434 put_group:
 435         iommu_group_put(host->group);
 436         host->group = NULL;
 437
 438         return ERR_PTR(err);
 439 }
 440
 441 static int host1x_iommu_init(struct host1x *host)
 442 {
 443         u64 mask = host->info->dma_mask;
 444         struct iommu_domain *domain;
 445         int err;
 446
 447         domain = host1x_iommu_attach(host);
 448         if (IS_ERR(domain)) {
 449                 err = PTR_ERR(domain);
 450                 dev_err(host->dev, "failed to attach to IOMMU: %d\n", err);
 451                 return err;
 452         }
 453
 454         /*
 455          * If we're not behind an IOMMU make sure we don't get push buffers
 456          * that are allocated outside of the range addressable by the GATHER
 457          * opcode.
 458          *
 459          * Newer generations of Tegra (Tegra186 and later) support a wide
 460          * variant of the GATHER opcode that allows addressing more bits.
 461          */
 462         if (!domain && !host->info->has_wide_gather)
 463                 mask = DMA_BIT_MASK(32);
 464
 465         err = dma_coerce_mask_and_coherent(host->dev, mask);
 466         if (err < 0) {
 467                 dev_err(host->dev, "failed to set DMA mask: %d\n", err);
 468                 return err;
 469         }
 470
 471         return 0;
 472 }
 473
 474 static void host1x_iommu_exit(struct host1x *host)
 475 {
 476         if (host->domain) {
 477                 put_iova_domain(&host->iova);
 478                 iommu_detach_group(host->domain, host->group);
 479
 480                 iommu_domain_free(host->domain);
 481                 host->domain = NULL;
 482
 483                 iova_cache_put();
 484
 485                 iommu_group_put(host->group);
 486                 host->group = NULL;
 487         }
 488 }
 489
 490 static int host1x_get_resets(struct host1x *host)
 491 {
 492         int err;
 493
 494         host->resets[0].id = "mc";
 495         host->resets[1].id = "host1x";
 496         host->nresets = ARRAY_SIZE(host->resets);
 497
 498         err = devm_reset_control_bulk_get_optional_exclusive_released(
 499                                 host->dev, host->nresets, host->resets);
 500         if (err) {
 501                 dev_err(host->dev, "failed to get reset: %d\n", err);
 502                 return err;
 503         }
 504
 505         return 0;
 506 }
 507
 508 static int host1x_probe(struct platform_device *pdev)
 509 {
 510         struct host1x *host;
 511         int err, i;
 512
 513         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 514         if (!host)
 515                 return -ENOMEM;
 516
 517         host->info = of_device_get_match_data(&pdev->dev);
 518
 519         if (host->info->has_hypervisor) {
 520                 host->regs = devm_platform_ioremap_resource_byname(pdev, "vm");
 521                 if (IS_ERR(host->regs))
 522                         return PTR_ERR(host->regs);
 523
 524                 host->hv_regs = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
 525                 if (IS_ERR(host->hv_regs))
 526                         return PTR_ERR(host->hv_regs);
 527
 528                 if (host->info->has_common) {
 529                         host->common_regs = devm_platform_ioremap_resource_byname(pdev, "common");
 530                         if (IS_ERR(host->common_regs))
 531                                 return PTR_ERR(host->common_regs);
 532                 }
 533         } else {
 534                 host->regs = devm_platform_ioremap_resource(pdev, 0);
 535                 if (IS_ERR(host->regs))
 536                         return PTR_ERR(host->regs);
 537         }
 538
 539         for (i = 0; i < ARRAY_SIZE(host->syncpt_irqs); i++) {
 540                 char irq_name[] = "syncptX";
 541
 542                 sprintf(irq_name, "syncpt%d", i);
 543
 544                 err = platform_get_irq_byname_optional(pdev, irq_name);
 545                 if (err == -ENXIO)
 546                         break;
 547                 if (err < 0)
 548                         return err;
 549
 550                 host->syncpt_irqs[i] = err;
 551         }
 552
 553         host->num_syncpt_irqs = i;
 554
 555         /* Device tree without irq names */
 556         if (i == 0) {
 557                 host->syncpt_irqs[0] = platform_get_irq(pdev, 0);
 558                 if (host->syncpt_irqs[0] < 0)
 559                         return host->syncpt_irqs[0];
 560
 561                 host->num_syncpt_irqs = 1;
 562         }
 563
 564         mutex_init(&host->devices_lock);
 565         INIT_LIST_HEAD(&host->devices);
 566         INIT_LIST_HEAD(&host->list);
 567         host->dev = &pdev->dev;
 568
 569         /* set common host1x device data */
 570         platform_set_drvdata(pdev, host);
 571
 572         host->dev->dma_parms = &host->dma_parms;
 573         dma_set_max_seg_size(host->dev, UINT_MAX);
 574
 575         if (host->info->init) {
 576                 err = host->info->init(host);
 577                 if (err)
 578                         return err;
 579         }
 580
 581         host->clk = devm_clk_get(&pdev->dev, NULL);
 582         if (IS_ERR(host->clk)) {
 583                 err = PTR_ERR(host->clk);
 584
 585                 if (err != -EPROBE_DEFER)
 586                         dev_err(&pdev->dev, "failed to get clock: %d\n", err);
 587
 588                 return err;
 589         }
 590
 591         err = host1x_get_resets(host);
 592         if (err)
 593                 return err;
 594
 595         host1x_bo_cache_init(&host->cache);
 596
 597         err = host1x_iommu_init(host);
 598         if (err < 0) {
 599                 dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err);
 600                 goto destroy_cache;
 601         }
 602
 603         err = host1x_channel_list_init(&host->channel_list,
 604                                        host->info->nb_channels);
 605         if (err) {
 606                 dev_err(&pdev->dev, "failed to initialize channel list\n");
 607                 goto iommu_exit;
 608         }
 609
 610         err = host1x_memory_context_list_init(host);
 611         if (err) {
 612                 dev_err(&pdev->dev, "failed to initialize context list\n");
 613                 goto free_channels;
 614         }
 615
 616         err = host1x_syncpt_init(host);
 617         if (err) {
 618                 dev_err(&pdev->dev, "failed to initialize syncpts\n");
 619                 goto free_contexts;
 620         }
 621
 622         pm_runtime_enable(&pdev->dev);
 623
 624         err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
 625         if (err)
 626                 goto pm_disable;
 627
 628         /* the driver's code isn't ready yet for the dynamic RPM */
 629         err = pm_runtime_resume_and_get(&pdev->dev);
 630         if (err)
 631                 goto pm_disable;
 632
 633         err = host1x_intr_init(host);
 634         if (err) {
 635                 dev_err(&pdev->dev, "failed to initialize interrupts\n");
 636                 goto pm_put;
 637         }
 638
 639         host1x_debug_init(host);
 640
 641         err = host1x_register(host);
 642         if (err < 0)
 643                 goto deinit_debugfs;
 644
 645         err = devm_of_platform_populate(&pdev->dev);
 646         if (err < 0)
 647                 goto unregister;
 648
 649         return 0;
 650
 651 unregister:
 652         host1x_unregister(host);
 653 deinit_debugfs:
 654         host1x_debug_deinit(host);
 655         host1x_intr_deinit(host);
 656 pm_put:
 657         pm_runtime_put_sync_suspend(&pdev->dev);
 658 pm_disable:
 659         pm_runtime_disable(&pdev->dev);
 660         host1x_syncpt_deinit(host);
 661 free_contexts:
 662         host1x_memory_context_list_free(&host->context_list);
 663 free_channels:
 664         host1x_channel_list_free(&host->channel_list);
 665 iommu_exit:
 666         host1x_iommu_exit(host);
 667 destroy_cache:
 668         host1x_bo_cache_destroy(&host->cache);
 669
 670         return err;
 671 }
 672
 673 static void host1x_remove(struct platform_device *pdev)
 674 {
 675         struct host1x *host = platform_get_drvdata(pdev);
 676
 677         host1x_unregister(host);
 678         host1x_debug_deinit(host);
 679
 680         pm_runtime_force_suspend(&pdev->dev);
 681
 682         host1x_intr_deinit(host);
 683         host1x_syncpt_deinit(host);
 684         host1x_memory_context_list_free(&host->context_list);
 685         host1x_channel_list_free(&host->channel_list);
 686         host1x_iommu_exit(host);
 687         host1x_bo_cache_destroy(&host->cache);
 688 }
 689
 690 static int __maybe_unused host1x_runtime_suspend(struct device *dev)
 691 {
 692         struct host1x *host = dev_get_drvdata(dev);
 693         int err;
 694
 695         host1x_channel_stop_all(host);
 696         host1x_intr_stop(host);
 697         host1x_syncpt_save(host);
 698
 699         if (!host->info->skip_reset_assert) {
 700                 err = reset_control_bulk_assert(host->nresets, host->resets);
 701                 if (err) {
 702                         dev_err(dev, "failed to assert reset: %d\n", err);
 703                         goto resume_host1x;
 704                 }
 705
 706                 usleep_range(1000, 2000);
 707         }
 708
 709         clk_disable_unprepare(host->clk);
 710         reset_control_bulk_release(host->nresets, host->resets);
 711
 712         return 0;
 713
 714 resume_host1x:
 715         host1x_setup_virtualization_tables(host);
 716         host1x_syncpt_restore(host);
 717         host1x_intr_start(host);
 718
 719         return err;
 720 }
 721
 722 static int __maybe_unused host1x_runtime_resume(struct device *dev)
 723 {
 724         struct host1x *host = dev_get_drvdata(dev);
 725         int err;
 726
 727         err = reset_control_bulk_acquire(host->nresets, host->resets);
 728         if (err) {
 729                 dev_err(dev, "failed to acquire reset: %d\n", err);
 730                 return err;
 731         }
 732
 733         err = clk_prepare_enable(host->clk);
 734         if (err) {
 735                 dev_err(dev, "failed to enable clock: %d\n", err);
 736                 goto release_reset;
 737         }
 738
 739         err = reset_control_bulk_deassert(host->nresets, host->resets);
 740         if (err < 0) {
 741                 dev_err(dev, "failed to deassert reset: %d\n", err);
 742                 goto disable_clk;
 743         }
 744
 745         host1x_setup_virtualization_tables(host);
 746         host1x_syncpt_restore(host);
 747         host1x_intr_start(host);
 748
 749         return 0;
 750
 751 disable_clk:
 752         clk_disable_unprepare(host->clk);
 753 release_reset:
 754         reset_control_bulk_release(host->nresets, host->resets);
 755
 756         return err;
 757 }
 758
 759 static const struct dev_pm_ops host1x_pm_ops = {
 760         SET_RUNTIME_PM_OPS(host1x_runtime_suspend, host1x_runtime_resume,
 761                            NULL)
 762         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
 763 };
 764
 765 static struct platform_driver tegra_host1x_driver = {
 766         .driver = {
 767                 .name = "tegra-host1x",
 768                 .of_match_table = host1x_of_match,
 769                 .pm = &host1x_pm_ops,
 770         },
 771         .probe = host1x_probe,
 772         .remove = host1x_remove,
 773 };
 774
 775 static struct platform_driver * const drivers[] = {
 776         &tegra_host1x_driver,
 777         &tegra_mipi_driver,
 778 };
 779
 780 static int __init tegra_host1x_init(void)
 781 {
 782         int err;
 783
 784         err = bus_register(&host1x_bus_type);
 785         if (err < 0)
 786                 return err;
 787
 788         err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
 789         if (err < 0)
 790                 bus_unregister(&host1x_bus_type);
 791
 792         return err;
 793 }
 794 module_init(tegra_host1x_init);
 795
 796 static void __exit tegra_host1x_exit(void)
 797 {
 798         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
 799         bus_unregister(&host1x_bus_type);
 800 }
 801 module_exit(tegra_host1x_exit);
 802
 803 /**
 804  * host1x_get_dma_mask() - query the supported DMA mask for host1x
 805  * @host1x: host1x instance
 806  *
 807  * Note that this returns the supported DMA mask for host1x, which can be
 808  * different from the applicable DMA mask under certain circumstances.
 809  */
 810 u64 host1x_get_dma_mask(struct host1x *host1x)
 811 {
 812         return host1x->info->dma_mask;
 813 }
 814 EXPORT_SYMBOL(host1x_get_dma_mask);
 815
 816 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
 817 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
 818 MODULE_DESCRIPTION("Host1x driver for Tegra products");
 819 MODULE_LICENSE("GPL");