1 // SPDX-License-Identifier: GPL-2.0-only
3 * NXP LPC18xx Watchdog Timer (WDT)
5 * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
9 * The Watchdog consists of a fixed divide-by-4 clock pre-scaler and a 24-bit
10 * counter which decrements on every clock cycle.
13 #include <linux/clk.h>
15 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/watchdog.h>
21 #define LPC18XX_WDT_MOD 0x00
22 #define LPC18XX_WDT_MOD_WDEN BIT(0)
23 #define LPC18XX_WDT_MOD_WDRESET BIT(1)
25 #define LPC18XX_WDT_TC 0x04
26 #define LPC18XX_WDT_TC_MIN 0xff
27 #define LPC18XX_WDT_TC_MAX 0xffffff
29 #define LPC18XX_WDT_FEED 0x08
30 #define LPC18XX_WDT_FEED_MAGIC1 0xaa
31 #define LPC18XX_WDT_FEED_MAGIC2 0x55
33 #define LPC18XX_WDT_TV 0x0c
35 /* Clock pre-scaler */
36 #define LPC18XX_WDT_CLK_DIV 4
38 /* Timeout values in seconds */
39 #define LPC18XX_WDT_DEF_TIMEOUT 30U
42 module_param(heartbeat
, int, 0);
43 MODULE_PARM_DESC(heartbeat
, "Watchdog heartbeats in seconds (default="
44 __MODULE_STRING(LPC18XX_WDT_DEF_TIMEOUT
) ")");
46 static bool nowayout
= WATCHDOG_NOWAYOUT
;
47 module_param(nowayout
, bool, 0);
48 MODULE_PARM_DESC(nowayout
, "Watchdog cannot be stopped once started (default="
49 __MODULE_STRING(WATCHDOG_NOWAYOUT
) ")");
51 struct lpc18xx_wdt_dev
{
52 struct watchdog_device wdt_dev
;
55 unsigned long clk_rate
;
57 struct timer_list timer
;
61 static int lpc18xx_wdt_feed(struct watchdog_device
*wdt_dev
)
63 struct lpc18xx_wdt_dev
*lpc18xx_wdt
= watchdog_get_drvdata(wdt_dev
);
67 * An abort condition will occur if an interrupt happens during the feed
70 spin_lock_irqsave(&lpc18xx_wdt
->lock
, flags
);
71 writel(LPC18XX_WDT_FEED_MAGIC1
, lpc18xx_wdt
->base
+ LPC18XX_WDT_FEED
);
72 writel(LPC18XX_WDT_FEED_MAGIC2
, lpc18xx_wdt
->base
+ LPC18XX_WDT_FEED
);
73 spin_unlock_irqrestore(&lpc18xx_wdt
->lock
, flags
);
78 static void lpc18xx_wdt_timer_feed(struct timer_list
*t
)
80 struct lpc18xx_wdt_dev
*lpc18xx_wdt
= from_timer(lpc18xx_wdt
, t
, timer
);
81 struct watchdog_device
*wdt_dev
= &lpc18xx_wdt
->wdt_dev
;
83 lpc18xx_wdt_feed(wdt_dev
);
85 /* Use safe value (1/2 of real timeout) */
86 mod_timer(&lpc18xx_wdt
->timer
, jiffies
+
87 msecs_to_jiffies((wdt_dev
->timeout
* MSEC_PER_SEC
) / 2));
91 * Since LPC18xx Watchdog cannot be disabled in hardware, we must keep feeding
92 * it with a timer until userspace watchdog software takes over.
94 static int lpc18xx_wdt_stop(struct watchdog_device
*wdt_dev
)
96 struct lpc18xx_wdt_dev
*lpc18xx_wdt
= watchdog_get_drvdata(wdt_dev
);
98 lpc18xx_wdt_timer_feed(&lpc18xx_wdt
->timer
);
103 static void __lpc18xx_wdt_set_timeout(struct lpc18xx_wdt_dev
*lpc18xx_wdt
)
107 val
= DIV_ROUND_UP(lpc18xx_wdt
->wdt_dev
.timeout
* lpc18xx_wdt
->clk_rate
,
108 LPC18XX_WDT_CLK_DIV
);
109 writel(val
, lpc18xx_wdt
->base
+ LPC18XX_WDT_TC
);
112 static int lpc18xx_wdt_set_timeout(struct watchdog_device
*wdt_dev
,
113 unsigned int new_timeout
)
115 struct lpc18xx_wdt_dev
*lpc18xx_wdt
= watchdog_get_drvdata(wdt_dev
);
117 lpc18xx_wdt
->wdt_dev
.timeout
= new_timeout
;
118 __lpc18xx_wdt_set_timeout(lpc18xx_wdt
);
123 static unsigned int lpc18xx_wdt_get_timeleft(struct watchdog_device
*wdt_dev
)
125 struct lpc18xx_wdt_dev
*lpc18xx_wdt
= watchdog_get_drvdata(wdt_dev
);
128 val
= readl(lpc18xx_wdt
->base
+ LPC18XX_WDT_TV
);
129 return (val
* LPC18XX_WDT_CLK_DIV
) / lpc18xx_wdt
->clk_rate
;
132 static int lpc18xx_wdt_start(struct watchdog_device
*wdt_dev
)
134 struct lpc18xx_wdt_dev
*lpc18xx_wdt
= watchdog_get_drvdata(wdt_dev
);
137 if (timer_pending(&lpc18xx_wdt
->timer
))
138 del_timer(&lpc18xx_wdt
->timer
);
140 val
= readl(lpc18xx_wdt
->base
+ LPC18XX_WDT_MOD
);
141 val
|= LPC18XX_WDT_MOD_WDEN
;
142 val
|= LPC18XX_WDT_MOD_WDRESET
;
143 writel(val
, lpc18xx_wdt
->base
+ LPC18XX_WDT_MOD
);
146 * Setting the WDEN bit in the WDMOD register is not sufficient to
147 * enable the Watchdog. A valid feed sequence must be completed after
148 * setting WDEN before the Watchdog is capable of generating a reset.
150 lpc18xx_wdt_feed(wdt_dev
);
155 static int lpc18xx_wdt_restart(struct watchdog_device
*wdt_dev
,
156 unsigned long action
, void *data
)
158 struct lpc18xx_wdt_dev
*lpc18xx_wdt
= watchdog_get_drvdata(wdt_dev
);
163 * Incorrect feed sequence causes immediate watchdog reset if enabled.
165 spin_lock_irqsave(&lpc18xx_wdt
->lock
, flags
);
167 val
= readl(lpc18xx_wdt
->base
+ LPC18XX_WDT_MOD
);
168 val
|= LPC18XX_WDT_MOD_WDEN
;
169 val
|= LPC18XX_WDT_MOD_WDRESET
;
170 writel(val
, lpc18xx_wdt
->base
+ LPC18XX_WDT_MOD
);
172 writel(LPC18XX_WDT_FEED_MAGIC1
, lpc18xx_wdt
->base
+ LPC18XX_WDT_FEED
);
173 writel(LPC18XX_WDT_FEED_MAGIC2
, lpc18xx_wdt
->base
+ LPC18XX_WDT_FEED
);
175 writel(LPC18XX_WDT_FEED_MAGIC1
, lpc18xx_wdt
->base
+ LPC18XX_WDT_FEED
);
176 writel(LPC18XX_WDT_FEED_MAGIC1
, lpc18xx_wdt
->base
+ LPC18XX_WDT_FEED
);
178 spin_unlock_irqrestore(&lpc18xx_wdt
->lock
, flags
);
183 static const struct watchdog_info lpc18xx_wdt_info
= {
184 .identity
= "NXP LPC18xx Watchdog",
185 .options
= WDIOF_SETTIMEOUT
|
186 WDIOF_KEEPALIVEPING
|
190 static const struct watchdog_ops lpc18xx_wdt_ops
= {
191 .owner
= THIS_MODULE
,
192 .start
= lpc18xx_wdt_start
,
193 .stop
= lpc18xx_wdt_stop
,
194 .ping
= lpc18xx_wdt_feed
,
195 .set_timeout
= lpc18xx_wdt_set_timeout
,
196 .get_timeleft
= lpc18xx_wdt_get_timeleft
,
197 .restart
= lpc18xx_wdt_restart
,
200 static int lpc18xx_wdt_probe(struct platform_device
*pdev
)
202 struct lpc18xx_wdt_dev
*lpc18xx_wdt
;
203 struct device
*dev
= &pdev
->dev
;
205 lpc18xx_wdt
= devm_kzalloc(dev
, sizeof(*lpc18xx_wdt
), GFP_KERNEL
);
209 lpc18xx_wdt
->base
= devm_platform_ioremap_resource(pdev
, 0);
210 if (IS_ERR(lpc18xx_wdt
->base
))
211 return PTR_ERR(lpc18xx_wdt
->base
);
213 lpc18xx_wdt
->reg_clk
= devm_clk_get_enabled(dev
, "reg");
214 if (IS_ERR(lpc18xx_wdt
->reg_clk
)) {
215 dev_err(dev
, "failed to get the reg clock\n");
216 return PTR_ERR(lpc18xx_wdt
->reg_clk
);
219 lpc18xx_wdt
->wdt_clk
= devm_clk_get_enabled(dev
, "wdtclk");
220 if (IS_ERR(lpc18xx_wdt
->wdt_clk
)) {
221 dev_err(dev
, "failed to get the wdt clock\n");
222 return PTR_ERR(lpc18xx_wdt
->wdt_clk
);
225 /* We use the clock rate to calculate timeouts */
226 lpc18xx_wdt
->clk_rate
= clk_get_rate(lpc18xx_wdt
->wdt_clk
);
227 if (lpc18xx_wdt
->clk_rate
== 0) {
228 dev_err(dev
, "failed to get clock rate\n");
232 lpc18xx_wdt
->wdt_dev
.info
= &lpc18xx_wdt_info
;
233 lpc18xx_wdt
->wdt_dev
.ops
= &lpc18xx_wdt_ops
;
235 lpc18xx_wdt
->wdt_dev
.min_timeout
= DIV_ROUND_UP(LPC18XX_WDT_TC_MIN
*
236 LPC18XX_WDT_CLK_DIV
, lpc18xx_wdt
->clk_rate
);
238 lpc18xx_wdt
->wdt_dev
.max_timeout
= (LPC18XX_WDT_TC_MAX
*
239 LPC18XX_WDT_CLK_DIV
) / lpc18xx_wdt
->clk_rate
;
241 lpc18xx_wdt
->wdt_dev
.timeout
= min(lpc18xx_wdt
->wdt_dev
.max_timeout
,
242 LPC18XX_WDT_DEF_TIMEOUT
);
244 spin_lock_init(&lpc18xx_wdt
->lock
);
246 lpc18xx_wdt
->wdt_dev
.parent
= dev
;
247 watchdog_set_drvdata(&lpc18xx_wdt
->wdt_dev
, lpc18xx_wdt
);
249 watchdog_init_timeout(&lpc18xx_wdt
->wdt_dev
, heartbeat
, dev
);
251 __lpc18xx_wdt_set_timeout(lpc18xx_wdt
);
253 timer_setup(&lpc18xx_wdt
->timer
, lpc18xx_wdt_timer_feed
, 0);
255 watchdog_set_nowayout(&lpc18xx_wdt
->wdt_dev
, nowayout
);
256 watchdog_set_restart_priority(&lpc18xx_wdt
->wdt_dev
, 128);
258 platform_set_drvdata(pdev
, lpc18xx_wdt
);
260 watchdog_stop_on_reboot(&lpc18xx_wdt
->wdt_dev
);
261 return devm_watchdog_register_device(dev
, &lpc18xx_wdt
->wdt_dev
);
264 static void lpc18xx_wdt_remove(struct platform_device
*pdev
)
266 struct lpc18xx_wdt_dev
*lpc18xx_wdt
= platform_get_drvdata(pdev
);
268 dev_warn(&pdev
->dev
, "I quit now, hardware will probably reboot!\n");
269 del_timer_sync(&lpc18xx_wdt
->timer
);
272 static const struct of_device_id lpc18xx_wdt_match
[] = {
273 { .compatible
= "nxp,lpc1850-wwdt" },
276 MODULE_DEVICE_TABLE(of
, lpc18xx_wdt_match
);
278 static struct platform_driver lpc18xx_wdt_driver
= {
280 .name
= "lpc18xx-wdt",
281 .of_match_table
= lpc18xx_wdt_match
,
283 .probe
= lpc18xx_wdt_probe
,
284 .remove
= lpc18xx_wdt_remove
,
286 module_platform_driver(lpc18xx_wdt_driver
);
288 MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
289 MODULE_DESCRIPTION("NXP LPC18xx Watchdog Timer Driver");
290 MODULE_LICENSE("GPL v2");