| blob | 3bf3e5280b24639205b94603348650003ead4131 |
1 config ARM
2 bool
3 default y
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
18 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_IRQ_PROBE
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_SCHED_CLOCK
24 select GENERIC_SMP_IDLE_THREAD
25 select GENERIC_STRNCPY_FROM_USER
26 select GENERIC_STRNLEN_USER
27 select HARDIRQS_SW_RESEND
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
29 select HAVE_ARCH_KGDB
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
32 select HAVE_BPF_JIT
33 select HAVE_CONTEXT_TRACKING
34 select HAVE_C_RECORDMCOUNT
35 select HAVE_CC_STACKPROTECTOR
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
38 select HAVE_DMA_ATTRS
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
53 select HAVE_KERNEL_XZ
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
56 select HAVE_MEMBLOCK
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
60 select HAVE_PERF_REGS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_PREEMPT_LAZY
63 select HAVE_REGS_AND_STACK_ACCESS_API
64 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_UID16
66 select HAVE_VIRT_CPU_ACCOUNTING_GEN
67 select IRQ_FORCED_THREADING
68 select KTIME_SCALAR
69 select MODULES_USE_ELF_REL
70 select NO_BOOTMEM
71 select OLD_SIGACTION
72 select OLD_SIGSUSPEND3
73 select PERF_USE_VMALLOC
74 select RTC_LIB
75 select SYS_SUPPORTS_APM_EMULATION
76 # Above selects are sorted alphabetically; please add new ones
77 # according to that. Thanks.
78 help
79 The ARM series is a line of low-power-consumption RISC chip designs
80 licensed by ARM Ltd and targeted at embedded applications and
81 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
82 manufactured, but legacy ARM-based PC hardware remains popular in
83 Europe. There is an ARM Linux project with a web page at
84 <http://www.arm.linux.org.uk/>.
86 config ARM_HAS_SG_CHAIN
87 bool
89 config NEED_SG_DMA_LENGTH
90 bool
92 config ARM_DMA_USE_IOMMU
93 bool
94 select ARM_HAS_SG_CHAIN
95 select NEED_SG_DMA_LENGTH
97 if ARM_DMA_USE_IOMMU
99 config ARM_DMA_IOMMU_ALIGNMENT
100 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
101 range 4 9
102 default 8
103 help
104 DMA mapping framework by default aligns all buffers to the smallest
105 PAGE_SIZE order which is greater than or equal to the requested buffer
106 size. This works well for buffers up to a few hundreds kilobytes, but
107 for larger buffers it just a waste of address space. Drivers which has
108 relatively small addressing window (like 64Mib) might run out of
109 virtual space with just a few allocations.
111 With this parameter you can specify the maximum PAGE_SIZE order for
112 DMA IOMMU buffers. Larger buffers will be aligned only to this
113 specified order. The order is expressed as a power of two multiplied
114 by the PAGE_SIZE.
116 endif
118 config HAVE_PWM
119 bool
121 config MIGHT_HAVE_PCI
122 bool
124 config SYS_SUPPORTS_APM_EMULATION
125 bool
127 config HAVE_TCM
128 bool
129 select GENERIC_ALLOCATOR
131 config HAVE_PROC_CPU
132 bool
134 config NO_IOPORT
135 bool
137 config EISA
138 bool
139 ---help---
140 The Extended Industry Standard Architecture (EISA) bus was
141 developed as an open alternative to the IBM MicroChannel bus.
143 The EISA bus provided some of the features of the IBM MicroChannel
144 bus while maintaining backward compatibility with cards made for
145 the older ISA bus. The EISA bus saw limited use between 1988 and
146 1995 when it was made obsolete by the PCI bus.
148 Say Y here if you are building a kernel for an EISA-based machine.
150 Otherwise, say N.
152 config SBUS
153 bool
155 config STACKTRACE_SUPPORT
156 bool
157 default y
159 config HAVE_LATENCYTOP_SUPPORT
160 bool
161 depends on !SMP
162 default y
164 config LOCKDEP_SUPPORT
165 bool
166 default y
168 config TRACE_IRQFLAGS_SUPPORT
169 bool
170 default y
172 config RWSEM_GENERIC_SPINLOCK
173 bool
174 default y
176 config RWSEM_XCHGADD_ALGORITHM
177 bool
179 config ARCH_HAS_ILOG2_U32
180 bool
182 config ARCH_HAS_ILOG2_U64
183 bool
185 config ARCH_HAS_CPUFREQ
186 bool
187 help
188 Internal node to signify that the ARCH has CPUFREQ support
189 and that the relevant menu configurations are displayed for
190 it.
192 config ARCH_HAS_BANDGAP
193 bool
195 config GENERIC_HWEIGHT
196 bool
197 default y
199 config GENERIC_CALIBRATE_DELAY
200 bool
201 default y
203 config ARCH_MAY_HAVE_PC_FDC
204 bool
206 config ZONE_DMA
207 bool
209 config NEED_DMA_MAP_STATE
210 def_bool y
212 config ARCH_HAS_DMA_SET_COHERENT_MASK
213 bool
215 config GENERIC_ISA_DMA
216 bool
218 config FIQ
219 bool
221 config NEED_RET_TO_USER
222 bool
224 config ARCH_MTD_XIP
225 bool
227 config VECTORS_BASE
228 hex
229 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
230 default DRAM_BASE if REMAP_VECTORS_TO_RAM
231 default 0x00000000
232 help
233 The base address of exception vectors. This must be two pages
234 in size.
236 config ARM_PATCH_PHYS_VIRT
237 bool "Patch physical to virtual translations at runtime" if EMBEDDED
238 default y
239 depends on !XIP_KERNEL && MMU
240 depends on !ARCH_REALVIEW || !SPARSEMEM
241 help
242 Patch phys-to-virt and virt-to-phys translation functions at
243 boot and module load time according to the position of the
244 kernel in system memory.
246 This can only be used with non-XIP MMU kernels where the base
247 of physical memory is at a 16MB boundary.
249 Only disable this option if you know that you do not require
250 this feature (eg, building a kernel for a single machine) and
251 you need to shrink the kernel to the minimal size.
253 config NEED_MACH_GPIO_H
254 bool
255 help
256 Select this when mach/gpio.h is required to provide special
257 definitions for this platform. The need for mach/gpio.h should
258 be avoided when possible.
260 config NEED_MACH_IO_H
261 bool
262 help
263 Select this when mach/io.h is required to provide special
264 definitions for this platform. The need for mach/io.h should
265 be avoided when possible.
267 config NEED_MACH_MEMORY_H
268 bool
269 help
270 Select this when mach/memory.h is required to provide special
271 definitions for this platform. The need for mach/memory.h should
272 be avoided when possible.
274 config PHYS_OFFSET
275 hex "Physical address of main memory" if MMU
276 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
277 default DRAM_BASE if !MMU
278 help
279 Please provide the physical address corresponding to the
280 location of main memory in your system.
282 config GENERIC_BUG
283 def_bool y
284 depends on BUG
286 source "init/Kconfig"
288 source "kernel/Kconfig.freezer"
290 menu "System Type"
292 config MMU
293 bool "MMU-based Paged Memory Management Support"
294 default y
295 help
296 Select if you want MMU-based virtualised addressing space
297 support by paged memory management. If unsure, say 'Y'.
299 #
300 # The "ARM system type" choice list is ordered alphabetically by option
301 # text. Please add new entries in the option alphabetic order.
302 #
303 choice
304 prompt "ARM system type"
305 default ARCH_VERSATILE if !MMU
306 default ARCH_MULTIPLATFORM if MMU
308 config ARCH_MULTIPLATFORM
309 bool "Allow multiple platforms to be selected"
310 depends on MMU
311 select ARM_PATCH_PHYS_VIRT
312 select AUTO_ZRELADDR
313 select COMMON_CLK
314 select MULTI_IRQ_HANDLER
315 select SPARSE_IRQ
316 select USE_OF
318 config ARCH_INTEGRATOR
319 bool "ARM Ltd. Integrator family"
320 select ARCH_HAS_CPUFREQ
321 select ARM_AMBA
322 select ARM_PATCH_PHYS_VIRT
323 select AUTO_ZRELADDR
324 select COMMON_CLK
325 select COMMON_CLK_VERSATILE
326 select GENERIC_CLOCKEVENTS
327 select HAVE_TCM
328 select ICST
329 select MULTI_IRQ_HANDLER
330 select NEED_MACH_MEMORY_H
331 select PLAT_VERSATILE
332 select SPARSE_IRQ
333 select USE_OF
334 select VERSATILE_FPGA_IRQ
335 help
336 Support for ARM's Integrator platform.
338 config ARCH_REALVIEW
339 bool "ARM Ltd. RealView family"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
341 select ARM_AMBA
342 select ARM_TIMER_SP804
343 select COMMON_CLK
344 select COMMON_CLK_VERSATILE
345 select GENERIC_CLOCKEVENTS
346 select GPIO_PL061 if GPIOLIB
347 select ICST
348 select NEED_MACH_MEMORY_H
349 select PLAT_VERSATILE
350 select PLAT_VERSATILE_CLCD
351 help
352 This enables support for ARM Ltd RealView boards.
354 config ARCH_VERSATILE
355 bool "ARM Ltd. Versatile family"
356 select ARCH_WANT_OPTIONAL_GPIOLIB
357 select ARM_AMBA
358 select ARM_TIMER_SP804
359 select ARM_VIC
360 select CLKDEV_LOOKUP
361 select GENERIC_CLOCKEVENTS
362 select HAVE_MACH_CLKDEV
363 select ICST
364 select PLAT_VERSATILE
365 select PLAT_VERSATILE_CLCD
366 select PLAT_VERSATILE_CLOCK
367 select VERSATILE_FPGA_IRQ
368 help
369 This enables support for ARM Ltd Versatile board.
371 config ARCH_AT91
372 bool "Atmel AT91"
373 select ARCH_REQUIRE_GPIOLIB
374 select CLKDEV_LOOKUP
375 select IRQ_DOMAIN
376 select NEED_MACH_GPIO_H
377 select NEED_MACH_IO_H if PCCARD
378 select PINCTRL
379 select PINCTRL_AT91 if USE_OF
380 help
381 This enables support for systems based on Atmel
382 AT91RM9200 and AT91SAM9* processors.
384 config ARCH_CLPS711X
385 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
386 select ARCH_REQUIRE_GPIOLIB
387 select AUTO_ZRELADDR
388 select CLKSRC_MMIO
389 select COMMON_CLK
390 select CPU_ARM720T
391 select GENERIC_CLOCKEVENTS
392 select MFD_SYSCON
393 select MULTI_IRQ_HANDLER
394 select SPARSE_IRQ
395 help
396 Support for Cirrus Logic 711x/721x/731x based boards.
398 config ARCH_GEMINI
399 bool "Cortina Systems Gemini"
400 select ARCH_REQUIRE_GPIOLIB
401 select CLKSRC_MMIO
402 select CPU_FA526
403 select GENERIC_CLOCKEVENTS
404 help
405 Support for the Cortina Systems Gemini family SoCs
407 config ARCH_EBSA110
408 bool "EBSA-110"
409 select ARCH_USES_GETTIMEOFFSET
410 select CPU_SA110
411 select ISA
412 select NEED_MACH_IO_H
413 select NEED_MACH_MEMORY_H
414 select NO_IOPORT
415 help
416 This is an evaluation board for the StrongARM processor available
417 from Digital. It has limited hardware on-board, including an
418 Ethernet interface, two PCMCIA sockets, two serial ports and a
419 parallel port.
421 config ARCH_EFM32
422 bool "Energy Micro efm32"
423 depends on !MMU
424 select ARCH_REQUIRE_GPIOLIB
425 select ARM_NVIC
426 # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
427 # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
428 select CLKSRC_MMIO
429 select CLKSRC_OF
430 select COMMON_CLK
431 select CPU_V7M
432 select GENERIC_CLOCKEVENTS
433 select NO_DMA
434 select NO_IOPORT
435 select SPARSE_IRQ
436 select USE_OF
437 help
438 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
439 processors.
441 config ARCH_EP93XX
442 bool "EP93xx-based"
443 select ARCH_HAS_HOLES_MEMORYMODEL
444 select ARCH_REQUIRE_GPIOLIB
445 select ARCH_USES_GETTIMEOFFSET
446 select ARM_AMBA
447 select ARM_VIC
448 select CLKDEV_LOOKUP
449 select CPU_ARM920T
450 select NEED_MACH_MEMORY_H
451 help
452 This enables support for the Cirrus EP93xx series of CPUs.
454 config ARCH_FOOTBRIDGE
455 bool "FootBridge"
456 select CPU_SA110
457 select FOOTBRIDGE
458 select GENERIC_CLOCKEVENTS
459 select HAVE_IDE
460 select NEED_MACH_IO_H if !MMU
461 select NEED_MACH_MEMORY_H
462 help
463 Support for systems based on the DC21285 companion chip
464 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
466 config ARCH_NETX
467 bool "Hilscher NetX based"
468 select ARM_VIC
469 select CLKSRC_MMIO
470 select CPU_ARM926T
471 select GENERIC_CLOCKEVENTS
472 help
473 This enables support for systems based on the Hilscher NetX Soc
475 config ARCH_IOP13XX
476 bool "IOP13xx-based"
477 depends on MMU
478 select CPU_XSC3
479 select NEED_MACH_MEMORY_H
480 select NEED_RET_TO_USER
481 select PCI
482 select PLAT_IOP
483 select VMSPLIT_1G
484 help
485 Support for Intel's IOP13XX (XScale) family of processors.
487 config ARCH_IOP32X
488 bool "IOP32x-based"
489 depends on MMU
490 select ARCH_REQUIRE_GPIOLIB
491 select CPU_XSCALE
492 select GPIO_IOP
493 select NEED_RET_TO_USER
494 select PCI
495 select PLAT_IOP
496 help
497 Support for Intel's 80219 and IOP32X (XScale) family of
498 processors.
500 config ARCH_IOP33X
501 bool "IOP33x-based"
502 depends on MMU
503 select ARCH_REQUIRE_GPIOLIB
504 select CPU_XSCALE
505 select GPIO_IOP
506 select NEED_RET_TO_USER
507 select PCI
508 select PLAT_IOP
509 help
510 Support for Intel's IOP33X (XScale) family of processors.
512 config ARCH_IXP4XX
513 bool "IXP4xx-based"
514 depends on MMU
515 select ARCH_HAS_DMA_SET_COHERENT_MASK
516 select ARCH_SUPPORTS_BIG_ENDIAN
517 select ARCH_REQUIRE_GPIOLIB
518 select CLKSRC_MMIO
519 select CPU_XSCALE
520 select DMABOUNCE if PCI
521 select GENERIC_CLOCKEVENTS
522 select MIGHT_HAVE_PCI
523 select NEED_MACH_IO_H
524 select USB_EHCI_BIG_ENDIAN_DESC
525 select USB_EHCI_BIG_ENDIAN_MMIO
526 help
527 Support for Intel's IXP4XX (XScale) family of processors.
529 config ARCH_DOVE
530 bool "Marvell Dove"
531 select ARCH_REQUIRE_GPIOLIB
532 select CPU_PJ4
533 select GENERIC_CLOCKEVENTS
534 select MIGHT_HAVE_PCI
535 select MVEBU_MBUS
536 select PINCTRL
537 select PINCTRL_DOVE
538 select PLAT_ORION_LEGACY
539 select USB_ARCH_HAS_EHCI
540 help
541 Support for the Marvell Dove SoC 88AP510
543 config ARCH_KIRKWOOD
544 bool "Marvell Kirkwood"
545 select ARCH_HAS_CPUFREQ
546 select ARCH_REQUIRE_GPIOLIB
547 select CPU_FEROCEON
548 select GENERIC_CLOCKEVENTS
549 select MVEBU_MBUS
550 select PCI
551 select PCI_QUIRKS
552 select PINCTRL
553 select PINCTRL_KIRKWOOD
554 select PLAT_ORION_LEGACY
555 help
556 Support for the following Marvell Kirkwood series SoCs:
557 88F6180, 88F6192 and 88F6281.
559 config ARCH_MV78XX0
560 bool "Marvell MV78xx0"
561 select ARCH_REQUIRE_GPIOLIB
562 select CPU_FEROCEON
563 select GENERIC_CLOCKEVENTS
564 select MVEBU_MBUS
565 select PCI
566 select PLAT_ORION_LEGACY
567 help
568 Support for the following Marvell MV78xx0 series SoCs:
569 MV781x0, MV782x0.
571 config ARCH_ORION5X
572 bool "Marvell Orion"
573 depends on MMU
574 select ARCH_REQUIRE_GPIOLIB
575 select CPU_FEROCEON
576 select GENERIC_CLOCKEVENTS
577 select MVEBU_MBUS
578 select PCI
579 select PLAT_ORION_LEGACY
580 help
581 Support for the following Marvell Orion 5x series SoCs:
582 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
583 Orion-2 (5281), Orion-1-90 (6183).
585 config ARCH_MMP
586 bool "Marvell PXA168/910/MMP2"
587 depends on MMU
588 select ARCH_REQUIRE_GPIOLIB
589 select CLKDEV_LOOKUP
590 select GENERIC_ALLOCATOR
591 select GENERIC_CLOCKEVENTS
592 select GPIO_PXA
593 select IRQ_DOMAIN
594 select MULTI_IRQ_HANDLER
595 select PINCTRL
596 select PLAT_PXA
597 select SPARSE_IRQ
598 help
599 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
601 config ARCH_KS8695
602 bool "Micrel/Kendin KS8695"
603 select ARCH_REQUIRE_GPIOLIB
604 select CLKSRC_MMIO
605 select CPU_ARM922T
606 select GENERIC_CLOCKEVENTS
607 select NEED_MACH_MEMORY_H
608 help
609 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
610 System-on-Chip devices.
612 config ARCH_W90X900
613 bool "Nuvoton W90X900 CPU"
614 select ARCH_REQUIRE_GPIOLIB
615 select CLKDEV_LOOKUP
616 select CLKSRC_MMIO
617 select CPU_ARM926T
618 select GENERIC_CLOCKEVENTS
619 help
620 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
621 At present, the w90x900 has been renamed nuc900, regarding
622 the ARM series product line, you can login the following
623 link address to know more.
625 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
626 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
628 config ARCH_LPC32XX
629 bool "NXP LPC32XX"
630 select ARCH_REQUIRE_GPIOLIB
631 select ARM_AMBA
632 select CLKDEV_LOOKUP
633 select CLKSRC_MMIO
634 select CPU_ARM926T
635 select GENERIC_CLOCKEVENTS
636 select HAVE_IDE
637 select HAVE_PWM
638 select USB_ARCH_HAS_OHCI
639 select USE_OF
640 help
641 Support for the NXP LPC32XX family of processors
643 config ARCH_PXA
644 bool "PXA2xx/PXA3xx-based"
645 depends on MMU
646 select ARCH_HAS_CPUFREQ
647 select ARCH_MTD_XIP
648 select ARCH_REQUIRE_GPIOLIB
649 select ARM_CPU_SUSPEND if PM
650 select AUTO_ZRELADDR
651 select CLKDEV_LOOKUP
652 select CLKSRC_MMIO
653 select GENERIC_CLOCKEVENTS
654 select GPIO_PXA
655 select HAVE_IDE
656 select MULTI_IRQ_HANDLER
657 select PLAT_PXA
658 select SPARSE_IRQ
659 help
660 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
662 config ARCH_MSM_NODT
663 bool "Qualcomm MSM"
664 select ARCH_MSM
665 select ARCH_REQUIRE_GPIOLIB
666 select COMMON_CLK
667 select GENERIC_CLOCKEVENTS
668 help
669 Support for Qualcomm MSM/QSD based systems. This runs on the
670 apps processor of the MSM/QSD and depends on a shared memory
671 interface to the modem processor which runs the baseband
672 stack and controls some vital subsystems
673 (clock and power control, etc).
675 config ARCH_SHMOBILE_LEGACY
676 bool "Renesas ARM SoCs (non-multiplatform)"
677 select ARCH_SHMOBILE
678 select ARM_PATCH_PHYS_VIRT
679 select CLKDEV_LOOKUP
680 select GENERIC_CLOCKEVENTS
681 select HAVE_ARM_SCU if SMP
682 select HAVE_ARM_TWD if SMP
683 select HAVE_MACH_CLKDEV
684 select HAVE_SMP
685 select MIGHT_HAVE_CACHE_L2X0
686 select MULTI_IRQ_HANDLER
687 select NO_IOPORT
688 select PINCTRL
689 select PM_GENERIC_DOMAINS if PM
690 select SPARSE_IRQ
691 help
692 Support for Renesas ARM SoC platforms using a non-multiplatform
693 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
694 and RZ families.
696 config ARCH_RPC
697 bool "RiscPC"
698 select ARCH_ACORN
699 select ARCH_MAY_HAVE_PC_FDC
700 select ARCH_SPARSEMEM_ENABLE
701 select ARCH_USES_GETTIMEOFFSET
702 select FIQ
703 select HAVE_IDE
704 select HAVE_PATA_PLATFORM
705 select ISA_DMA_API
706 select NEED_MACH_IO_H
707 select NEED_MACH_MEMORY_H
708 select NO_IOPORT
709 select VIRT_TO_BUS
710 help
711 On the Acorn Risc-PC, Linux can support the internal IDE disk and
712 CD-ROM interface, serial and parallel port, and the floppy drive.
714 config ARCH_SA1100
715 bool "SA1100-based"
716 select ARCH_HAS_CPUFREQ
717 select ARCH_MTD_XIP
718 select ARCH_REQUIRE_GPIOLIB
719 select ARCH_SPARSEMEM_ENABLE
720 select CLKDEV_LOOKUP
721 select CLKSRC_MMIO
722 select CPU_FREQ
723 select CPU_SA1100
724 select GENERIC_CLOCKEVENTS
725 select HAVE_IDE
726 select ISA
727 select NEED_MACH_MEMORY_H
728 select SPARSE_IRQ
729 help
730 Support for StrongARM 11x0 based boards.
732 config ARCH_S3C24XX
733 bool "Samsung S3C24XX SoCs"
734 select ARCH_HAS_CPUFREQ
735 select ARCH_REQUIRE_GPIOLIB
736 select CLKDEV_LOOKUP
737 select CLKSRC_SAMSUNG_PWM
738 select GENERIC_CLOCKEVENTS
739 select GPIO_SAMSUNG
740 select HAVE_S3C2410_I2C if I2C
741 select HAVE_S3C2410_WATCHDOG if WATCHDOG
742 select HAVE_S3C_RTC if RTC_CLASS
743 select MULTI_IRQ_HANDLER
744 select NEED_MACH_IO_H
745 select SAMSUNG_ATAGS
746 help
747 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
748 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
749 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
750 Samsung SMDK2410 development board (and derivatives).
752 config ARCH_S3C64XX
753 bool "Samsung S3C64XX"
754 select ARCH_HAS_CPUFREQ
755 select ARCH_REQUIRE_GPIOLIB
756 select ARM_AMBA
757 select ARM_VIC
758 select CLKDEV_LOOKUP
759 select CLKSRC_SAMSUNG_PWM
760 select COMMON_CLK
761 select CPU_V6K
762 select GENERIC_CLOCKEVENTS
763 select GPIO_SAMSUNG
764 select HAVE_S3C2410_I2C if I2C
765 select HAVE_S3C2410_WATCHDOG if WATCHDOG
766 select HAVE_TCM
767 select NO_IOPORT
768 select PLAT_SAMSUNG
769 select PM_GENERIC_DOMAINS
770 select S3C_DEV_NAND
771 select S3C_GPIO_TRACK
772 select SAMSUNG_ATAGS
773 select SAMSUNG_WAKEMASK
774 select SAMSUNG_WDT_RESET
775 select USB_ARCH_HAS_OHCI
776 help
777 Samsung S3C64XX series based systems
779 config ARCH_S5P64X0
780 bool "Samsung S5P6440 S5P6450"
781 select CLKDEV_LOOKUP
782 select CLKSRC_SAMSUNG_PWM
783 select CPU_V6
784 select GENERIC_CLOCKEVENTS
785 select GPIO_SAMSUNG
786 select HAVE_S3C2410_I2C if I2C
787 select HAVE_S3C2410_WATCHDOG if WATCHDOG
788 select HAVE_S3C_RTC if RTC_CLASS
789 select NEED_MACH_GPIO_H
790 select SAMSUNG_ATAGS
791 select SAMSUNG_WDT_RESET
792 help
793 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
794 SMDK6450.
796 config ARCH_S5PC100
797 bool "Samsung S5PC100"
798 select ARCH_REQUIRE_GPIOLIB
799 select CLKDEV_LOOKUP
800 select CLKSRC_SAMSUNG_PWM
801 select CPU_V7
802 select GENERIC_CLOCKEVENTS
803 select GPIO_SAMSUNG
804 select HAVE_S3C2410_I2C if I2C
805 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 select HAVE_S3C_RTC if RTC_CLASS
807 select NEED_MACH_GPIO_H
808 select SAMSUNG_ATAGS
809 select SAMSUNG_WDT_RESET
810 help
811 Samsung S5PC100 series based systems
813 config ARCH_S5PV210
814 bool "Samsung S5PV210/S5PC110"
815 select ARCH_HAS_CPUFREQ
816 select ARCH_HAS_HOLES_MEMORYMODEL
817 select ARCH_SPARSEMEM_ENABLE
818 select CLKDEV_LOOKUP
819 select CLKSRC_SAMSUNG_PWM
820 select CPU_V7
821 select GENERIC_CLOCKEVENTS
822 select GPIO_SAMSUNG
823 select HAVE_S3C2410_I2C if I2C
824 select HAVE_S3C2410_WATCHDOG if WATCHDOG
825 select HAVE_S3C_RTC if RTC_CLASS
826 select NEED_MACH_GPIO_H
827 select NEED_MACH_MEMORY_H
828 select SAMSUNG_ATAGS
829 help
830 Samsung S5PV210/S5PC110 series based systems
832 config ARCH_EXYNOS
833 bool "Samsung EXYNOS"
834 select ARCH_HAS_CPUFREQ
835 select ARCH_HAS_HOLES_MEMORYMODEL
836 select ARCH_REQUIRE_GPIOLIB
837 select ARCH_SPARSEMEM_ENABLE
838 select ARM_GIC
839 select COMMON_CLK
840 select CPU_V7
841 select GENERIC_CLOCKEVENTS
842 select HAVE_S3C2410_I2C if I2C
843 select HAVE_S3C2410_WATCHDOG if WATCHDOG
844 select HAVE_S3C_RTC if RTC_CLASS
845 select NEED_MACH_MEMORY_H
846 select SPARSE_IRQ
847 select USE_OF
848 help
849 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
851 config ARCH_DAVINCI
852 bool "TI DaVinci"
853 select ARCH_HAS_HOLES_MEMORYMODEL
854 select ARCH_REQUIRE_GPIOLIB
855 select CLKDEV_LOOKUP
856 select GENERIC_ALLOCATOR
857 select GENERIC_CLOCKEVENTS
858 select GENERIC_IRQ_CHIP
859 select HAVE_IDE
860 select TI_PRIV_EDMA
861 select USE_OF
862 select ZONE_DMA
863 help
864 Support for TI's DaVinci platform.
866 config ARCH_OMAP1
867 bool "TI OMAP1"
868 depends on MMU
869 select ARCH_HAS_CPUFREQ
870 select ARCH_HAS_HOLES_MEMORYMODEL
871 select ARCH_OMAP
872 select ARCH_REQUIRE_GPIOLIB
873 select CLKDEV_LOOKUP
874 select CLKSRC_MMIO
875 select GENERIC_CLOCKEVENTS
876 select GENERIC_IRQ_CHIP
877 select HAVE_IDE
878 select IRQ_DOMAIN
879 select NEED_MACH_IO_H if PCCARD
880 select NEED_MACH_MEMORY_H
881 help
882 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
884 endchoice
886 menu "Multiple platform selection"
887 depends on ARCH_MULTIPLATFORM
889 comment "CPU Core family selection"
891 config ARCH_MULTI_V4T
892 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
893 depends on !ARCH_MULTI_V6_V7
894 select ARCH_MULTI_V4_V5
895 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
896 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
897 CPU_ARM925T || CPU_ARM940T)
899 config ARCH_MULTI_V5
900 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
901 depends on !ARCH_MULTI_V6_V7
902 select ARCH_MULTI_V4_V5
903 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
904 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
905 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
907 config ARCH_MULTI_V4_V5
908 bool
910 config ARCH_MULTI_V6
911 bool "ARMv6 based platforms (ARM11)"
912 select ARCH_MULTI_V6_V7
913 select CPU_V6
915 config ARCH_MULTI_V7
916 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
917 default y
918 select ARCH_MULTI_V6_V7
919 select CPU_V7
921 config ARCH_MULTI_V6_V7
922 bool
924 config ARCH_MULTI_CPU_AUTO
925 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
926 select ARCH_MULTI_V5
928 endmenu
930 #
931 # This is sorted alphabetically by mach-* pathname. However, plat-*
932 # Kconfigs may be included either alphabetically (according to the
933 # plat- suffix) or along side the corresponding mach-* source.
934 #
935 source "arch/arm/mach-mvebu/Kconfig"
937 source "arch/arm/mach-at91/Kconfig"
939 source "arch/arm/mach-bcm/Kconfig"
941 source "arch/arm/mach-bcm2835/Kconfig"
943 source "arch/arm/mach-berlin/Kconfig"
945 source "arch/arm/mach-clps711x/Kconfig"
947 source "arch/arm/mach-cns3xxx/Kconfig"
949 source "arch/arm/mach-davinci/Kconfig"
951 source "arch/arm/mach-dove/Kconfig"
953 source "arch/arm/mach-ep93xx/Kconfig"
955 source "arch/arm/mach-footbridge/Kconfig"
957 source "arch/arm/mach-gemini/Kconfig"
959 source "arch/arm/mach-highbank/Kconfig"
961 source "arch/arm/mach-hisi/Kconfig"
963 source "arch/arm/mach-integrator/Kconfig"
965 source "arch/arm/mach-iop32x/Kconfig"
967 source "arch/arm/mach-iop33x/Kconfig"
969 source "arch/arm/mach-iop13xx/Kconfig"
971 source "arch/arm/mach-ixp4xx/Kconfig"
973 source "arch/arm/mach-keystone/Kconfig"
975 source "arch/arm/mach-kirkwood/Kconfig"
977 source "arch/arm/mach-ks8695/Kconfig"
979 source "arch/arm/mach-msm/Kconfig"
981 source "arch/arm/mach-moxart/Kconfig"
983 source "arch/arm/mach-mv78xx0/Kconfig"
985 source "arch/arm/mach-imx/Kconfig"
987 source "arch/arm/mach-mxs/Kconfig"
989 source "arch/arm/mach-netx/Kconfig"
991 source "arch/arm/mach-nomadik/Kconfig"
993 source "arch/arm/mach-nspire/Kconfig"
995 source "arch/arm/plat-omap/Kconfig"
997 source "arch/arm/mach-omap1/Kconfig"
999 source "arch/arm/mach-omap2/Kconfig"
1001 source "arch/arm/mach-orion5x/Kconfig"
1003 source "arch/arm/mach-picoxcell/Kconfig"
1005 source "arch/arm/mach-pxa/Kconfig"
1006 source "arch/arm/plat-pxa/Kconfig"
1008 source "arch/arm/mach-mmp/Kconfig"
1010 source "arch/arm/mach-realview/Kconfig"
1012 source "arch/arm/mach-rockchip/Kconfig"
1014 source "arch/arm/mach-sa1100/Kconfig"
1016 source "arch/arm/plat-samsung/Kconfig"
1018 source "arch/arm/mach-socfpga/Kconfig"
1020 source "arch/arm/mach-spear/Kconfig"
1022 source "arch/arm/mach-sti/Kconfig"
1024 source "arch/arm/mach-s3c24xx/Kconfig"
1026 source "arch/arm/mach-s3c64xx/Kconfig"
1028 source "arch/arm/mach-s5p64x0/Kconfig"
1030 source "arch/arm/mach-s5pc100/Kconfig"
1032 source "arch/arm/mach-s5pv210/Kconfig"
1034 source "arch/arm/mach-exynos/Kconfig"
1036 source "arch/arm/mach-shmobile/Kconfig"
1038 source "arch/arm/mach-sunxi/Kconfig"
1040 source "arch/arm/mach-prima2/Kconfig"
1042 source "arch/arm/mach-tegra/Kconfig"
1044 source "arch/arm/mach-u300/Kconfig"
1046 source "arch/arm/mach-ux500/Kconfig"
1048 source "arch/arm/mach-versatile/Kconfig"
1050 source "arch/arm/mach-vexpress/Kconfig"
1051 source "arch/arm/plat-versatile/Kconfig"
1053 source "arch/arm/mach-virt/Kconfig"
1055 source "arch/arm/mach-vt8500/Kconfig"
1057 source "arch/arm/mach-w90x900/Kconfig"
1059 source "arch/arm/mach-zynq/Kconfig"
1061 # Definitions to make life easier
1062 config ARCH_ACORN
1063 bool
1065 config PLAT_IOP
1066 bool
1067 select GENERIC_CLOCKEVENTS
1069 config PLAT_ORION
1070 bool
1071 select CLKSRC_MMIO
1072 select COMMON_CLK
1073 select GENERIC_IRQ_CHIP
1074 select IRQ_DOMAIN
1076 config PLAT_ORION_LEGACY
1077 bool
1078 select PLAT_ORION
1080 config PLAT_PXA
1081 bool
1083 config PLAT_VERSATILE
1084 bool
1086 config ARM_TIMER_SP804
1087 bool
1088 select CLKSRC_MMIO
1089 select CLKSRC_OF if OF
1091 source "arch/arm/firmware/Kconfig"
1093 source arch/arm/mm/Kconfig
1095 config ARM_NR_BANKS
1096 int
1097 default 16 if ARCH_EP93XX
1098 default 8
1100 config IWMMXT
1101 bool "Enable iWMMXt support" if !CPU_PJ4
1102 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1103 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1104 help
1105 Enable support for iWMMXt context switching at run time if
1106 running on a CPU that supports it.
1108 config MULTI_IRQ_HANDLER
1109 bool
1110 help
1111 Allow each machine to specify it's own IRQ handler at run time.
1113 if !MMU
1114 source "arch/arm/Kconfig-nommu"
1115 endif
1117 config PJ4B_ERRATA_4742
1118 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1119 depends on CPU_PJ4B && MACH_ARMADA_370
1120 default y
1121 help
1122 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1123 Event (WFE) IDLE states, a specific timing sensitivity exists between
1124 the retiring WFI/WFE instructions and the newly issued subsequent
1125 instructions. This sensitivity can result in a CPU hang scenario.
1126 Workaround:
1127 The software must insert either a Data Synchronization Barrier (DSB)
1128 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1129 instruction
1131 config ARM_ERRATA_326103
1132 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1133 depends on CPU_V6
1134 help
1135 Executing a SWP instruction to read-only memory does not set bit 11
1136 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1137 treat the access as a read, preventing a COW from occurring and
1138 causing the faulting task to livelock.
1140 config ARM_ERRATA_411920
1141 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1142 depends on CPU_V6 || CPU_V6K
1143 help
1144 Invalidation of the Instruction Cache operation can
1145 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1146 It does not affect the MPCore. This option enables the ARM Ltd.
1147 recommended workaround.
1149 config ARM_ERRATA_430973
1150 bool "ARM errata: Stale prediction on replaced interworking branch"
1151 depends on CPU_V7
1152 help
1153 This option enables the workaround for the 430973 Cortex-A8
1154 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1155 interworking branch is replaced with another code sequence at the
1156 same virtual address, whether due to self-modifying code or virtual
1157 to physical address re-mapping, Cortex-A8 does not recover from the
1158 stale interworking branch prediction. This results in Cortex-A8
1159 executing the new code sequence in the incorrect ARM or Thumb state.
1160 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1161 and also flushes the branch target cache at every context switch.
1162 Note that setting specific bits in the ACTLR register may not be
1163 available in non-secure mode.
1165 config ARM_ERRATA_458693
1166 bool "ARM errata: Processor deadlock when a false hazard is created"
1167 depends on CPU_V7
1168 depends on !ARCH_MULTIPLATFORM
1169 help
1170 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1171 erratum. For very specific sequences of memory operations, it is
1172 possible for a hazard condition intended for a cache line to instead
1173 be incorrectly associated with a different cache line. This false
1174 hazard might then cause a processor deadlock. The workaround enables
1175 the L1 caching of the NEON accesses and disables the PLD instruction
1176 in the ACTLR register. Note that setting specific bits in the ACTLR
1177 register may not be available in non-secure mode.
1179 config ARM_ERRATA_460075
1180 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1181 depends on CPU_V7
1182 depends on !ARCH_MULTIPLATFORM
1183 help
1184 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1185 erratum. Any asynchronous access to the L2 cache may encounter a
1186 situation in which recent store transactions to the L2 cache are lost
1187 and overwritten with stale memory contents from external memory. The
1188 workaround disables the write-allocate mode for the L2 cache via the
1189 ACTLR register. Note that setting specific bits in the ACTLR register
1190 may not be available in non-secure mode.
1192 config ARM_ERRATA_742230
1193 bool "ARM errata: DMB operation may be faulty"
1194 depends on CPU_V7 && SMP
1195 depends on !ARCH_MULTIPLATFORM
1196 help
1197 This option enables the workaround for the 742230 Cortex-A9
1198 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1199 between two write operations may not ensure the correct visibility
1200 ordering of the two writes. This workaround sets a specific bit in
1201 the diagnostic register of the Cortex-A9 which causes the DMB
1202 instruction to behave as a DSB, ensuring the correct behaviour of
1203 the two writes.
1205 config ARM_ERRATA_742231
1206 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1207 depends on CPU_V7 && SMP
1208 depends on !ARCH_MULTIPLATFORM
1209 help
1210 This option enables the workaround for the 742231 Cortex-A9
1211 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1212 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1213 accessing some data located in the same cache line, may get corrupted
1214 data due to bad handling of the address hazard when the line gets
1215 replaced from one of the CPUs at the same time as another CPU is
1216 accessing it. This workaround sets specific bits in the diagnostic
1217 register of the Cortex-A9 which reduces the linefill issuing
1218 capabilities of the processor.
1220 config PL310_ERRATA_588369
1221 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1222 depends on CACHE_L2X0
1223 help
1224 The PL310 L2 cache controller implements three types of Clean &
1225 Invalidate maintenance operations: by Physical Address
1226 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1227 They are architecturally defined to behave as the execution of a
1228 clean operation followed immediately by an invalidate operation,
1229 both performing to the same memory location. This functionality
1230 is not correctly implemented in PL310 as clean lines are not
1231 invalidated as a result of these operations.
1233 config ARM_ERRATA_643719
1234 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1235 depends on CPU_V7 && SMP
1236 help
1237 This option enables the workaround for the 643719 Cortex-A9 (prior to
1238 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1239 register returns zero when it should return one. The workaround
1240 corrects this value, ensuring cache maintenance operations which use
1241 it behave as intended and avoiding data corruption.
1243 config ARM_ERRATA_720789
1244 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1245 depends on CPU_V7
1246 help
1247 This option enables the workaround for the 720789 Cortex-A9 (prior to
1248 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1249 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1250 As a consequence of this erratum, some TLB entries which should be
1251 invalidated are not, resulting in an incoherency in the system page
1252 tables. The workaround changes the TLB flushing routines to invalidate
1253 entries regardless of the ASID.
1255 config PL310_ERRATA_727915
1256 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1257 depends on CACHE_L2X0
1258 help
1259 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1260 operation (offset 0x7FC). This operation runs in background so that
1261 PL310 can handle normal accesses while it is in progress. Under very
1262 rare circumstances, due to this erratum, write data can be lost when
1263 PL310 treats a cacheable write transaction during a Clean &
1264 Invalidate by Way operation.
1266 config ARM_ERRATA_743622
1267 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1268 depends on CPU_V7
1269 depends on !ARCH_MULTIPLATFORM
1270 help
1271 This option enables the workaround for the 743622 Cortex-A9
1272 (r2p*) erratum. Under very rare conditions, a faulty
1273 optimisation in the Cortex-A9 Store Buffer may lead to data
1274 corruption. This workaround sets a specific bit in the diagnostic
1275 register of the Cortex-A9 which disables the Store Buffer
1276 optimisation, preventing the defect from occurring. This has no
1277 visible impact on the overall performance or power consumption of the
1278 processor.
1280 config ARM_ERRATA_751472
1281 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1282 depends on CPU_V7
1283 depends on !ARCH_MULTIPLATFORM
1284 help
1285 This option enables the workaround for the 751472 Cortex-A9 (prior
1286 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1287 completion of a following broadcasted operation if the second
1288 operation is received by a CPU before the ICIALLUIS has completed,
1289 potentially leading to corrupted entries in the cache or TLB.
1291 config PL310_ERRATA_753970
1292 bool "PL310 errata: cache sync operation may be faulty"
1293 depends on CACHE_PL310
1294 help
1295 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1297 Under some condition the effect of cache sync operation on
1298 the store buffer still remains when the operation completes.
1299 This means that the store buffer is always asked to drain and
1300 this prevents it from merging any further writes. The workaround
1301 is to replace the normal offset of cache sync operation (0x730)
1302 by another offset targeting an unmapped PL310 register 0x740.
1303 This has the same effect as the cache sync operation: store buffer
1304 drain and waiting for all buffers empty.
1306 config ARM_ERRATA_754322
1307 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1308 depends on CPU_V7
1309 help
1310 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1311 r3p*) erratum. A speculative memory access may cause a page table walk
1312 which starts prior to an ASID switch but completes afterwards. This
1313 can populate the micro-TLB with a stale entry which may be hit with
1314 the new ASID. This workaround places two dsb instructions in the mm
1315 switching code so that no page table walks can cross the ASID switch.
1317 config ARM_ERRATA_754327
1318 bool "ARM errata: no automatic Store Buffer drain"
1319 depends on CPU_V7 && SMP
1320 help
1321 This option enables the workaround for the 754327 Cortex-A9 (prior to
1322 r2p0) erratum. The Store Buffer does not have any automatic draining
1323 mechanism and therefore a livelock may occur if an external agent
1324 continuously polls a memory location waiting to observe an update.
1325 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1326 written polling loops from denying visibility of updates to memory.
1328 config ARM_ERRATA_364296
1329 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1330 depends on CPU_V6
1331 help
1332 This options enables the workaround for the 364296 ARM1136
1333 r0p2 erratum (possible cache data corruption with
1334 hit-under-miss enabled). It sets the undocumented bit 31 in
1335 the auxiliary control register and the FI bit in the control
1336 register, thus disabling hit-under-miss without putting the
1337 processor into full low interrupt latency mode. ARM11MPCore
1338 is not affected.
1340 config ARM_ERRATA_764369
1341 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1342 depends on CPU_V7 && SMP
1343 help
1344 This option enables the workaround for erratum 764369
1345 affecting Cortex-A9 MPCore with two or more processors (all
1346 current revisions). Under certain timing circumstances, a data
1347 cache line maintenance operation by MVA targeting an Inner
1348 Shareable memory region may fail to proceed up to either the
1349 Point of Coherency or to the Point of Unification of the
1350 system. This workaround adds a DSB instruction before the
1351 relevant cache maintenance functions and sets a specific bit
1352 in the diagnostic control register of the SCU.
1354 config PL310_ERRATA_769419
1355 bool "PL310 errata: no automatic Store Buffer drain"
1356 depends on CACHE_L2X0
1357 help
1358 On revisions of the PL310 prior to r3p2, the Store Buffer does
1359 not automatically drain. This can cause normal, non-cacheable
1360 writes to be retained when the memory system is idle, leading
1361 to suboptimal I/O performance for drivers using coherent DMA.
1362 This option adds a write barrier to the cpu_idle loop so that,
1363 on systems with an outer cache, the store buffer is drained
1364 explicitly.
1366 config ARM_ERRATA_775420
1367 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1368 depends on CPU_V7
1369 help
1370 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1371 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1372 operation aborts with MMU exception, it might cause the processor
1373 to deadlock. This workaround puts DSB before executing ISB if
1374 an abort may occur on cache maintenance.
1376 config ARM_ERRATA_798181
1377 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1378 depends on CPU_V7 && SMP
1379 help
1380 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1381 adequately shooting down all use of the old entries. This
1382 option enables the Linux kernel workaround for this erratum
1383 which sends an IPI to the CPUs that are running the same ASID
1384 as the one being invalidated.
1386 config ARM_ERRATA_773022
1387 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1388 depends on CPU_V7
1389 help
1390 This option enables the workaround for the 773022 Cortex-A15
1391 (up to r0p4) erratum. In certain rare sequences of code, the
1392 loop buffer may deliver incorrect instructions. This
1393 workaround disables the loop buffer to avoid the erratum.
1395 endmenu
1397 source "arch/arm/common/Kconfig"
1399 menu "Bus support"
1401 config ARM_AMBA
1402 bool
1404 config ISA
1405 bool
1406 help
1407 Find out whether you have ISA slots on your motherboard. ISA is the
1408 name of a bus system, i.e. the way the CPU talks to the other stuff
1409 inside your box. Other bus systems are PCI, EISA, MicroChannel
1410 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1411 newer boards don't support it. If you have ISA, say Y, otherwise N.
1413 # Select ISA DMA controller support
1414 config ISA_DMA
1415 bool
1416 select ISA_DMA_API
1418 # Select ISA DMA interface
1419 config ISA_DMA_API
1420 bool
1422 config PCI
1423 bool "PCI support" if MIGHT_HAVE_PCI
1424 help
1425 Find out whether you have a PCI motherboard. PCI is the name of a
1426 bus system, i.e. the way the CPU talks to the other stuff inside
1427 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1428 VESA. If you have PCI, say Y, otherwise N.
1430 config PCI_DOMAINS
1431 bool
1432 depends on PCI
1434 config PCI_NANOENGINE
1435 bool "BSE nanoEngine PCI support"
1436 depends on SA1100_NANOENGINE
1437 help
1438 Enable PCI on the BSE nanoEngine board.
1440 config PCI_SYSCALL
1441 def_bool PCI
1443 config PCI_HOST_ITE8152
1444 bool
1445 depends on PCI && MACH_ARMCORE
1446 default y
1447 select DMABOUNCE
1449 source "drivers/pci/Kconfig"
1450 source "drivers/pci/pcie/Kconfig"
1452 source "drivers/pcmcia/Kconfig"
1454 endmenu
1456 menu "Kernel Features"
1458 config HAVE_SMP
1459 bool
1460 help
1461 This option should be selected by machines which have an SMP-
1462 capable CPU.
1464 The only effect of this option is to make the SMP-related
1465 options available to the user for configuration.
1467 config SMP
1468 bool "Symmetric Multi-Processing"
1469 depends on CPU_V6K || CPU_V7
1470 depends on GENERIC_CLOCKEVENTS
1471 depends on HAVE_SMP
1472 depends on MMU || ARM_MPU
1473 help
1474 This enables support for systems with more than one CPU. If you have
1475 a system with only one CPU, say N. If you have a system with more
1476 than one CPU, say Y.
1478 If you say N here, the kernel will run on uni- and multiprocessor
1479 machines, but will use only one CPU of a multiprocessor machine. If
1480 you say Y here, the kernel will run on many, but not all,
1481 uniprocessor machines. On a uniprocessor machine, the kernel
1482 will run faster if you say N here.
1484 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1485 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1486 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1488 If you don't know what to do here, say N.
1490 config SMP_ON_UP
1491 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1492 depends on SMP && !XIP_KERNEL && MMU
1493 default y
1494 help
1495 SMP kernels contain instructions which fail on non-SMP processors.
1496 Enabling this option allows the kernel to modify itself to make
1497 these instructions safe. Disabling it allows about 1K of space
1498 savings.
1500 If you don't know what to do here, say Y.
1502 config ARM_CPU_TOPOLOGY
1503 bool "Support cpu topology definition"
1504 depends on SMP && CPU_V7
1505 default y
1506 help
1507 Support ARM cpu topology definition. The MPIDR register defines
1508 affinity between processors which is then used to describe the cpu
1509 topology of an ARM System.
1511 config SCHED_MC
1512 bool "Multi-core scheduler support"
1513 depends on ARM_CPU_TOPOLOGY
1514 help
1515 Multi-core scheduler support improves the CPU scheduler's decision
1516 making when dealing with multi-core CPU chips at a cost of slightly
1517 increased overhead in some places. If unsure say N here.
1519 config SCHED_SMT
1520 bool "SMT scheduler support"
1521 depends on ARM_CPU_TOPOLOGY
1522 help
1523 Improves the CPU scheduler's decision making when dealing with
1524 MultiThreading at a cost of slightly increased overhead in some
1525 places. If unsure say N here.
1527 config HAVE_ARM_SCU
1528 bool
1529 help
1530 This option enables support for the ARM system coherency unit
1532 config HAVE_ARM_ARCH_TIMER
1533 bool "Architected timer support"
1534 depends on CPU_V7
1535 select ARM_ARCH_TIMER
1536 select GENERIC_CLOCKEVENTS
1537 help
1538 This option enables support for the ARM architected timer
1540 config HAVE_ARM_TWD
1541 bool
1542 depends on SMP
1543 select CLKSRC_OF if OF
1544 help
1545 This options enables support for the ARM timer and watchdog unit
1547 config MCPM
1548 bool "Multi-Cluster Power Management"
1549 depends on CPU_V7 && SMP
1550 help
1551 This option provides the common power management infrastructure
1552 for (multi-)cluster based systems, such as big.LITTLE based
1553 systems.
1555 config BIG_LITTLE
1556 bool "big.LITTLE support (Experimental)"
1557 depends on CPU_V7 && SMP
1558 select MCPM
1559 help
1560 This option enables support selections for the big.LITTLE
1561 system architecture.
1563 config BL_SWITCHER
1564 bool "big.LITTLE switcher support"
1565 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1566 select CPU_PM
1567 select ARM_CPU_SUSPEND
1568 help
1569 The big.LITTLE "switcher" provides the core functionality to
1570 transparently handle transition between a cluster of A15's
1571 and a cluster of A7's in a big.LITTLE system.
1573 config BL_SWITCHER_DUMMY_IF
1574 tristate "Simple big.LITTLE switcher user interface"
1575 depends on BL_SWITCHER && DEBUG_KERNEL
1576 help
1577 This is a simple and dummy char dev interface to control
1578 the big.LITTLE switcher core code. It is meant for
1579 debugging purposes only.
1581 choice
1582 prompt "Memory split"
1583 depends on MMU
1584 default VMSPLIT_3G
1585 help
1586 Select the desired split between kernel and user memory.
1588 If you are not absolutely sure what you are doing, leave this
1589 option alone!
1591 config VMSPLIT_3G
1592 bool "3G/1G user/kernel split"
1593 config VMSPLIT_2G
1594 bool "2G/2G user/kernel split"
1595 config VMSPLIT_1G
1596 bool "1G/3G user/kernel split"
1597 endchoice
1599 config PAGE_OFFSET
1600 hex
1601 default PHYS_OFFSET if !MMU
1602 default 0x40000000 if VMSPLIT_1G
1603 default 0x80000000 if VMSPLIT_2G
1604 default 0xC0000000
1606 config NR_CPUS
1607 int "Maximum number of CPUs (2-32)"
1608 range 2 32
1609 depends on SMP
1610 default "4"
1612 config HOTPLUG_CPU
1613 bool "Support for hot-pluggable CPUs"
1614 depends on SMP
1615 help
1616 Say Y here to experiment with turning CPUs off and on. CPUs
1617 can be controlled through /sys/devices/system/cpu.
1619 config ARM_PSCI
1620 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1621 depends on CPU_V7
1622 help
1623 Say Y here if you want Linux to communicate with system firmware
1624 implementing the PSCI specification for CPU-centric power
1625 management operations described in ARM document number ARM DEN
1626 0022A ("Power State Coordination Interface System Software on
1627 ARM processors").
1629 # The GPIO number here must be sorted by descending number. In case of
1630 # a multiplatform kernel, we just want the highest value required by the
1631 # selected platforms.
1632 config ARCH_NR_GPIO
1633 int
1634 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1635 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1636 default 392 if ARCH_U8500
1637 default 352 if ARCH_VT8500
1638 default 288 if ARCH_SUNXI
1639 default 264 if MACH_H4700
1640 default 0
1641 help
1642 Maximum number of GPIOs in the system.
1644 If unsure, leave the default value.
1646 source kernel/Kconfig.preempt
1648 config HZ_FIXED
1649 int
1650 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1651 ARCH_S5PV210 || ARCH_EXYNOS4
1652 default AT91_TIMER_HZ if ARCH_AT91
1653 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1654 default 0
1656 choice
1657 depends on HZ_FIXED = 0
1658 prompt "Timer frequency"
1660 config HZ_100
1661 bool "100 Hz"
1663 config HZ_200
1664 bool "200 Hz"
1666 config HZ_250
1667 bool "250 Hz"
1669 config HZ_300
1670 bool "300 Hz"
1672 config HZ_500
1673 bool "500 Hz"
1675 config HZ_1000
1676 bool "1000 Hz"
1678 endchoice
1680 config HZ
1681 int
1682 default HZ_FIXED if HZ_FIXED != 0
1683 default 100 if HZ_100
1684 default 200 if HZ_200
1685 default 250 if HZ_250
1686 default 300 if HZ_300
1687 default 500 if HZ_500
1688 default 1000
1690 config SCHED_HRTICK
1691 def_bool HIGH_RES_TIMERS
1693 config THUMB2_KERNEL
1694 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1695 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1696 default y if CPU_THUMBONLY
1697 select AEABI
1698 select ARM_ASM_UNIFIED
1699 select ARM_UNWIND
1700 help
1701 By enabling this option, the kernel will be compiled in
1702 Thumb-2 mode. A compiler/assembler that understand the unified
1703 ARM-Thumb syntax is needed.
1705 If unsure, say N.
1707 config THUMB2_AVOID_R_ARM_THM_JUMP11
1708 bool "Work around buggy Thumb-2 short branch relocations in gas"
1709 depends on THUMB2_KERNEL && MODULES
1710 default y
1711 help
1712 Various binutils versions can resolve Thumb-2 branches to
1713 locally-defined, preemptible global symbols as short-range "b.n"
1714 branch instructions.
1716 This is a problem, because there's no guarantee the final
1717 destination of the symbol, or any candidate locations for a
1718 trampoline, are within range of the branch. For this reason, the
1719 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1720 relocation in modules at all, and it makes little sense to add
1721 support.
1723 The symptom is that the kernel fails with an "unsupported
1724 relocation" error when loading some modules.
1726 Until fixed tools are available, passing
1727 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1728 code which hits this problem, at the cost of a bit of extra runtime
1729 stack usage in some cases.
1731 The problem is described in more detail at:
1732 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1734 Only Thumb-2 kernels are affected.
1736 Unless you are sure your tools don't have this problem, say Y.
1738 config ARM_ASM_UNIFIED
1739 bool
1741 config AEABI
1742 bool "Use the ARM EABI to compile the kernel"
1743 help
1744 This option allows for the kernel to be compiled using the latest
1745 ARM ABI (aka EABI). This is only useful if you are using a user
1746 space environment that is also compiled with EABI.
1748 Since there are major incompatibilities between the legacy ABI and
1749 EABI, especially with regard to structure member alignment, this
1750 option also changes the kernel syscall calling convention to
1751 disambiguate both ABIs and allow for backward compatibility support
1752 (selected with CONFIG_OABI_COMPAT).
1754 To use this you need GCC version 4.0.0 or later.
1756 config OABI_COMPAT
1757 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1758 depends on AEABI && !THUMB2_KERNEL
1759 help
1760 This option preserves the old syscall interface along with the
1761 new (ARM EABI) one. It also provides a compatibility layer to
1762 intercept syscalls that have structure arguments which layout
1763 in memory differs between the legacy ABI and the new ARM EABI
1764 (only for non "thumb" binaries). This option adds a tiny
1765 overhead to all syscalls and produces a slightly larger kernel.
1767 The seccomp filter system will not be available when this is
1768 selected, since there is no way yet to sensibly distinguish
1769 between calling conventions during filtering.
1771 If you know you'll be using only pure EABI user space then you
1772 can say N here. If this option is not selected and you attempt
1773 to execute a legacy ABI binary then the result will be
1774 UNPREDICTABLE (in fact it can be predicted that it won't work
1775 at all). If in doubt say N.
1777 config ARCH_HAS_HOLES_MEMORYMODEL
1778 bool
1780 config ARCH_SPARSEMEM_ENABLE
1781 bool
1783 config ARCH_SPARSEMEM_DEFAULT
1784 def_bool ARCH_SPARSEMEM_ENABLE
1786 config ARCH_SELECT_MEMORY_MODEL
1787 def_bool ARCH_SPARSEMEM_ENABLE
1789 config HAVE_ARCH_PFN_VALID
1790 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1792 config HIGHMEM
1793 bool "High Memory Support"
1794 depends on MMU
1795 help
1796 The address space of ARM processors is only 4 Gigabytes large
1797 and it has to accommodate user address space, kernel address
1798 space as well as some memory mapped IO. That means that, if you
1799 have a large amount of physical memory and/or IO, not all of the
1800 memory can be "permanently mapped" by the kernel. The physical
1801 memory that is not permanently mapped is called "high memory".
1803 Depending on the selected kernel/user memory split, minimum
1804 vmalloc space and actual amount of RAM, you may not need this
1805 option which should result in a slightly faster kernel.
1807 If unsure, say n.
1809 config HIGHPTE
1810 bool "Allocate 2nd-level pagetables from highmem"
1811 depends on HIGHMEM
1813 config HW_PERF_EVENTS
1814 bool "Enable hardware performance counter support for perf events"
1815 depends on PERF_EVENTS
1816 default y
1817 help
1818 Enable hardware performance counter support for perf events. If
1819 disabled, perf events will use software events only.
1821 config SYS_SUPPORTS_HUGETLBFS
1822 def_bool y
1823 depends on ARM_LPAE
1825 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1826 def_bool y
1827 depends on ARM_LPAE
1829 config ARCH_WANT_GENERAL_HUGETLB
1830 def_bool y
1832 source "mm/Kconfig"
1834 config FORCE_MAX_ZONEORDER
1835 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1836 range 11 64 if ARCH_SHMOBILE_LEGACY
1837 default "12" if SOC_AM33XX
1838 default "9" if SA1111 || ARCH_EFM32
1839 default "11"
1840 help
1841 The kernel memory allocator divides physically contiguous memory
1842 blocks into "zones", where each zone is a power of two number of
1843 pages. This option selects the largest power of two that the kernel
1844 keeps in the memory allocator. If you need to allocate very large
1845 blocks of physically contiguous memory, then you may need to
1846 increase this value.
1848 This config option is actually maximum order plus one. For example,
1849 a value of 11 means that the largest free memory block is 2^10 pages.
1851 config ALIGNMENT_TRAP
1852 bool
1853 depends on CPU_CP15_MMU
1854 default y if !ARCH_EBSA110
1855 select HAVE_PROC_CPU if PROC_FS
1856 help
1857 ARM processors cannot fetch/store information which is not
1858 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1859 address divisible by 4. On 32-bit ARM processors, these non-aligned
1860 fetch/store instructions will be emulated in software if you say
1861 here, which has a severe performance impact. This is necessary for
1862 correct operation of some network protocols. With an IP-only
1863 configuration it is safe to say N, otherwise say Y.
1865 config UACCESS_WITH_MEMCPY
1866 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1867 depends on MMU
1868 default y if CPU_FEROCEON
1869 help
1870 Implement faster copy_to_user and clear_user methods for CPU
1871 cores where a 8-word STM instruction give significantly higher
1872 memory write throughput than a sequence of individual 32bit stores.
1874 A possible side effect is a slight increase in scheduling latency
1875 between threads sharing the same address space if they invoke
1876 such copy operations with large buffers.
1878 However, if the CPU data cache is using a write-allocate mode,
1879 this option is unlikely to provide any performance gain.
1881 config SECCOMP
1882 bool
1883 prompt "Enable seccomp to safely compute untrusted bytecode"
1884 ---help---
1885 This kernel feature is useful for number crunching applications
1886 that may need to compute untrusted bytecode during their
1887 execution. By using pipes or other transports made available to
1888 the process as file descriptors supporting the read/write
1889 syscalls, it's possible to isolate those applications in
1890 their own address space using seccomp. Once seccomp is
1891 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1892 and the task is only allowed to execute a few safe syscalls
1893 defined by each seccomp mode.
1895 config SWIOTLB
1896 def_bool y
1898 config IOMMU_HELPER
1899 def_bool SWIOTLB
1901 config XEN_DOM0
1902 def_bool y
1903 depends on XEN
1905 config XEN
1906 bool "Xen guest support on ARM (EXPERIMENTAL)"
1907 depends on ARM && AEABI && OF
1908 depends on CPU_V7 && !CPU_V6
1909 depends on !GENERIC_ATOMIC64
1910 depends on MMU
1911 select ARM_PSCI
1912 select SWIOTLB_XEN
1913 select ARCH_DMA_ADDR_T_64BIT
1914 help
1915 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1917 endmenu
1919 menu "Boot options"
1921 config USE_OF
1922 bool "Flattened Device Tree support"
1923 select IRQ_DOMAIN
1924 select OF
1925 select OF_EARLY_FLATTREE
1926 help
1927 Include support for flattened device tree machine descriptions.
1929 config ATAGS
1930 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1931 default y
1932 help
1933 This is the traditional way of passing data to the kernel at boot
1934 time. If you are solely relying on the flattened device tree (or
1935 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1936 to remove ATAGS support from your kernel binary. If unsure,
1937 leave this to y.
1939 config DEPRECATED_PARAM_STRUCT
1940 bool "Provide old way to pass kernel parameters"
1941 depends on ATAGS
1942 help
1943 This was deprecated in 2001 and announced to live on for 5 years.
1944 Some old boot loaders still use this way.
1946 # Compressed boot loader in ROM. Yes, we really want to ask about
1947 # TEXT and BSS so we preserve their values in the config files.
1948 config ZBOOT_ROM_TEXT
1949 hex "Compressed ROM boot loader base address"
1950 default "0"
1951 help
1952 The physical address at which the ROM-able zImage is to be
1953 placed in the target. Platforms which normally make use of
1954 ROM-able zImage formats normally set this to a suitable
1955 value in their defconfig file.
1957 If ZBOOT_ROM is not enabled, this has no effect.
1959 config ZBOOT_ROM_BSS
1960 hex "Compressed ROM boot loader BSS address"
1961 default "0"
1962 help
1963 The base address of an area of read/write memory in the target
1964 for the ROM-able zImage which must be available while the
1965 decompressor is running. It must be large enough to hold the
1966 entire decompressed kernel plus an additional 128 KiB.
1967 Platforms which normally make use of ROM-able zImage formats
1968 normally set this to a suitable value in their defconfig file.
1970 If ZBOOT_ROM is not enabled, this has no effect.
1972 config ZBOOT_ROM
1973 bool "Compressed boot loader in ROM/flash"
1974 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1975 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1976 help
1977 Say Y here if you intend to execute your compressed kernel image
1978 (zImage) directly from ROM or flash. If unsure, say N.
1980 choice
1981 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1982 depends on ZBOOT_ROM && ARCH_SH7372
1983 default ZBOOT_ROM_NONE
1984 help
1985 Include experimental SD/MMC loading code in the ROM-able zImage.
1986 With this enabled it is possible to write the ROM-able zImage
1987 kernel image to an MMC or SD card and boot the kernel straight
1988 from the reset vector. At reset the processor Mask ROM will load
1989 the first part of the ROM-able zImage which in turn loads the
1990 rest the kernel image to RAM.
1992 config ZBOOT_ROM_NONE
1993 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1994 help
1995 Do not load image from SD or MMC
1997 config ZBOOT_ROM_MMCIF
1998 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1999 help
2000 Load image from MMCIF hardware block.
2002 config ZBOOT_ROM_SH_MOBILE_SDHI
2003 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2004 help
2005 Load image from SDHI hardware block
2007 endchoice
2009 config ARM_APPENDED_DTB
2010 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2011 depends on OF
2012 help
2013 With this option, the boot code will look for a device tree binary
2014 (DTB) appended to zImage
2015 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2017 This is meant as a backward compatibility convenience for those
2018 systems with a bootloader that can't be upgraded to accommodate
2019 the documented boot protocol using a device tree.
2021 Beware that there is very little in terms of protection against
2022 this option being confused by leftover garbage in memory that might
2023 look like a DTB header after a reboot if no actual DTB is appended
2024 to zImage. Do not leave this option active in a production kernel
2025 if you don't intend to always append a DTB. Proper passing of the
2026 location into r2 of a bootloader provided DTB is always preferable
2027 to this option.
2029 config ARM_ATAG_DTB_COMPAT
2030 bool "Supplement the appended DTB with traditional ATAG information"
2031 depends on ARM_APPENDED_DTB
2032 help
2033 Some old bootloaders can't be updated to a DTB capable one, yet
2034 they provide ATAGs with memory configuration, the ramdisk address,
2035 the kernel cmdline string, etc. Such information is dynamically
2036 provided by the bootloader and can't always be stored in a static
2037 DTB. To allow a device tree enabled kernel to be used with such
2038 bootloaders, this option allows zImage to extract the information
2039 from the ATAG list and store it at run time into the appended DTB.
2041 choice
2042 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2043 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2045 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2046 bool "Use bootloader kernel arguments if available"
2047 help
2048 Uses the command-line options passed by the boot loader instead of
2049 the device tree bootargs property. If the boot loader doesn't provide
2050 any, the device tree bootargs property will be used.
2052 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2053 bool "Extend with bootloader kernel arguments"
2054 help
2055 The command-line arguments provided by the boot loader will be
2056 appended to the the device tree bootargs property.
2058 endchoice
2060 config CMDLINE
2061 string "Default kernel command string"
2062 default ""
2063 help
2064 On some architectures (EBSA110 and CATS), there is currently no way
2065 for the boot loader to pass arguments to the kernel. For these
2066 architectures, you should supply some command-line options at build
2067 time by entering them here. As a minimum, you should specify the
2068 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2070 choice
2071 prompt "Kernel command line type" if CMDLINE != ""
2072 default CMDLINE_FROM_BOOTLOADER
2073 depends on ATAGS
2075 config CMDLINE_FROM_BOOTLOADER
2076 bool "Use bootloader kernel arguments if available"
2077 help
2078 Uses the command-line options passed by the boot loader. If
2079 the boot loader doesn't provide any, the default kernel command
2080 string provided in CMDLINE will be used.
2082 config CMDLINE_EXTEND
2083 bool "Extend bootloader kernel arguments"
2084 help
2085 The command-line arguments provided by the boot loader will be
2086 appended to the default kernel command string.
2088 config CMDLINE_FORCE
2089 bool "Always use the default kernel command string"
2090 help
2091 Always use the default kernel command string, even if the boot
2092 loader passes other arguments to the kernel.
2093 This is useful if you cannot or don't want to change the
2094 command-line options your boot loader passes to the kernel.
2095 endchoice
2097 config XIP_KERNEL
2098 bool "Kernel Execute-In-Place from ROM"
2099 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2100 help
2101 Execute-In-Place allows the kernel to run from non-volatile storage
2102 directly addressable by the CPU, such as NOR flash. This saves RAM
2103 space since the text section of the kernel is not loaded from flash
2104 to RAM. Read-write sections, such as the data section and stack,
2105 are still copied to RAM. The XIP kernel is not compressed since
2106 it has to run directly from flash, so it will take more space to
2107 store it. The flash address used to link the kernel object files,
2108 and for storing it, is configuration dependent. Therefore, if you
2109 say Y here, you must know the proper physical address where to
2110 store the kernel image depending on your own flash memory usage.
2112 Also note that the make target becomes "make xipImage" rather than
2113 "make zImage" or "make Image". The final kernel binary to put in
2114 ROM memory will be arch/arm/boot/xipImage.
2116 If unsure, say N.
2118 config XIP_PHYS_ADDR
2119 hex "XIP Kernel Physical Location"
2120 depends on XIP_KERNEL
2121 default "0x00080000"
2122 help
2123 This is the physical address in your flash memory the kernel will
2124 be linked for and stored to. This address is dependent on your
2125 own flash usage.
2127 config KEXEC
2128 bool "Kexec system call (EXPERIMENTAL)"
2129 depends on (!SMP || PM_SLEEP_SMP)
2130 help
2131 kexec is a system call that implements the ability to shutdown your
2132 current kernel, and to start another kernel. It is like a reboot
2133 but it is independent of the system firmware. And like a reboot
2134 you can start any kernel with it, not just Linux.
2136 It is an ongoing process to be certain the hardware in a machine
2137 is properly shutdown, so do not be surprised if this code does not
2138 initially work for you.
2140 config ATAGS_PROC
2141 bool "Export atags in procfs"
2142 depends on ATAGS && KEXEC
2143 default y
2144 help
2145 Should the atags used to boot the kernel be exported in an "atags"
2146 file in procfs. Useful with kexec.
2148 config CRASH_DUMP
2149 bool "Build kdump crash kernel (EXPERIMENTAL)"
2150 help
2151 Generate crash dump after being started by kexec. This should
2152 be normally only set in special crash dump kernels which are
2153 loaded in the main kernel with kexec-tools into a specially
2154 reserved region and then later executed after a crash by
2155 kdump/kexec. The crash dump kernel must be compiled to a
2156 memory address not used by the main kernel
2158 For more details see Documentation/kdump/kdump.txt
2160 config AUTO_ZRELADDR
2161 bool "Auto calculation of the decompressed kernel image address"
2162 help
2163 ZRELADDR is the physical address where the decompressed kernel
2164 image will be placed. If AUTO_ZRELADDR is selected, the address
2165 will be determined at run-time by masking the current IP with
2166 0xf8000000. This assumes the zImage being placed in the first 128MB
2167 from start of memory.
2169 endmenu
2171 menu "CPU Power Management"
2173 if ARCH_HAS_CPUFREQ
2174 source "drivers/cpufreq/Kconfig"
2175 endif
2177 source "drivers/cpuidle/Kconfig"
2179 endmenu
2181 menu "Floating point emulation"
2183 comment "At least one emulation must be selected"
2185 config FPE_NWFPE
2186 bool "NWFPE math emulation"
2187 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2188 ---help---
2189 Say Y to include the NWFPE floating point emulator in the kernel.
2190 This is necessary to run most binaries. Linux does not currently
2191 support floating point hardware so you need to say Y here even if
2192 your machine has an FPA or floating point co-processor podule.
2194 You may say N here if you are going to load the Acorn FPEmulator
2195 early in the bootup.
2197 config FPE_NWFPE_XP
2198 bool "Support extended precision"
2199 depends on FPE_NWFPE
2200 help
2201 Say Y to include 80-bit support in the kernel floating-point
2202 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2203 Note that gcc does not generate 80-bit operations by default,
2204 so in most cases this option only enlarges the size of the
2205 floating point emulator without any good reason.
2207 You almost surely want to say N here.
2209 config FPE_FASTFPE
2210 bool "FastFPE math emulation (EXPERIMENTAL)"
2211 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2212 ---help---
2213 Say Y here to include the FAST floating point emulator in the kernel.
2214 This is an experimental much faster emulator which now also has full
2215 precision for the mantissa. It does not support any exceptions.
2216 It is very simple, and approximately 3-6 times faster than NWFPE.
2218 It should be sufficient for most programs. It may be not suitable
2219 for scientific calculations, but you have to check this for yourself.
2220 If you do not feel you need a faster FP emulation you should better
2221 choose NWFPE.
2223 config VFP
2224 bool "VFP-format floating point maths"
2225 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2226 help
2227 Say Y to include VFP support code in the kernel. This is needed
2228 if your hardware includes a VFP unit.
2230 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2231 release notes and additional status information.
2233 Say N if your target does not have VFP hardware.
2235 config VFPv3
2236 bool
2237 depends on VFP
2238 default y if CPU_V7
2240 config NEON
2241 bool "Advanced SIMD (NEON) Extension support"
2242 depends on VFPv3 && CPU_V7
2243 help
2244 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2245 Extension.
2247 config KERNEL_MODE_NEON
2248 bool "Support for NEON in kernel mode"
2249 depends on NEON && AEABI
2250 help
2251 Say Y to include support for NEON in kernel mode.
2253 endmenu
2255 menu "Userspace binary formats"
2257 source "fs/Kconfig.binfmt"
2259 config ARTHUR
2260 tristate "RISC OS personality"
2261 depends on !AEABI
2262 help
2263 Say Y here to include the kernel code necessary if you want to run
2264 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2265 experimental; if this sounds frightening, say N and sleep in peace.
2266 You can also say M here to compile this support as a module (which
2267 will be called arthur).
2269 endmenu
2271 menu "Power management options"
2273 source "kernel/power/Kconfig"
2275 config ARCH_SUSPEND_POSSIBLE
2276 depends on !ARCH_S5PC100
2277 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2278 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2279 def_bool y
2281 config ARM_CPU_SUSPEND
2282 def_bool PM_SLEEP
2284 endmenu
2286 source "net/Kconfig"
2288 source "drivers/Kconfig"
2290 source "fs/Kconfig"
2292 source "arch/arm/Kconfig.debug"
2294 source "security/Kconfig"
2296 source "crypto/Kconfig"
2298 source "lib/Kconfig"
2300 source "arch/arm/kvm/Kconfig"