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Lynx framebuffers multidomain implementation.
[linux/elbrus.git] / arch / arm / mm / alignment.c
blobd301662b7b329e95981b8c5ceb812856c18b68c3
1 /*
2 * linux/arch/arm/mm/alignment.c
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 * Modifications for ARM processor (c) 1995-2001 Russell King
6 * Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
7 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
8 * Copyright (C) 1996, Cygnus Software Technologies Ltd.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14 #include <linux/moduleparam.h>
15 #include <linux/compiler.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/proc_fs.h>
20 #include <linux/seq_file.h>
21 #include <linux/init.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24
25 #include <asm/cp15.h>
26 #include <asm/system_info.h>
27 #include <asm/unaligned.h>
28 #include <asm/opcodes.h>
29
30 #include "fault.h"
31
32 /*
33 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
34 * /proc/sys/debug/alignment, modified and integrated into
35 * Linux 2.1 by Russell King
36 *
37 * Speed optimisations and better fault handling by Russell King.
38 *
39 * *** NOTE ***
40 * This code is not portable to processors with late data abort handling.
41 */
42 #define CODING_BITS(i) (i & 0x0e000000)
43 #define COND_BITS(i) (i & 0xf0000000)
44
45 #define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
46 #define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
47 #define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */
48 #define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */
49 #define LDST_L_BIT(i) (i & (1 << 20)) /* Load */
50
51 #define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
52
53 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
54 #define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */
55
56 #define RN_BITS(i) ((i >> 16) & 15) /* Rn */
57 #define RD_BITS(i) ((i >> 12) & 15) /* Rd */
58 #define RM_BITS(i) (i & 15) /* Rm */
59
60 #define REGMASK_BITS(i) (i & 0xffff)
61 #define OFFSET_BITS(i) (i & 0x0fff)
62
63 #define IS_SHIFT(i) (i & 0x0ff0)
64 #define SHIFT_BITS(i) ((i >> 7) & 0x1f)
65 #define SHIFT_TYPE(i) (i & 0x60)
66 #define SHIFT_LSL 0x00
67 #define SHIFT_LSR 0x20
68 #define SHIFT_ASR 0x40
69 #define SHIFT_RORRRX 0x60
70
71 #define BAD_INSTR 0xdeadc0de
72
73 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
74 #define IS_T32(hi16) \
75 (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
76
77 static unsigned long ai_user;
78 static unsigned long ai_sys;
79 static unsigned long ai_skipped;
80 static unsigned long ai_half;
81 static unsigned long ai_word;
82 static unsigned long ai_dword;
83 static unsigned long ai_multi;
84 static int ai_usermode;
85
86 core_param(alignment, ai_usermode, int, 0600);
87
88 #define UM_WARN (1 << 0)
89 #define UM_FIXUP (1 << 1)
90 #define UM_SIGNAL (1 << 2)
91
92 /* Return true if and only if the ARMv6 unaligned access model is in use. */
93 static bool cpu_is_v6_unaligned(void)
94 {
95 return cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U);
96 }
97
98 static int safe_usermode(int new_usermode, bool warn)
99 {
100 /*
101 * ARMv6 and later CPUs can perform unaligned accesses for
102 * most single load and store instructions up to word size.
103 * LDM, STM, LDRD and STRD still need to be handled.
104 *
105 * Ignoring the alignment fault is not an option on these
106 * CPUs since we spin re-faulting the instruction without
107 * making any progress.
108 */
109 if (cpu_is_v6_unaligned() && !(new_usermode & (UM_FIXUP | UM_SIGNAL))) {
110 new_usermode |= UM_FIXUP;
111
112 if (warn)
113 printk(KERN_WARNING "alignment: ignoring faults is unsafe on this CPU. Defaulting to fixup mode.\n");
114 }
115
116 return new_usermode;
117 }
118
119 #ifdef CONFIG_PROC_FS
120 static const char *usermode_action[] = {
121 "ignored",
122 "warn",
123 "fixup",
124 "fixup+warn",
125 "signal",
126 "signal+warn"
127 };
128
129 static int alignment_proc_show(struct seq_file *m, void *v)
130 {
131 seq_printf(m, "User:\t\t%lu\n", ai_user);
132 seq_printf(m, "System:\t\t%lu\n", ai_sys);
133 seq_printf(m, "Skipped:\t%lu\n", ai_skipped);
134 seq_printf(m, "Half:\t\t%lu\n", ai_half);
135 seq_printf(m, "Word:\t\t%lu\n", ai_word);
136 if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
137 seq_printf(m, "DWord:\t\t%lu\n", ai_dword);
138 seq_printf(m, "Multi:\t\t%lu\n", ai_multi);
139 seq_printf(m, "User faults:\t%i (%s)\n", ai_usermode,
140 usermode_action[ai_usermode]);
141
142 return 0;
143 }
144
145 static int alignment_proc_open(struct inode *inode, struct file *file)
146 {
147 return single_open(file, alignment_proc_show, NULL);
148 }
149
150 static ssize_t alignment_proc_write(struct file *file, const char __user *buffer,
151 size_t count, loff_t *pos)
152 {
153 char mode;
154
155 if (count > 0) {
156 if (get_user(mode, buffer))
157 return -EFAULT;
158 if (mode >= '0' && mode <= '5')
159 ai_usermode = safe_usermode(mode - '0', true);
160 }
161 return count;
162 }
163
164 static const struct file_operations alignment_proc_fops = {
165 .open = alignment_proc_open,
166 .read = seq_read,
167 .llseek = seq_lseek,
168 .release = single_release,
169 .write = alignment_proc_write,
170 };
171 #endif /* CONFIG_PROC_FS */
172
173 union offset_union {
174 unsigned long un;
175 signed long sn;
176 };
177
178 #define TYPE_ERROR 0
179 #define TYPE_FAULT 1
180 #define TYPE_LDST 2
181 #define TYPE_DONE 3
182
183 #ifdef __ARMEB__
184 #define BE 1
185 #define FIRST_BYTE_16 "mov %1, %1, ror #8\n"
186 #define FIRST_BYTE_32 "mov %1, %1, ror #24\n"
187 #define NEXT_BYTE "ror #24"
188 #else
189 #define BE 0
190 #define FIRST_BYTE_16
191 #define FIRST_BYTE_32
192 #define NEXT_BYTE "lsr #8"
193 #endif
194
195 #define __get8_unaligned_check(ins,val,addr,err) \
196 __asm__( \
197 ARM( "1: "ins" %1, [%2], #1\n" ) \
198 THUMB( "1: "ins" %1, [%2]\n" ) \
199 THUMB( " add %2, %2, #1\n" ) \
200 "2:\n" \
201 " .pushsection .fixup,\"ax\"\n" \
202 " .align 2\n" \
203 "3: mov %0, #1\n" \
204 " b 2b\n" \
205 " .popsection\n" \
206 " .pushsection __ex_table,\"a\"\n" \
207 " .align 3\n" \
208 " .long 1b, 3b\n" \
209 " .popsection\n" \
210 : "=r" (err), "=&r" (val), "=r" (addr) \
211 : "0" (err), "2" (addr))
212
213 #define __get16_unaligned_check(ins,val,addr) \
214 do { \
215 unsigned int err = 0, v, a = addr; \
216 __get8_unaligned_check(ins,v,a,err); \
217 val = v << ((BE) ? 8 : 0); \
218 __get8_unaligned_check(ins,v,a,err); \
219 val |= v << ((BE) ? 0 : 8); \
220 if (err) \
221 goto fault; \
222 } while (0)
223
224 #define get16_unaligned_check(val,addr) \
225 __get16_unaligned_check("ldrb",val,addr)
226
227 #define get16t_unaligned_check(val,addr) \
228 __get16_unaligned_check("ldrbt",val,addr)
229
230 #define __get32_unaligned_check(ins,val,addr) \
231 do { \
232 unsigned int err = 0, v, a = addr; \
233 __get8_unaligned_check(ins,v,a,err); \
234 val = v << ((BE) ? 24 : 0); \
235 __get8_unaligned_check(ins,v,a,err); \
236 val |= v << ((BE) ? 16 : 8); \
237 __get8_unaligned_check(ins,v,a,err); \
238 val |= v << ((BE) ? 8 : 16); \
239 __get8_unaligned_check(ins,v,a,err); \
240 val |= v << ((BE) ? 0 : 24); \
241 if (err) \
242 goto fault; \
243 } while (0)
244
245 #define get32_unaligned_check(val,addr) \
246 __get32_unaligned_check("ldrb",val,addr)
247
248 #define get32t_unaligned_check(val,addr) \
249 __get32_unaligned_check("ldrbt",val,addr)
250
251 #define __put16_unaligned_check(ins,val,addr) \
252 do { \
253 unsigned int err = 0, v = val, a = addr; \
254 __asm__( FIRST_BYTE_16 \
255 ARM( "1: "ins" %1, [%2], #1\n" ) \
256 THUMB( "1: "ins" %1, [%2]\n" ) \
257 THUMB( " add %2, %2, #1\n" ) \
258 " mov %1, %1, "NEXT_BYTE"\n" \
259 "2: "ins" %1, [%2]\n" \
260 "3:\n" \
261 " .pushsection .fixup,\"ax\"\n" \
262 " .align 2\n" \
263 "4: mov %0, #1\n" \
264 " b 3b\n" \
265 " .popsection\n" \
266 " .pushsection __ex_table,\"a\"\n" \
267 " .align 3\n" \
268 " .long 1b, 4b\n" \
269 " .long 2b, 4b\n" \
270 " .popsection\n" \
271 : "=r" (err), "=&r" (v), "=&r" (a) \
272 : "0" (err), "1" (v), "2" (a)); \
273 if (err) \
274 goto fault; \
275 } while (0)
276
277 #define put16_unaligned_check(val,addr) \
278 __put16_unaligned_check("strb",val,addr)
279
280 #define put16t_unaligned_check(val,addr) \
281 __put16_unaligned_check("strbt",val,addr)
282
283 #define __put32_unaligned_check(ins,val,addr) \
284 do { \
285 unsigned int err = 0, v = val, a = addr; \
286 __asm__( FIRST_BYTE_32 \
287 ARM( "1: "ins" %1, [%2], #1\n" ) \
288 THUMB( "1: "ins" %1, [%2]\n" ) \
289 THUMB( " add %2, %2, #1\n" ) \
290 " mov %1, %1, "NEXT_BYTE"\n" \
291 ARM( "2: "ins" %1, [%2], #1\n" ) \
292 THUMB( "2: "ins" %1, [%2]\n" ) \
293 THUMB( " add %2, %2, #1\n" ) \
294 " mov %1, %1, "NEXT_BYTE"\n" \
295 ARM( "3: "ins" %1, [%2], #1\n" ) \
296 THUMB( "3: "ins" %1, [%2]\n" ) \
297 THUMB( " add %2, %2, #1\n" ) \
298 " mov %1, %1, "NEXT_BYTE"\n" \
299 "4: "ins" %1, [%2]\n" \
300 "5:\n" \
301 " .pushsection .fixup,\"ax\"\n" \
302 " .align 2\n" \
303 "6: mov %0, #1\n" \
304 " b 5b\n" \
305 " .popsection\n" \
306 " .pushsection __ex_table,\"a\"\n" \
307 " .align 3\n" \
308 " .long 1b, 6b\n" \
309 " .long 2b, 6b\n" \
310 " .long 3b, 6b\n" \
311 " .long 4b, 6b\n" \
312 " .popsection\n" \
313 : "=r" (err), "=&r" (v), "=&r" (a) \
314 : "0" (err), "1" (v), "2" (a)); \
315 if (err) \
316 goto fault; \
317 } while (0)
318
319 #define put32_unaligned_check(val,addr) \
320 __put32_unaligned_check("strb", val, addr)
321
322 #define put32t_unaligned_check(val,addr) \
323 __put32_unaligned_check("strbt", val, addr)
324
325 static void
326 do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
327 {
328 if (!LDST_U_BIT(instr))
329 offset.un = -offset.un;
330
331 if (!LDST_P_BIT(instr))
332 addr += offset.un;
333
334 if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
335 regs->uregs[RN_BITS(instr)] = addr;
336 }
337
338 static int
339 do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
340 {
341 unsigned int rd = RD_BITS(instr);
342
343 ai_half += 1;
344
345 if (user_mode(regs))
346 goto user;
347
348 if (LDST_L_BIT(instr)) {
349 unsigned long val;
350 get16_unaligned_check(val, addr);
351
352 /* signed half-word? */
353 if (instr & 0x40)
354 val = (signed long)((signed short) val);
355
356 regs->uregs[rd] = val;
357 } else
358 put16_unaligned_check(regs->uregs[rd], addr);
359
360 return TYPE_LDST;
361
362 user:
363 if (LDST_L_BIT(instr)) {
364 unsigned long val;
365 get16t_unaligned_check(val, addr);
366
367 /* signed half-word? */
368 if (instr & 0x40)
369 val = (signed long)((signed short) val);
370
371 regs->uregs[rd] = val;
372 } else
373 put16t_unaligned_check(regs->uregs[rd], addr);
374
375 return TYPE_LDST;
376
377 fault:
378 return TYPE_FAULT;
379 }
380
381 static int
382 do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
383 struct pt_regs *regs)
384 {
385 unsigned int rd = RD_BITS(instr);
386 unsigned int rd2;
387 int load;
388
389 if ((instr & 0xfe000000) == 0xe8000000) {
390 /* ARMv7 Thumb-2 32-bit LDRD/STRD */
391 rd2 = (instr >> 8) & 0xf;
392 load = !!(LDST_L_BIT(instr));
393 } else if (((rd & 1) == 1) || (rd == 14))
394 goto bad;
395 else {
396 load = ((instr & 0xf0) == 0xd0);
397 rd2 = rd + 1;
398 }
399
400 ai_dword += 1;
401
402 if (user_mode(regs))
403 goto user;
404
405 if (load) {
406 unsigned long val;
407 get32_unaligned_check(val, addr);
408 regs->uregs[rd] = val;
409 get32_unaligned_check(val, addr + 4);
410 regs->uregs[rd2] = val;
411 } else {
412 put32_unaligned_check(regs->uregs[rd], addr);
413 put32_unaligned_check(regs->uregs[rd2], addr + 4);
414 }
415
416 return TYPE_LDST;
417
418 user:
419 if (load) {
420 unsigned long val;
421 get32t_unaligned_check(val, addr);
422 regs->uregs[rd] = val;
423 get32t_unaligned_check(val, addr + 4);
424 regs->uregs[rd2] = val;
425 } else {
426 put32t_unaligned_check(regs->uregs[rd], addr);
427 put32t_unaligned_check(regs->uregs[rd2], addr + 4);
428 }
429
430 return TYPE_LDST;
431 bad:
432 return TYPE_ERROR;
433 fault:
434 return TYPE_FAULT;
435 }
436
437 static int
438 do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
439 {
440 unsigned int rd = RD_BITS(instr);
441
442 ai_word += 1;
443
444 if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
445 goto trans;
446
447 if (LDST_L_BIT(instr)) {
448 unsigned int val;
449 get32_unaligned_check(val, addr);
450 regs->uregs[rd] = val;
451 } else
452 put32_unaligned_check(regs->uregs[rd], addr);
453 return TYPE_LDST;
454
455 trans:
456 if (LDST_L_BIT(instr)) {
457 unsigned int val;
458 get32t_unaligned_check(val, addr);
459 regs->uregs[rd] = val;
460 } else
461 put32t_unaligned_check(regs->uregs[rd], addr);
462 return TYPE_LDST;
463
464 fault:
465 return TYPE_FAULT;
466 }
467
468 /*
469 * LDM/STM alignment handler.
470 *
471 * There are 4 variants of this instruction:
472 *
473 * B = rn pointer before instruction, A = rn pointer after instruction
474 * ------ increasing address ----->
475 * | | r0 | r1 | ... | rx | |
476 * PU = 01 B A
477 * PU = 11 B A
478 * PU = 00 A B
479 * PU = 10 A B
480 */
481 static int
482 do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
483 {
484 unsigned int rd, rn, correction, nr_regs, regbits;
485 unsigned long eaddr, newaddr;
486
487 if (LDM_S_BIT(instr))
488 goto bad;
489
490 correction = 4; /* processor implementation defined */
491 regs->ARM_pc += correction;
492
493 ai_multi += 1;
494
495 /* count the number of registers in the mask to be transferred */
496 nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
497
498 rn = RN_BITS(instr);
499 newaddr = eaddr = regs->uregs[rn];
500
501 if (!LDST_U_BIT(instr))
502 nr_regs = -nr_regs;
503 newaddr += nr_regs;
504 if (!LDST_U_BIT(instr))
505 eaddr = newaddr;
506
507 if (LDST_P_EQ_U(instr)) /* U = P */
508 eaddr += 4;
509
510 /*
511 * For alignment faults on the ARM922T/ARM920T the MMU makes
512 * the FSR (and hence addr) equal to the updated base address
513 * of the multiple access rather than the restored value.
514 * Switch this message off if we've got a ARM92[02], otherwise
515 * [ls]dm alignment faults are noisy!
516 */
517 #if !(defined CONFIG_CPU_ARM922T) && !(defined CONFIG_CPU_ARM920T)
518 /*
519 * This is a "hint" - we already have eaddr worked out by the
520 * processor for us.
521 */
522 if (addr != eaddr) {
523 printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
524 "addr = %08lx, eaddr = %08lx\n",
525 instruction_pointer(regs), instr, addr, eaddr);
526 show_regs(regs);
527 }
528 #endif
529
530 if (user_mode(regs)) {
531 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
532 regbits >>= 1, rd += 1)
533 if (regbits & 1) {
534 if (LDST_L_BIT(instr)) {
535 unsigned int val;
536 get32t_unaligned_check(val, eaddr);
537 regs->uregs[rd] = val;
538 } else
539 put32t_unaligned_check(regs->uregs[rd], eaddr);
540 eaddr += 4;
541 }
542 } else {
543 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
544 regbits >>= 1, rd += 1)
545 if (regbits & 1) {
546 if (LDST_L_BIT(instr)) {
547 unsigned int val;
548 get32_unaligned_check(val, eaddr);
549 regs->uregs[rd] = val;
550 } else
551 put32_unaligned_check(regs->uregs[rd], eaddr);
552 eaddr += 4;
553 }
554 }
555
556 if (LDST_W_BIT(instr))
557 regs->uregs[rn] = newaddr;
558 if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
559 regs->ARM_pc -= correction;
560 return TYPE_DONE;
561
562 fault:
563 regs->ARM_pc -= correction;
564 return TYPE_FAULT;
565
566 bad:
567 printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
568 return TYPE_ERROR;
569 }
570
571 /*
572 * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
573 * we can reuse ARM userland alignment fault fixups for Thumb.
574 *
575 * This implementation was initially based on the algorithm found in
576 * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
577 * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
578 *
579 * NOTES:
580 * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
581 * 2. If for some reason we're passed an non-ld/st Thumb instruction to
582 * decode, we return 0xdeadc0de. This should never happen under normal
583 * circumstances but if it does, we've got other problems to deal with
584 * elsewhere and we obviously can't fix those problems here.
585 */
586
587 static unsigned long
588 thumb2arm(u16 tinstr)
589 {
590 u32 L = (tinstr & (1<<11)) >> 11;
591
592 switch ((tinstr & 0xf800) >> 11) {
593 /* 6.5.1 Format 1: */
594 case 0x6000 >> 11: /* 7.1.52 STR(1) */
595 case 0x6800 >> 11: /* 7.1.26 LDR(1) */
596 case 0x7000 >> 11: /* 7.1.55 STRB(1) */
597 case 0x7800 >> 11: /* 7.1.30 LDRB(1) */
598 return 0xe5800000 |
599 ((tinstr & (1<<12)) << (22-12)) | /* fixup */
600 (L<<20) | /* L==1? */
601 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
602 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
603 ((tinstr & (31<<6)) >> /* immed_5 */
604 (6 - ((tinstr & (1<<12)) ? 0 : 2)));
605 case 0x8000 >> 11: /* 7.1.57 STRH(1) */
606 case 0x8800 >> 11: /* 7.1.32 LDRH(1) */
607 return 0xe1c000b0 |
608 (L<<20) | /* L==1? */
609 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
610 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
611 ((tinstr & (7<<6)) >> (6-1)) | /* immed_5[2:0] */
612 ((tinstr & (3<<9)) >> (9-8)); /* immed_5[4:3] */
613
614 /* 6.5.1 Format 2: */
615 case 0x5000 >> 11:
616 case 0x5800 >> 11:
617 {
618 static const u32 subset[8] = {
619 0xe7800000, /* 7.1.53 STR(2) */
620 0xe18000b0, /* 7.1.58 STRH(2) */
621 0xe7c00000, /* 7.1.56 STRB(2) */
622 0xe19000d0, /* 7.1.34 LDRSB */
623 0xe7900000, /* 7.1.27 LDR(2) */
624 0xe19000b0, /* 7.1.33 LDRH(2) */
625 0xe7d00000, /* 7.1.31 LDRB(2) */
626 0xe19000f0 /* 7.1.35 LDRSH */
627 };
628 return subset[(tinstr & (7<<9)) >> 9] |
629 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
630 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
631 ((tinstr & (7<<6)) >> (6-0)); /* Rm */
632 }
633
634 /* 6.5.1 Format 3: */
635 case 0x4800 >> 11: /* 7.1.28 LDR(3) */
636 /* NOTE: This case is not technically possible. We're
637 * loading 32-bit memory data via PC relative
638 * addressing mode. So we can and should eliminate
639 * this case. But I'll leave it here for now.
640 */
641 return 0xe59f0000 |
642 ((tinstr & (7<<8)) << (12-8)) | /* Rd */
643 ((tinstr & 255) << (2-0)); /* immed_8 */
644
645 /* 6.5.1 Format 4: */
646 case 0x9000 >> 11: /* 7.1.54 STR(3) */
647 case 0x9800 >> 11: /* 7.1.29 LDR(4) */
648 return 0xe58d0000 |
649 (L<<20) | /* L==1? */
650 ((tinstr & (7<<8)) << (12-8)) | /* Rd */
651 ((tinstr & 255) << 2); /* immed_8 */
652
653 /* 6.6.1 Format 1: */
654 case 0xc000 >> 11: /* 7.1.51 STMIA */
655 case 0xc800 >> 11: /* 7.1.25 LDMIA */
656 {
657 u32 Rn = (tinstr & (7<<8)) >> 8;
658 u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
659
660 return 0xe8800000 | W | (L<<20) | (Rn<<16) |
661 (tinstr&255);
662 }
663
664 /* 6.6.1 Format 2: */
665 case 0xb000 >> 11: /* 7.1.48 PUSH */
666 case 0xb800 >> 11: /* 7.1.47 POP */
667 if ((tinstr & (3 << 9)) == 0x0400) {
668 static const u32 subset[4] = {
669 0xe92d0000, /* STMDB sp!,{registers} */
670 0xe92d4000, /* STMDB sp!,{registers,lr} */
671 0xe8bd0000, /* LDMIA sp!,{registers} */
672 0xe8bd8000 /* LDMIA sp!,{registers,pc} */
673 };
674 return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
675 (tinstr & 255); /* register_list */
676 }
677 /* Else fall through for illegal instruction case */
678
679 default:
680 return BAD_INSTR;
681 }
682 }
683
684 /*
685 * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
686 * handlable by ARM alignment handler, also find the corresponding handler,
687 * so that we can reuse ARM userland alignment fault fixups for Thumb.
688 *
689 * @pinstr: original Thumb-2 instruction; returns new handlable instruction
690 * @regs: register context.
691 * @poffset: return offset from faulted addr for later writeback
692 *
693 * NOTES:
694 * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
695 * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
696 */
697 static void *
698 do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
699 union offset_union *poffset)
700 {
701 unsigned long instr = *pinstr;
702 u16 tinst1 = (instr >> 16) & 0xffff;
703 u16 tinst2 = instr & 0xffff;
704
705 switch (tinst1 & 0xffe0) {
706 /* A6.3.5 Load/Store multiple */
707 case 0xe880: /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
708 case 0xe8a0: /* ...above writeback version */
709 case 0xe900: /* STMDB/STMFD, LDMDB/LDMEA */
710 case 0xe920: /* ...above writeback version */
711 /* no need offset decision since handler calculates it */
712 return do_alignment_ldmstm;
713
714 case 0xf840: /* POP/PUSH T3 (single register) */
715 if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
716 u32 L = !!(LDST_L_BIT(instr));
717 const u32 subset[2] = {
718 0xe92d0000, /* STMDB sp!,{registers} */
719 0xe8bd0000, /* LDMIA sp!,{registers} */
720 };
721 *pinstr = subset[L] | (1<<RD_BITS(instr));
722 return do_alignment_ldmstm;
723 }
724 /* Else fall through for illegal instruction case */
725 break;
726
727 /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
728 case 0xe860:
729 case 0xe960:
730 case 0xe8e0:
731 case 0xe9e0:
732 poffset->un = (tinst2 & 0xff) << 2;
733 case 0xe940:
734 case 0xe9c0:
735 return do_alignment_ldrdstrd;
736
737 /*
738 * No need to handle load/store instructions up to word size
739 * since ARMv6 and later CPUs can perform unaligned accesses.
740 */
741 default:
742 break;
743 }
744 return NULL;
745 }
746
747 static int
748 do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
749 {
750 union offset_union uninitialized_var(offset);
751 unsigned long instr = 0, instrptr;
752 int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
753 unsigned int type;
754 unsigned int fault;
755 u16 tinstr = 0;
756 int isize = 4;
757 int thumb2_32b = 0;
758
759 if (interrupts_enabled(regs))
760 local_irq_enable();
761
762 instrptr = instruction_pointer(regs);
763
764 if (thumb_mode(regs)) {
765 u16 *ptr = (u16 *)(instrptr & ~1);
766 fault = probe_kernel_address(ptr, tinstr);
767 tinstr = __mem_to_opcode_thumb16(tinstr);
768 if (!fault) {
769 if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
770 IS_T32(tinstr)) {
771 /* Thumb-2 32-bit */
772 u16 tinst2 = 0;
773 fault = probe_kernel_address(ptr + 1, tinst2);
774 tinst2 = __mem_to_opcode_thumb16(tinst2);
775 instr = __opcode_thumb32_compose(tinstr, tinst2);
776 thumb2_32b = 1;
777 } else {
778 isize = 2;
779 instr = thumb2arm(tinstr);
780 }
781 }
782 } else {
783 fault = probe_kernel_address(instrptr, instr);
784 instr = __mem_to_opcode_arm(instr);
785 }
786
787 if (fault) {
788 type = TYPE_FAULT;
789 goto bad_or_fault;
790 }
791
792 if (user_mode(regs))
793 goto user;
794
795 ai_sys += 1;
796
797 fixup:
798
799 regs->ARM_pc += isize;
800
801 switch (CODING_BITS(instr)) {
802 case 0x00000000: /* 3.13.4 load/store instruction extensions */
803 if (LDSTHD_I_BIT(instr))
804 offset.un = (instr & 0xf00) >> 4 | (instr & 15);
805 else
806 offset.un = regs->uregs[RM_BITS(instr)];
807
808 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
809 (instr & 0x001000f0) == 0x001000f0) /* LDRSH */
810 handler = do_alignment_ldrhstrh;
811 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
812 (instr & 0x001000f0) == 0x000000f0) /* STRD */
813 handler = do_alignment_ldrdstrd;
814 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
815 goto swp;
816 else
817 goto bad;
818 break;
819
820 case 0x04000000: /* ldr or str immediate */
821 if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */
822 goto bad;
823 offset.un = OFFSET_BITS(instr);
824 handler = do_alignment_ldrstr;
825 break;
826
827 case 0x06000000: /* ldr or str register */
828 offset.un = regs->uregs[RM_BITS(instr)];
829
830 if (IS_SHIFT(instr)) {
831 unsigned int shiftval = SHIFT_BITS(instr);
832
833 switch(SHIFT_TYPE(instr)) {
834 case SHIFT_LSL:
835 offset.un <<= shiftval;
836 break;
837
838 case SHIFT_LSR:
839 offset.un >>= shiftval;
840 break;
841
842 case SHIFT_ASR:
843 offset.sn >>= shiftval;
844 break;
845
846 case SHIFT_RORRRX:
847 if (shiftval == 0) {
848 offset.un >>= 1;
849 if (regs->ARM_cpsr & PSR_C_BIT)
850 offset.un |= 1 << 31;
851 } else
852 offset.un = offset.un >> shiftval |
853 offset.un << (32 - shiftval);
854 break;
855 }
856 }
857 handler = do_alignment_ldrstr;
858 break;
859
860 case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */
861 if (thumb2_32b) {
862 offset.un = 0;
863 handler = do_alignment_t32_to_handler(&instr, regs, &offset);
864 } else {
865 offset.un = 0;
866 handler = do_alignment_ldmstm;
867 }
868 break;
869
870 default:
871 goto bad;
872 }
873
874 if (!handler)
875 goto bad;
876 type = handler(addr, instr, regs);
877
878 if (type == TYPE_ERROR || type == TYPE_FAULT) {
879 regs->ARM_pc -= isize;
880 goto bad_or_fault;
881 }
882
883 if (type == TYPE_LDST)
884 do_alignment_finish_ldst(addr, instr, regs, offset);
885
886 return 0;
887
888 bad_or_fault:
889 if (type == TYPE_ERROR)
890 goto bad;
891 /*
892 * We got a fault - fix it up, or die.
893 */
894 do_bad_area(addr, fsr, regs);
895 return 0;
896
897 swp:
898 printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
899
900 bad:
901 /*
902 * Oops, we didn't handle the instruction.
903 */
904 printk(KERN_ERR "Alignment trap: not handling instruction "
905 "%0*lx at [<%08lx>]\n",
906 isize << 1,
907 isize == 2 ? tinstr : instr, instrptr);
908 ai_skipped += 1;
909 return 1;
910
911 user:
912 ai_user += 1;
913
914 if (ai_usermode & UM_WARN)
915 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
916 "Address=0x%08lx FSR 0x%03x\n", current->comm,
917 task_pid_nr(current), instrptr,
918 isize << 1,
919 isize == 2 ? tinstr : instr,
920 addr, fsr);
921
922 if (ai_usermode & UM_FIXUP)
923 goto fixup;
924
925 if (ai_usermode & UM_SIGNAL) {
926 siginfo_t si;
927
928 si.si_signo = SIGBUS;
929 si.si_errno = 0;
930 si.si_code = BUS_ADRALN;
931 si.si_addr = (void __user *)addr;
932
933 force_sig_info(si.si_signo, &si, current);
934 } else {
935 /*
936 * We're about to disable the alignment trap and return to
937 * user space. But if an interrupt occurs before actually
938 * reaching user space, then the IRQ vector entry code will
939 * notice that we were still in kernel space and therefore
940 * the alignment trap won't be re-enabled in that case as it
941 * is presumed to be always on from kernel space.
942 * Let's prevent that race by disabling interrupts here (they
943 * are disabled on the way back to user space anyway in
944 * entry-common.S) and disable the alignment trap only if
945 * there is no work pending for this thread.
946 */
947 raw_local_irq_disable();
948 if (!(current_thread_info()->flags & _TIF_WORK_MASK))
949 set_cr(cr_no_alignment);
950 }
951
952 return 0;
953 }
954
955 /*
956 * This needs to be done after sysctl_init, otherwise sys/ will be
957 * overwritten. Actually, this shouldn't be in sys/ at all since
958 * it isn't a sysctl, and it doesn't contain sysctl information.
959 * We now locate it in /proc/cpu/alignment instead.
960 */
961 static int __init alignment_init(void)
962 {
963 #ifdef CONFIG_PROC_FS
964 struct proc_dir_entry *res;
965
966 res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL,
967 &alignment_proc_fops);
968 if (!res)
969 return -ENOMEM;
970 #endif
971
972 #ifdef CONFIG_CPU_CP15
973 if (cpu_is_v6_unaligned()) {
974 cr_alignment &= ~CR_A;
975 cr_no_alignment &= ~CR_A;
976 set_cr(cr_alignment);
977 ai_usermode = safe_usermode(ai_usermode, false);
978 }
979 #endif
980
981 hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
982 "alignment exception");
983
984 /*
985 * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
986 * fault, not as alignment error.
987 *
988 * TODO: handle ARMv6K properly. Runtime check for 'K' extension is
989 * needed.
990 */
991 if (cpu_architecture() <= CPU_ARCH_ARMv6) {
992 hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
993 "alignment exception");
994 }
995
996 return 0;
997 }
998
999 fs_initcall(alignment_init);
Linux for the MCST Elbrus 2000 architecture