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Lynx framebuffers multidomain implementation.
[linux/elbrus.git] / drivers / ata / libahci.c
blobc0d9dd68c1479999a13cd946f1511d7f21e6c1c1
1 /*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47 #include "ahci.h"
48 #include "libata.h"
49
50 static int ahci_skip_host_reset;
51 int ahci_ignore_sss;
52 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53
54 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
55 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56
57 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
58 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59
60 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 unsigned hints);
62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
72 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74 static int ahci_port_start(struct ata_port *ap);
75 static void ahci_port_stop(struct ata_port *ap);
76 static void ahci_qc_prep(struct ata_queued_cmd *qc);
77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78 static void ahci_freeze(struct ata_port *ap);
79 static void ahci_thaw(struct ata_port *ap);
80 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
81 static void ahci_enable_fbs(struct ata_port *ap);
82 static void ahci_disable_fbs(struct ata_port *ap);
83 static void ahci_pmp_attach(struct ata_port *ap);
84 static void ahci_pmp_detach(struct ata_port *ap);
85 static int ahci_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static void ahci_postreset(struct ata_link *link, unsigned int *class);
92 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
93 static void ahci_dev_config(struct ata_device *dev);
94 #ifdef CONFIG_PM
95 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96 #endif
97 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98 static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100 static void ahci_init_sw_activity(struct ata_link *link);
101
102 static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104 static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106 static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108 static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
110 static ssize_t ahci_read_em_buffer(struct device *dev,
111 struct device_attribute *attr, char *buf);
112 static ssize_t ahci_store_em_buffer(struct device *dev,
113 struct device_attribute *attr,
114 const char *buf, size_t size);
115 static ssize_t ahci_show_em_supported(struct device *dev,
116 struct device_attribute *attr, char *buf);
117
118 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
119 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
120 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
121 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
122 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
123 ahci_read_em_buffer, ahci_store_em_buffer);
124 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
125
126 struct device_attribute *ahci_shost_attrs[] = {
127 &dev_attr_link_power_management_policy,
128 &dev_attr_em_message_type,
129 &dev_attr_em_message,
130 &dev_attr_ahci_host_caps,
131 &dev_attr_ahci_host_cap2,
132 &dev_attr_ahci_host_version,
133 &dev_attr_ahci_port_cmd,
134 &dev_attr_em_buffer,
135 &dev_attr_em_message_supported,
136 NULL
137 };
138 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
139
140 struct device_attribute *ahci_sdev_attrs[] = {
141 &dev_attr_sw_activity,
142 &dev_attr_unload_heads,
143 NULL
144 };
145 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
146
147 struct ata_port_operations ahci_ops = {
148 .inherits = &sata_pmp_port_ops,
149
150 .qc_defer = ahci_pmp_qc_defer,
151 .qc_prep = ahci_qc_prep,
152 .qc_issue = ahci_qc_issue,
153 .qc_fill_rtf = ahci_qc_fill_rtf,
154
155 .freeze = ahci_freeze,
156 .thaw = ahci_thaw,
157 .softreset = ahci_softreset,
158 .hardreset = ahci_hardreset,
159 .postreset = ahci_postreset,
160 .pmp_softreset = ahci_softreset,
161 .error_handler = ahci_error_handler,
162 .post_internal_cmd = ahci_post_internal_cmd,
163 .dev_config = ahci_dev_config,
164
165 .scr_read = ahci_scr_read,
166 .scr_write = ahci_scr_write,
167 .pmp_attach = ahci_pmp_attach,
168 .pmp_detach = ahci_pmp_detach,
169
170 .set_lpm = ahci_set_lpm,
171 .em_show = ahci_led_show,
172 .em_store = ahci_led_store,
173 .sw_activity_show = ahci_activity_show,
174 .sw_activity_store = ahci_activity_store,
175 .transmit_led_message = ahci_transmit_led_message,
176 #ifdef CONFIG_PM
177 .port_suspend = ahci_port_suspend,
178 .port_resume = ahci_port_resume,
179 #endif
180 .port_start = ahci_port_start,
181 .port_stop = ahci_port_stop,
182 };
183 EXPORT_SYMBOL_GPL(ahci_ops);
184
185 struct ata_port_operations ahci_pmp_retry_srst_ops = {
186 .inherits = &ahci_ops,
187 .softreset = ahci_pmp_retry_softreset,
188 };
189 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
190
191 static bool ahci_em_messages __read_mostly = true;
192 EXPORT_SYMBOL_GPL(ahci_em_messages);
193 module_param(ahci_em_messages, bool, 0444);
194 /* add other LED protocol types when they become supported */
195 MODULE_PARM_DESC(ahci_em_messages,
196 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
197
198 /* device sleep idle timeout in ms */
199 static int devslp_idle_timeout __read_mostly = 1000;
200 module_param(devslp_idle_timeout, int, 0644);
201 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
202
203 static void ahci_enable_ahci(void __iomem *mmio)
204 {
205 int i;
206 u32 tmp;
207
208 /* turn on AHCI_EN */
209 tmp = readl(mmio + HOST_CTL);
210 if (tmp & HOST_AHCI_EN)
211 return;
212
213 /* Some controllers need AHCI_EN to be written multiple times.
214 * Try a few times before giving up.
215 */
216 for (i = 0; i < 5; i++) {
217 tmp |= HOST_AHCI_EN;
218 writel(tmp, mmio + HOST_CTL);
219 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
220 if (tmp & HOST_AHCI_EN)
221 return;
222 msleep(10);
223 }
224
225 WARN_ON(1);
226 }
227
228 static ssize_t ahci_show_host_caps(struct device *dev,
229 struct device_attribute *attr, char *buf)
230 {
231 struct Scsi_Host *shost = class_to_shost(dev);
232 struct ata_port *ap = ata_shost_to_port(shost);
233 struct ahci_host_priv *hpriv = ap->host->private_data;
234
235 return sprintf(buf, "%x\n", hpriv->cap);
236 }
237
238 static ssize_t ahci_show_host_cap2(struct device *dev,
239 struct device_attribute *attr, char *buf)
240 {
241 struct Scsi_Host *shost = class_to_shost(dev);
242 struct ata_port *ap = ata_shost_to_port(shost);
243 struct ahci_host_priv *hpriv = ap->host->private_data;
244
245 return sprintf(buf, "%x\n", hpriv->cap2);
246 }
247
248 static ssize_t ahci_show_host_version(struct device *dev,
249 struct device_attribute *attr, char *buf)
250 {
251 struct Scsi_Host *shost = class_to_shost(dev);
252 struct ata_port *ap = ata_shost_to_port(shost);
253 struct ahci_host_priv *hpriv = ap->host->private_data;
254 void __iomem *mmio = hpriv->mmio;
255
256 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
257 }
258
259 static ssize_t ahci_show_port_cmd(struct device *dev,
260 struct device_attribute *attr, char *buf)
261 {
262 struct Scsi_Host *shost = class_to_shost(dev);
263 struct ata_port *ap = ata_shost_to_port(shost);
264 void __iomem *port_mmio = ahci_port_base(ap);
265
266 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
267 }
268
269 static ssize_t ahci_read_em_buffer(struct device *dev,
270 struct device_attribute *attr, char *buf)
271 {
272 struct Scsi_Host *shost = class_to_shost(dev);
273 struct ata_port *ap = ata_shost_to_port(shost);
274 struct ahci_host_priv *hpriv = ap->host->private_data;
275 void __iomem *mmio = hpriv->mmio;
276 void __iomem *em_mmio = mmio + hpriv->em_loc;
277 u32 em_ctl, msg;
278 unsigned long flags;
279 size_t count;
280 int i;
281
282 spin_lock_irqsave(ap->lock, flags);
283
284 em_ctl = readl(mmio + HOST_EM_CTL);
285 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
286 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
287 spin_unlock_irqrestore(ap->lock, flags);
288 return -EINVAL;
289 }
290
291 if (!(em_ctl & EM_CTL_MR)) {
292 spin_unlock_irqrestore(ap->lock, flags);
293 return -EAGAIN;
294 }
295
296 if (!(em_ctl & EM_CTL_SMB))
297 em_mmio += hpriv->em_buf_sz;
298
299 count = hpriv->em_buf_sz;
300
301 /* the count should not be larger than PAGE_SIZE */
302 if (count > PAGE_SIZE) {
303 if (printk_ratelimit())
304 ata_port_warn(ap,
305 "EM read buffer size too large: "
306 "buffer size %u, page size %lu\n",
307 hpriv->em_buf_sz, PAGE_SIZE);
308 count = PAGE_SIZE;
309 }
310
311 for (i = 0; i < count; i += 4) {
312 msg = readl(em_mmio + i);
313 buf[i] = msg & 0xff;
314 buf[i + 1] = (msg >> 8) & 0xff;
315 buf[i + 2] = (msg >> 16) & 0xff;
316 buf[i + 3] = (msg >> 24) & 0xff;
317 }
318
319 spin_unlock_irqrestore(ap->lock, flags);
320
321 return i;
322 }
323
324 static ssize_t ahci_store_em_buffer(struct device *dev,
325 struct device_attribute *attr,
326 const char *buf, size_t size)
327 {
328 struct Scsi_Host *shost = class_to_shost(dev);
329 struct ata_port *ap = ata_shost_to_port(shost);
330 struct ahci_host_priv *hpriv = ap->host->private_data;
331 void __iomem *mmio = hpriv->mmio;
332 void __iomem *em_mmio = mmio + hpriv->em_loc;
333 const unsigned char *msg_buf = buf;
334 u32 em_ctl, msg;
335 unsigned long flags;
336 int i;
337
338 /* check size validity */
339 if (!(ap->flags & ATA_FLAG_EM) ||
340 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
341 size % 4 || size > hpriv->em_buf_sz)
342 return -EINVAL;
343
344 spin_lock_irqsave(ap->lock, flags);
345
346 em_ctl = readl(mmio + HOST_EM_CTL);
347 if (em_ctl & EM_CTL_TM) {
348 spin_unlock_irqrestore(ap->lock, flags);
349 return -EBUSY;
350 }
351
352 for (i = 0; i < size; i += 4) {
353 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
354 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
355 writel(msg, em_mmio + i);
356 }
357
358 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
359
360 spin_unlock_irqrestore(ap->lock, flags);
361
362 return size;
363 }
364
365 static ssize_t ahci_show_em_supported(struct device *dev,
366 struct device_attribute *attr, char *buf)
367 {
368 struct Scsi_Host *shost = class_to_shost(dev);
369 struct ata_port *ap = ata_shost_to_port(shost);
370 struct ahci_host_priv *hpriv = ap->host->private_data;
371 void __iomem *mmio = hpriv->mmio;
372 u32 em_ctl;
373
374 em_ctl = readl(mmio + HOST_EM_CTL);
375
376 return sprintf(buf, "%s%s%s%s\n",
377 em_ctl & EM_CTL_LED ? "led " : "",
378 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
379 em_ctl & EM_CTL_SES ? "ses-2 " : "",
380 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
381 }
382
383 /**
384 * ahci_save_initial_config - Save and fixup initial config values
385 * @dev: target AHCI device
386 * @hpriv: host private area to store config values
387 * @force_port_map: force port map to a specified value
388 * @mask_port_map: mask out particular bits from port map
389 *
390 * Some registers containing configuration info might be setup by
391 * BIOS and might be cleared on reset. This function saves the
392 * initial values of those registers into @hpriv such that they
393 * can be restored after controller reset.
394 *
395 * If inconsistent, config values are fixed up by this function.
396 *
397 * LOCKING:
398 * None.
399 */
400 void ahci_save_initial_config(struct device *dev,
401 struct ahci_host_priv *hpriv,
402 unsigned int force_port_map,
403 unsigned int mask_port_map)
404 {
405 void __iomem *mmio = hpriv->mmio;
406 u32 cap, cap2, vers, port_map;
407 int i;
408
409 /* make sure AHCI mode is enabled before accessing CAP */
410 ahci_enable_ahci(mmio);
411
412 /* Values prefixed with saved_ are written back to host after
413 * reset. Values without are used for driver operation.
414 */
415 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
416 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
417
418 /* CAP2 register is only defined for AHCI 1.2 and later */
419 vers = readl(mmio + HOST_VERSION);
420 if ((vers >> 16) > 1 ||
421 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
422 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
423 else
424 hpriv->saved_cap2 = cap2 = 0;
425
426 /* some chips have errata preventing 64bit use */
427 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
428 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
429 cap &= ~HOST_CAP_64;
430 }
431
432 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
433 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
434 cap &= ~HOST_CAP_NCQ;
435 }
436
437 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
438 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
439 cap |= HOST_CAP_NCQ;
440 }
441
442 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
443 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
444 cap &= ~HOST_CAP_PMP;
445 }
446
447 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
448 dev_info(dev,
449 "controller can't do SNTF, turning off CAP_SNTF\n");
450 cap &= ~HOST_CAP_SNTF;
451 }
452
453 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
454 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
455 cap |= HOST_CAP_FBS;
456 }
457
458 if (force_port_map && port_map != force_port_map) {
459 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
460 port_map, force_port_map);
461 port_map = force_port_map;
462 }
463
464 if (mask_port_map) {
465 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
466 port_map,
467 port_map & mask_port_map);
468 port_map &= mask_port_map;
469 }
470
471 /* cross check port_map and cap.n_ports */
472 if (port_map) {
473 int map_ports = 0;
474
475 for (i = 0; i < AHCI_MAX_PORTS; i++)
476 if (port_map & (1 << i))
477 map_ports++;
478
479 /* If PI has more ports than n_ports, whine, clear
480 * port_map and let it be generated from n_ports.
481 */
482 if (map_ports > ahci_nr_ports(cap)) {
483 dev_warn(dev,
484 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
485 port_map, ahci_nr_ports(cap));
486 port_map = 0;
487 }
488 }
489
490 /* fabricate port_map from cap.nr_ports */
491 if (!port_map) {
492 port_map = (1 << ahci_nr_ports(cap)) - 1;
493 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
494
495 /* write the fixed up value to the PI register */
496 hpriv->saved_port_map = port_map;
497 }
498
499 /* record values to use during operation */
500 hpriv->cap = cap;
501 hpriv->cap2 = cap2;
502 hpriv->port_map = port_map;
503 }
504 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
505
506 /**
507 * ahci_restore_initial_config - Restore initial config
508 * @host: target ATA host
509 *
510 * Restore initial config stored by ahci_save_initial_config().
511 *
512 * LOCKING:
513 * None.
514 */
515 static void ahci_restore_initial_config(struct ata_host *host)
516 {
517 struct ahci_host_priv *hpriv = host->private_data;
518 void __iomem *mmio = hpriv->mmio;
519
520 writel(hpriv->saved_cap, mmio + HOST_CAP);
521 if (hpriv->saved_cap2)
522 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
523 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
524 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
525 }
526
527 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
528 {
529 static const int offset[] = {
530 [SCR_STATUS] = PORT_SCR_STAT,
531 [SCR_CONTROL] = PORT_SCR_CTL,
532 [SCR_ERROR] = PORT_SCR_ERR,
533 [SCR_ACTIVE] = PORT_SCR_ACT,
534 [SCR_NOTIFICATION] = PORT_SCR_NTF,
535 };
536 struct ahci_host_priv *hpriv = ap->host->private_data;
537
538 if (sc_reg < ARRAY_SIZE(offset) &&
539 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
540 return offset[sc_reg];
541 return 0;
542 }
543
544 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
545 {
546 void __iomem *port_mmio = ahci_port_base(link->ap);
547 int offset = ahci_scr_offset(link->ap, sc_reg);
548
549 if (offset) {
550 *val = readl(port_mmio + offset);
551 return 0;
552 }
553 return -EINVAL;
554 }
555
556 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
557 {
558 void __iomem *port_mmio = ahci_port_base(link->ap);
559 int offset = ahci_scr_offset(link->ap, sc_reg);
560
561 if (offset) {
562 writel(val, port_mmio + offset);
563 return 0;
564 }
565 return -EINVAL;
566 }
567
568 void ahci_start_engine(struct ata_port *ap)
569 {
570 void __iomem *port_mmio = ahci_port_base(ap);
571 u32 tmp;
572
573 /* start DMA */
574 tmp = readl(port_mmio + PORT_CMD);
575 tmp |= PORT_CMD_START;
576 writel(tmp, port_mmio + PORT_CMD);
577 readl(port_mmio + PORT_CMD); /* flush */
578 }
579 EXPORT_SYMBOL_GPL(ahci_start_engine);
580
581 int ahci_stop_engine(struct ata_port *ap)
582 {
583 void __iomem *port_mmio = ahci_port_base(ap);
584 u32 tmp;
585
586 tmp = readl(port_mmio + PORT_CMD);
587
588 /* check if the HBA is idle */
589 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
590 return 0;
591
592 /* setting HBA to idle */
593 tmp &= ~PORT_CMD_START;
594 writel(tmp, port_mmio + PORT_CMD);
595
596 /* wait for engine to stop. This could be as long as 500 msec */
597 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
598 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
599 if (tmp & PORT_CMD_LIST_ON)
600 return -EIO;
601
602 return 0;
603 }
604 EXPORT_SYMBOL_GPL(ahci_stop_engine);
605
606 static void ahci_start_fis_rx(struct ata_port *ap)
607 {
608 void __iomem *port_mmio = ahci_port_base(ap);
609 struct ahci_host_priv *hpriv = ap->host->private_data;
610 struct ahci_port_priv *pp = ap->private_data;
611 u32 tmp;
612
613 /* set FIS registers */
614 if (hpriv->cap & HOST_CAP_64)
615 writel((pp->cmd_slot_dma >> 16) >> 16,
616 port_mmio + PORT_LST_ADDR_HI);
617 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
618
619 if (hpriv->cap & HOST_CAP_64)
620 writel((pp->rx_fis_dma >> 16) >> 16,
621 port_mmio + PORT_FIS_ADDR_HI);
622 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
623
624 /* enable FIS reception */
625 tmp = readl(port_mmio + PORT_CMD);
626 tmp |= PORT_CMD_FIS_RX;
627 writel(tmp, port_mmio + PORT_CMD);
628
629 /* flush */
630 readl(port_mmio + PORT_CMD);
631 }
632
633 static int ahci_stop_fis_rx(struct ata_port *ap)
634 {
635 void __iomem *port_mmio = ahci_port_base(ap);
636 u32 tmp;
637
638 /* disable FIS reception */
639 tmp = readl(port_mmio + PORT_CMD);
640 tmp &= ~PORT_CMD_FIS_RX;
641 writel(tmp, port_mmio + PORT_CMD);
642
643 /* wait for completion, spec says 500ms, give it 1000 */
644 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
645 PORT_CMD_FIS_ON, 10, 1000);
646 if (tmp & PORT_CMD_FIS_ON)
647 return -EBUSY;
648
649 return 0;
650 }
651
652 static void ahci_power_up(struct ata_port *ap)
653 {
654 struct ahci_host_priv *hpriv = ap->host->private_data;
655 void __iomem *port_mmio = ahci_port_base(ap);
656 u32 cmd;
657
658 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
659
660 /* spin up device */
661 if (hpriv->cap & HOST_CAP_SSS) {
662 cmd |= PORT_CMD_SPIN_UP;
663 writel(cmd, port_mmio + PORT_CMD);
664 }
665
666 /* wake up link */
667 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
668 }
669
670 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
671 unsigned int hints)
672 {
673 struct ata_port *ap = link->ap;
674 struct ahci_host_priv *hpriv = ap->host->private_data;
675 struct ahci_port_priv *pp = ap->private_data;
676 void __iomem *port_mmio = ahci_port_base(ap);
677
678 if (policy != ATA_LPM_MAX_POWER) {
679 /*
680 * Disable interrupts on Phy Ready. This keeps us from
681 * getting woken up due to spurious phy ready
682 * interrupts.
683 */
684 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
685 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
686
687 sata_link_scr_lpm(link, policy, false);
688 }
689
690 if (hpriv->cap & HOST_CAP_ALPM) {
691 u32 cmd = readl(port_mmio + PORT_CMD);
692
693 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
694 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
695 cmd |= PORT_CMD_ICC_ACTIVE;
696
697 writel(cmd, port_mmio + PORT_CMD);
698 readl(port_mmio + PORT_CMD);
699
700 /* wait 10ms to be sure we've come out of LPM state */
701 ata_msleep(ap, 10);
702 } else {
703 cmd |= PORT_CMD_ALPE;
704 if (policy == ATA_LPM_MIN_POWER)
705 cmd |= PORT_CMD_ASP;
706
707 /* write out new cmd value */
708 writel(cmd, port_mmio + PORT_CMD);
709 }
710 }
711
712 /* set aggressive device sleep */
713 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
714 (hpriv->cap2 & HOST_CAP2_SADM) &&
715 (link->device->flags & ATA_DFLAG_DEVSLP)) {
716 if (policy == ATA_LPM_MIN_POWER)
717 ahci_set_aggressive_devslp(ap, true);
718 else
719 ahci_set_aggressive_devslp(ap, false);
720 }
721
722 if (policy == ATA_LPM_MAX_POWER) {
723 sata_link_scr_lpm(link, policy, false);
724
725 /* turn PHYRDY IRQ back on */
726 pp->intr_mask |= PORT_IRQ_PHYRDY;
727 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
728 }
729
730 return 0;
731 }
732
733 #ifdef CONFIG_PM
734 static void ahci_power_down(struct ata_port *ap)
735 {
736 struct ahci_host_priv *hpriv = ap->host->private_data;
737 void __iomem *port_mmio = ahci_port_base(ap);
738 u32 cmd, scontrol;
739
740 if (!(hpriv->cap & HOST_CAP_SSS))
741 return;
742
743 /* put device into listen mode, first set PxSCTL.DET to 0 */
744 scontrol = readl(port_mmio + PORT_SCR_CTL);
745 scontrol &= ~0xf;
746 writel(scontrol, port_mmio + PORT_SCR_CTL);
747
748 /* then set PxCMD.SUD to 0 */
749 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
750 cmd &= ~PORT_CMD_SPIN_UP;
751 writel(cmd, port_mmio + PORT_CMD);
752 }
753 #endif
754
755 static void ahci_start_port(struct ata_port *ap)
756 {
757 struct ahci_host_priv *hpriv = ap->host->private_data;
758 struct ahci_port_priv *pp = ap->private_data;
759 struct ata_link *link;
760 struct ahci_em_priv *emp;
761 ssize_t rc;
762 int i;
763
764 /* enable FIS reception */
765 ahci_start_fis_rx(ap);
766
767 /* enable DMA */
768 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
769 ahci_start_engine(ap);
770
771 /* turn on LEDs */
772 if (ap->flags & ATA_FLAG_EM) {
773 ata_for_each_link(link, ap, EDGE) {
774 emp = &pp->em_priv[link->pmp];
775
776 /* EM Transmit bit maybe busy during init */
777 for (i = 0; i < EM_MAX_RETRY; i++) {
778 rc = ap->ops->transmit_led_message(ap,
779 emp->led_state,
780 4);
781 /*
782 * If busy, give a breather but do not
783 * release EH ownership by using msleep()
784 * instead of ata_msleep(). EM Transmit
785 * bit is busy for the whole host and
786 * releasing ownership will cause other
787 * ports to fail the same way.
788 */
789 if (rc == -EBUSY)
790 msleep(1);
791 else
792 break;
793 }
794 }
795 }
796
797 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
798 ata_for_each_link(link, ap, EDGE)
799 ahci_init_sw_activity(link);
800
801 }
802
803 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
804 {
805 int rc;
806
807 /* disable DMA */
808 rc = ahci_stop_engine(ap);
809 if (rc) {
810 *emsg = "failed to stop engine";
811 return rc;
812 }
813
814 /* disable FIS reception */
815 rc = ahci_stop_fis_rx(ap);
816 if (rc) {
817 *emsg = "failed stop FIS RX";
818 return rc;
819 }
820
821 return 0;
822 }
823
824 int ahci_reset_controller(struct ata_host *host)
825 {
826 struct ahci_host_priv *hpriv = host->private_data;
827 void __iomem *mmio = hpriv->mmio;
828 u32 tmp;
829
830 /* we must be in AHCI mode, before using anything
831 * AHCI-specific, such as HOST_RESET.
832 */
833 ahci_enable_ahci(mmio);
834
835 /* global controller reset */
836 if (!ahci_skip_host_reset) {
837 tmp = readl(mmio + HOST_CTL);
838 if ((tmp & HOST_RESET) == 0) {
839 writel(tmp | HOST_RESET, mmio + HOST_CTL);
840 readl(mmio + HOST_CTL); /* flush */
841 }
842
843 /*
844 * to perform host reset, OS should set HOST_RESET
845 * and poll until this bit is read to be "0".
846 * reset must complete within 1 second, or
847 * the hardware should be considered fried.
848 */
849 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
850 HOST_RESET, 10, 1000);
851
852 if (tmp & HOST_RESET) {
853 dev_err(host->dev, "controller reset failed (0x%x)\n",
854 tmp);
855 return -EIO;
856 }
857
858 /* turn on AHCI mode */
859 ahci_enable_ahci(mmio);
860
861 /* Some registers might be cleared on reset. Restore
862 * initial values.
863 */
864 ahci_restore_initial_config(host);
865 } else
866 dev_info(host->dev, "skipping global host reset\n");
867
868 return 0;
869 }
870 EXPORT_SYMBOL_GPL(ahci_reset_controller);
871
872 static void ahci_sw_activity(struct ata_link *link)
873 {
874 struct ata_port *ap = link->ap;
875 struct ahci_port_priv *pp = ap->private_data;
876 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
877
878 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
879 return;
880
881 emp->activity++;
882 if (!timer_pending(&emp->timer))
883 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
884 }
885
886 static void ahci_sw_activity_blink(unsigned long arg)
887 {
888 struct ata_link *link = (struct ata_link *)arg;
889 struct ata_port *ap = link->ap;
890 struct ahci_port_priv *pp = ap->private_data;
891 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
892 unsigned long led_message = emp->led_state;
893 u32 activity_led_state;
894 unsigned long flags;
895
896 led_message &= EM_MSG_LED_VALUE;
897 led_message |= ap->port_no | (link->pmp << 8);
898
899 /* check to see if we've had activity. If so,
900 * toggle state of LED and reset timer. If not,
901 * turn LED to desired idle state.
902 */
903 spin_lock_irqsave(ap->lock, flags);
904 if (emp->saved_activity != emp->activity) {
905 emp->saved_activity = emp->activity;
906 /* get the current LED state */
907 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
908
909 if (activity_led_state)
910 activity_led_state = 0;
911 else
912 activity_led_state = 1;
913
914 /* clear old state */
915 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
916
917 /* toggle state */
918 led_message |= (activity_led_state << 16);
919 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
920 } else {
921 /* switch to idle */
922 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
923 if (emp->blink_policy == BLINK_OFF)
924 led_message |= (1 << 16);
925 }
926 spin_unlock_irqrestore(ap->lock, flags);
927 ap->ops->transmit_led_message(ap, led_message, 4);
928 }
929
930 static void ahci_init_sw_activity(struct ata_link *link)
931 {
932 struct ata_port *ap = link->ap;
933 struct ahci_port_priv *pp = ap->private_data;
934 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
935
936 /* init activity stats, setup timer */
937 emp->saved_activity = emp->activity = 0;
938 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
939
940 /* check our blink policy and set flag for link if it's enabled */
941 if (emp->blink_policy)
942 link->flags |= ATA_LFLAG_SW_ACTIVITY;
943 }
944
945 int ahci_reset_em(struct ata_host *host)
946 {
947 struct ahci_host_priv *hpriv = host->private_data;
948 void __iomem *mmio = hpriv->mmio;
949 u32 em_ctl;
950
951 em_ctl = readl(mmio + HOST_EM_CTL);
952 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
953 return -EINVAL;
954
955 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
956 return 0;
957 }
958 EXPORT_SYMBOL_GPL(ahci_reset_em);
959
960 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
961 ssize_t size)
962 {
963 struct ahci_host_priv *hpriv = ap->host->private_data;
964 struct ahci_port_priv *pp = ap->private_data;
965 void __iomem *mmio = hpriv->mmio;
966 u32 em_ctl;
967 u32 message[] = {0, 0};
968 unsigned long flags;
969 int pmp;
970 struct ahci_em_priv *emp;
971
972 /* get the slot number from the message */
973 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
974 if (pmp < EM_MAX_SLOTS)
975 emp = &pp->em_priv[pmp];
976 else
977 return -EINVAL;
978
979 spin_lock_irqsave(ap->lock, flags);
980
981 /*
982 * if we are still busy transmitting a previous message,
983 * do not allow
984 */
985 em_ctl = readl(mmio + HOST_EM_CTL);
986 if (em_ctl & EM_CTL_TM) {
987 spin_unlock_irqrestore(ap->lock, flags);
988 return -EBUSY;
989 }
990
991 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
992 /*
993 * create message header - this is all zero except for
994 * the message size, which is 4 bytes.
995 */
996 message[0] |= (4 << 8);
997
998 /* ignore 0:4 of byte zero, fill in port info yourself */
999 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1000
1001 /* write message to EM_LOC */
1002 writel(message[0], mmio + hpriv->em_loc);
1003 writel(message[1], mmio + hpriv->em_loc+4);
1004
1005 /*
1006 * tell hardware to transmit the message
1007 */
1008 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1009 }
1010
1011 /* save off new led state for port/slot */
1012 emp->led_state = state;
1013
1014 spin_unlock_irqrestore(ap->lock, flags);
1015 return size;
1016 }
1017
1018 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1019 {
1020 struct ahci_port_priv *pp = ap->private_data;
1021 struct ata_link *link;
1022 struct ahci_em_priv *emp;
1023 int rc = 0;
1024
1025 ata_for_each_link(link, ap, EDGE) {
1026 emp = &pp->em_priv[link->pmp];
1027 rc += sprintf(buf, "%lx\n", emp->led_state);
1028 }
1029 return rc;
1030 }
1031
1032 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1033 size_t size)
1034 {
1035 int state;
1036 int pmp;
1037 struct ahci_port_priv *pp = ap->private_data;
1038 struct ahci_em_priv *emp;
1039
1040 state = simple_strtoul(buf, NULL, 0);
1041
1042 /* get the slot number from the message */
1043 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1044 if (pmp < EM_MAX_SLOTS)
1045 emp = &pp->em_priv[pmp];
1046 else
1047 return -EINVAL;
1048
1049 /* mask off the activity bits if we are in sw_activity
1050 * mode, user should turn off sw_activity before setting
1051 * activity led through em_message
1052 */
1053 if (emp->blink_policy)
1054 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1055
1056 return ap->ops->transmit_led_message(ap, state, size);
1057 }
1058
1059 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1060 {
1061 struct ata_link *link = dev->link;
1062 struct ata_port *ap = link->ap;
1063 struct ahci_port_priv *pp = ap->private_data;
1064 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1065 u32 port_led_state = emp->led_state;
1066
1067 /* save the desired Activity LED behavior */
1068 if (val == OFF) {
1069 /* clear LFLAG */
1070 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1071
1072 /* set the LED to OFF */
1073 port_led_state &= EM_MSG_LED_VALUE_OFF;
1074 port_led_state |= (ap->port_no | (link->pmp << 8));
1075 ap->ops->transmit_led_message(ap, port_led_state, 4);
1076 } else {
1077 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1078 if (val == BLINK_OFF) {
1079 /* set LED to ON for idle */
1080 port_led_state &= EM_MSG_LED_VALUE_OFF;
1081 port_led_state |= (ap->port_no | (link->pmp << 8));
1082 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1083 ap->ops->transmit_led_message(ap, port_led_state, 4);
1084 }
1085 }
1086 emp->blink_policy = val;
1087 return 0;
1088 }
1089
1090 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1091 {
1092 struct ata_link *link = dev->link;
1093 struct ata_port *ap = link->ap;
1094 struct ahci_port_priv *pp = ap->private_data;
1095 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1096
1097 /* display the saved value of activity behavior for this
1098 * disk.
1099 */
1100 return sprintf(buf, "%d\n", emp->blink_policy);
1101 }
1102
1103 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1104 int port_no, void __iomem *mmio,
1105 void __iomem *port_mmio)
1106 {
1107 const char *emsg = NULL;
1108 int rc;
1109 u32 tmp;
1110
1111 /* make sure port is not active */
1112 rc = ahci_deinit_port(ap, &emsg);
1113 if (rc)
1114 dev_warn(dev, "%s (%d)\n", emsg, rc);
1115
1116 /* clear SError */
1117 tmp = readl(port_mmio + PORT_SCR_ERR);
1118 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1119 writel(tmp, port_mmio + PORT_SCR_ERR);
1120
1121 /* clear port IRQ */
1122 tmp = readl(port_mmio + PORT_IRQ_STAT);
1123 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1124 if (tmp)
1125 writel(tmp, port_mmio + PORT_IRQ_STAT);
1126
1127 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1128 }
1129
1130 void ahci_init_controller(struct ata_host *host)
1131 {
1132 struct ahci_host_priv *hpriv = host->private_data;
1133 void __iomem *mmio = hpriv->mmio;
1134 int i;
1135 void __iomem *port_mmio;
1136 u32 tmp;
1137
1138 for (i = 0; i < host->n_ports; i++) {
1139 struct ata_port *ap = host->ports[i];
1140
1141 port_mmio = ahci_port_base(ap);
1142 if (ata_port_is_dummy(ap))
1143 continue;
1144
1145 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1146 }
1147
1148 tmp = readl(mmio + HOST_CTL);
1149 VPRINTK("HOST_CTL 0x%x\n", tmp);
1150 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1151 tmp = readl(mmio + HOST_CTL);
1152 VPRINTK("HOST_CTL 0x%x\n", tmp);
1153 }
1154 EXPORT_SYMBOL_GPL(ahci_init_controller);
1155
1156 static void ahci_dev_config(struct ata_device *dev)
1157 {
1158 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1159
1160 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1161 dev->max_sectors = 255;
1162 ata_dev_info(dev,
1163 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1164 }
1165 }
1166
1167 unsigned int ahci_dev_classify(struct ata_port *ap)
1168 {
1169 void __iomem *port_mmio = ahci_port_base(ap);
1170 struct ata_taskfile tf;
1171 u32 tmp;
1172
1173 tmp = readl(port_mmio + PORT_SIG);
1174 tf.lbah = (tmp >> 24) & 0xff;
1175 tf.lbam = (tmp >> 16) & 0xff;
1176 tf.lbal = (tmp >> 8) & 0xff;
1177 tf.nsect = (tmp) & 0xff;
1178
1179 return ata_dev_classify(&tf);
1180 }
1181 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1182
1183 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1184 u32 opts)
1185 {
1186 dma_addr_t cmd_tbl_dma;
1187
1188 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1189
1190 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1191 pp->cmd_slot[tag].status = 0;
1192 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1193 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1194 }
1195 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1196
1197 int ahci_kick_engine(struct ata_port *ap)
1198 {
1199 void __iomem *port_mmio = ahci_port_base(ap);
1200 struct ahci_host_priv *hpriv = ap->host->private_data;
1201 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1202 u32 tmp;
1203 int busy, rc;
1204
1205 /* stop engine */
1206 rc = ahci_stop_engine(ap);
1207 if (rc)
1208 goto out_restart;
1209
1210 /* need to do CLO?
1211 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1212 */
1213 busy = status & (ATA_BUSY | ATA_DRQ);
1214 if (!busy && !sata_pmp_attached(ap)) {
1215 rc = 0;
1216 goto out_restart;
1217 }
1218
1219 if (!(hpriv->cap & HOST_CAP_CLO)) {
1220 rc = -EOPNOTSUPP;
1221 goto out_restart;
1222 }
1223
1224 /* perform CLO */
1225 tmp = readl(port_mmio + PORT_CMD);
1226 tmp |= PORT_CMD_CLO;
1227 writel(tmp, port_mmio + PORT_CMD);
1228
1229 rc = 0;
1230 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1231 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1232 if (tmp & PORT_CMD_CLO)
1233 rc = -EIO;
1234
1235 /* restart engine */
1236 out_restart:
1237 ahci_start_engine(ap);
1238 return rc;
1239 }
1240 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1241
1242 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1243 struct ata_taskfile *tf, int is_cmd, u16 flags,
1244 unsigned long timeout_msec)
1245 {
1246 const u32 cmd_fis_len = 5; /* five dwords */
1247 struct ahci_port_priv *pp = ap->private_data;
1248 void __iomem *port_mmio = ahci_port_base(ap);
1249 u8 *fis = pp->cmd_tbl;
1250 u32 tmp;
1251
1252 /* prep the command */
1253 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1254 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1255
1256 /* issue & wait */
1257 writel(1, port_mmio + PORT_CMD_ISSUE);
1258
1259 if (timeout_msec) {
1260 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1261 0x1, 0x1, 1, timeout_msec);
1262 if (tmp & 0x1) {
1263 ahci_kick_engine(ap);
1264 return -EBUSY;
1265 }
1266 } else
1267 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1268
1269 return 0;
1270 }
1271
1272 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1273 int pmp, unsigned long deadline,
1274 int (*check_ready)(struct ata_link *link))
1275 {
1276 struct ata_port *ap = link->ap;
1277 struct ahci_host_priv *hpriv = ap->host->private_data;
1278 struct ahci_port_priv *pp = ap->private_data;
1279 const char *reason = NULL;
1280 unsigned long now, msecs;
1281 struct ata_taskfile tf;
1282 bool fbs_disabled = false;
1283 int rc;
1284
1285 DPRINTK("ENTER\n");
1286
1287 /* prepare for SRST (AHCI-1.1 10.4.1) */
1288 rc = ahci_kick_engine(ap);
1289 if (rc && rc != -EOPNOTSUPP)
1290 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1291
1292 /*
1293 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1294 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1295 * that is attached to port multiplier.
1296 */
1297 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1298 ahci_disable_fbs(ap);
1299 fbs_disabled = true;
1300 }
1301
1302 ata_tf_init(link->device, &tf);
1303
1304 /* issue the first D2H Register FIS */
1305 msecs = 0;
1306 now = jiffies;
1307 if (time_after(deadline, now))
1308 msecs = jiffies_to_msecs(deadline - now);
1309
1310 tf.ctl |= ATA_SRST;
1311 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1312 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1313 rc = -EIO;
1314 reason = "1st FIS failed";
1315 goto fail;
1316 }
1317
1318 /* spec says at least 5us, but be generous and sleep for 1ms */
1319 ata_msleep(ap, 1);
1320
1321 /* issue the second D2H Register FIS */
1322 tf.ctl &= ~ATA_SRST;
1323 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1324
1325 /* wait for link to become ready */
1326 rc = ata_wait_after_reset(link, deadline, check_ready);
1327 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1328 /*
1329 * Workaround for cases where link online status can't
1330 * be trusted. Treat device readiness timeout as link
1331 * offline.
1332 */
1333 ata_link_info(link, "device not ready, treating as offline\n");
1334 *class = ATA_DEV_NONE;
1335 } else if (rc) {
1336 /* link occupied, -ENODEV too is an error */
1337 reason = "device not ready";
1338 goto fail;
1339 } else
1340 *class = ahci_dev_classify(ap);
1341
1342 /* re-enable FBS if disabled before */
1343 if (fbs_disabled)
1344 ahci_enable_fbs(ap);
1345
1346 DPRINTK("EXIT, class=%u\n", *class);
1347 return 0;
1348
1349 fail:
1350 ata_link_err(link, "softreset failed (%s)\n", reason);
1351 return rc;
1352 }
1353
1354 int ahci_check_ready(struct ata_link *link)
1355 {
1356 void __iomem *port_mmio = ahci_port_base(link->ap);
1357 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1358
1359 return ata_check_ready(status);
1360 }
1361 EXPORT_SYMBOL_GPL(ahci_check_ready);
1362
1363 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1364 unsigned long deadline)
1365 {
1366 int pmp = sata_srst_pmp(link);
1367
1368 DPRINTK("ENTER\n");
1369
1370 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1371 }
1372 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1373
1374 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1375 {
1376 void __iomem *port_mmio = ahci_port_base(link->ap);
1377 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1378 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1379
1380 /*
1381 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1382 * which can save timeout delay.
1383 */
1384 if (irq_status & PORT_IRQ_BAD_PMP)
1385 return -EIO;
1386
1387 return ata_check_ready(status);
1388 }
1389
1390 int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1391 unsigned long deadline)
1392 {
1393 struct ata_port *ap = link->ap;
1394 void __iomem *port_mmio = ahci_port_base(ap);
1395 int pmp = sata_srst_pmp(link);
1396 int rc;
1397 u32 irq_sts;
1398
1399 DPRINTK("ENTER\n");
1400
1401 rc = ahci_do_softreset(link, class, pmp, deadline,
1402 ahci_bad_pmp_check_ready);
1403
1404 /*
1405 * Soft reset fails with IPMS set when PMP is enabled but
1406 * SATA HDD/ODD is connected to SATA port, do soft reset
1407 * again to port 0.
1408 */
1409 if (rc == -EIO) {
1410 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1411 if (irq_sts & PORT_IRQ_BAD_PMP) {
1412 ata_link_warn(link,
1413 "applying PMP SRST workaround "
1414 "and retrying\n");
1415 rc = ahci_do_softreset(link, class, 0, deadline,
1416 ahci_check_ready);
1417 }
1418 }
1419
1420 return rc;
1421 }
1422
1423 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1424 unsigned long deadline)
1425 {
1426 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1427 struct ata_port *ap = link->ap;
1428 struct ahci_port_priv *pp = ap->private_data;
1429 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1430 struct ata_taskfile tf;
1431 bool online;
1432 int rc;
1433
1434 DPRINTK("ENTER\n");
1435
1436 ahci_stop_engine(ap);
1437
1438 /* clear D2H reception area to properly wait for D2H FIS */
1439 ata_tf_init(link->device, &tf);
1440 tf.command = ATA_BUSY;
1441 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1442
1443 rc = sata_link_hardreset(link, timing, deadline, &online,
1444 ahci_check_ready);
1445
1446 ahci_start_engine(ap);
1447
1448 if (online)
1449 *class = ahci_dev_classify(ap);
1450
1451 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1452 return rc;
1453 }
1454
1455 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1456 {
1457 struct ata_port *ap = link->ap;
1458 void __iomem *port_mmio = ahci_port_base(ap);
1459 u32 new_tmp, tmp;
1460
1461 ata_std_postreset(link, class);
1462
1463 /* Make sure port's ATAPI bit is set appropriately */
1464 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1465 if (*class == ATA_DEV_ATAPI)
1466 new_tmp |= PORT_CMD_ATAPI;
1467 else
1468 new_tmp &= ~PORT_CMD_ATAPI;
1469 if (new_tmp != tmp) {
1470 writel(new_tmp, port_mmio + PORT_CMD);
1471 readl(port_mmio + PORT_CMD); /* flush */
1472 }
1473 }
1474
1475 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1476 {
1477 struct scatterlist *sg;
1478 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1479 unsigned int si;
1480
1481 VPRINTK("ENTER\n");
1482
1483 /*
1484 * Next, the S/G list.
1485 */
1486 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1487 dma_addr_t addr = sg_dma_address(sg);
1488 u32 sg_len = sg_dma_len(sg);
1489
1490 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1491 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1492 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1493 }
1494
1495 return si;
1496 }
1497
1498 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1499 {
1500 struct ata_port *ap = qc->ap;
1501 struct ahci_port_priv *pp = ap->private_data;
1502
1503 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1504 return ata_std_qc_defer(qc);
1505 else
1506 return sata_pmp_qc_defer_cmd_switch(qc);
1507 }
1508 #if defined(CONFIG_E2K)
1509 static unsigned int ahci_fill_sg_1sect(struct ata_queued_cmd *qc, void *cmd_tbl)
1510 {
1511 struct scatterlist *sg;
1512 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1513 unsigned int si, j = 0;
1514
1515 VPRINTK("ENTER\n");
1516
1517 /*
1518 * Next, the S/G list.
1519 */
1520 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1521 dma_addr_t addr = sg_dma_address(sg);
1522 u32 sg_len = sg_dma_len(sg);
1523 int i, rem = sg_len % ATA_SECT_SIZE;
1524 for (i = 0; i < sg_len / ATA_SECT_SIZE; i++,
1525 addr += ATA_SECT_SIZE) {
1526 BUG_ON(j + i >= AHCI_MAX_SG);
1527 ahci_sg[j + i].addr = cpu_to_le32(addr & 0xffffffff);
1528 ahci_sg[j + i].addr_hi =
1529 cpu_to_le32((addr >> 16) >> 16);
1530 ahci_sg[j + i].flags_size =
1531 cpu_to_le32(ATA_SECT_SIZE - 1);
1532 }
1533 if (rem) {
1534 ahci_sg[j + i].addr = cpu_to_le32(addr & 0xffffffff);
1535 ahci_sg[j + i].addr_hi =
1536 cpu_to_le32((addr >> 16) >> 16);
1537 ahci_sg[j + i].flags_size = cpu_to_le32(rem - 1);
1538 i++;
1539 }
1540 j += i;
1541 }
1542
1543 return j;
1544 }
1545 #endif
1546
1547 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1548 {
1549 struct ata_port *ap = qc->ap;
1550 struct ahci_port_priv *pp = ap->private_data;
1551 int is_atapi = ata_is_atapi(qc->tf.protocol);
1552 void *cmd_tbl;
1553 u32 opts;
1554 const u32 cmd_fis_len = 5; /* five dwords */
1555 unsigned int n_elem;
1556
1557 /*
1558 * Fill in command table information. First, the header,
1559 * a SATA Register - Host to Device command FIS.
1560 */
1561 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1562
1563 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1564 if (is_atapi) {
1565 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1566 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1567 }
1568
1569 n_elem = 0;
1570 #if defined(CONFIG_E2K)
1571 if (qc->flags & ATA_QCFLAG_DMAMAP) {
1572 struct ahci_host_priv *hpriv = ap->host->private_data;
1573 if (hpriv->flags & AHCI_HFLAG_SECT1)
1574 n_elem = ahci_fill_sg_1sect(qc, cmd_tbl);
1575 else
1576 n_elem = ahci_fill_sg(qc, cmd_tbl);
1577
1578 if (is_atapi && hpriv->flags & AHCI_HFLAG_SECT1) {
1579 void __iomem *port_mmio = ahci_port_base(ap);
1580 u32 v = readl(port_mmio + PORT_CMD);
1581 writel(v & ~PORT_CMD_START, port_mmio + PORT_CMD);
1582 readl(port_mmio + PORT_CMD);
1583 writel(v, port_mmio + PORT_CMD);
1584 }
1585 }
1586 #else
1587 if (qc->flags & ATA_QCFLAG_DMAMAP)
1588 n_elem = ahci_fill_sg(qc, cmd_tbl);
1589 #endif
1590
1591 /*
1592 * Fill in command slot information.
1593 */
1594 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1595 if (qc->tf.flags & ATA_TFLAG_WRITE)
1596 opts |= AHCI_CMD_WRITE;
1597 if (is_atapi)
1598 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1599
1600 ahci_fill_cmd_slot(pp, qc->tag, opts);
1601 }
1602
1603 static void ahci_fbs_dec_intr(struct ata_port *ap)
1604 {
1605 struct ahci_port_priv *pp = ap->private_data;
1606 void __iomem *port_mmio = ahci_port_base(ap);
1607 u32 fbs = readl(port_mmio + PORT_FBS);
1608 int retries = 3;
1609
1610 DPRINTK("ENTER\n");
1611 BUG_ON(!pp->fbs_enabled);
1612
1613 /* time to wait for DEC is not specified by AHCI spec,
1614 * add a retry loop for safety.
1615 */
1616 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1617 fbs = readl(port_mmio + PORT_FBS);
1618 while ((fbs & PORT_FBS_DEC) && retries--) {
1619 udelay(1);
1620 fbs = readl(port_mmio + PORT_FBS);
1621 }
1622
1623 if (fbs & PORT_FBS_DEC)
1624 dev_err(ap->host->dev, "failed to clear device error\n");
1625 }
1626
1627 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1628 {
1629 struct ahci_host_priv *hpriv = ap->host->private_data;
1630 struct ahci_port_priv *pp = ap->private_data;
1631 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1632 struct ata_link *link = NULL;
1633 struct ata_queued_cmd *active_qc;
1634 struct ata_eh_info *active_ehi;
1635 bool fbs_need_dec = false;
1636 u32 serror;
1637
1638 /* determine active link with error */
1639 if (pp->fbs_enabled) {
1640 void __iomem *port_mmio = ahci_port_base(ap);
1641 u32 fbs = readl(port_mmio + PORT_FBS);
1642 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1643
1644 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1645 link = &ap->pmp_link[pmp];
1646 fbs_need_dec = true;
1647 }
1648
1649 } else
1650 ata_for_each_link(link, ap, EDGE)
1651 if (ata_link_active(link))
1652 break;
1653
1654 if (!link)
1655 link = &ap->link;
1656
1657 active_qc = ata_qc_from_tag(ap, link->active_tag);
1658 active_ehi = &link->eh_info;
1659
1660 /* record irq stat */
1661 ata_ehi_clear_desc(host_ehi);
1662 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1663
1664 /* AHCI needs SError cleared; otherwise, it might lock up */
1665 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1666 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1667 host_ehi->serror |= serror;
1668
1669 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1670 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1671 irq_stat &= ~PORT_IRQ_IF_ERR;
1672
1673 if (irq_stat & PORT_IRQ_TF_ERR) {
1674 /* If qc is active, charge it; otherwise, the active
1675 * link. There's no active qc on NCQ errors. It will
1676 * be determined by EH by reading log page 10h.
1677 */
1678 if (active_qc)
1679 active_qc->err_mask |= AC_ERR_DEV;
1680 else
1681 active_ehi->err_mask |= AC_ERR_DEV;
1682
1683 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1684 host_ehi->serror &= ~SERR_INTERNAL;
1685 }
1686
1687 if (irq_stat & PORT_IRQ_UNK_FIS) {
1688 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1689
1690 active_ehi->err_mask |= AC_ERR_HSM;
1691 active_ehi->action |= ATA_EH_RESET;
1692 ata_ehi_push_desc(active_ehi,
1693 "unknown FIS %08x %08x %08x %08x" ,
1694 unk[0], unk[1], unk[2], unk[3]);
1695 }
1696
1697 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1698 active_ehi->err_mask |= AC_ERR_HSM;
1699 active_ehi->action |= ATA_EH_RESET;
1700 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1701 }
1702
1703 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1704 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1705 host_ehi->action |= ATA_EH_RESET;
1706 ata_ehi_push_desc(host_ehi, "host bus error");
1707 }
1708
1709 if (irq_stat & PORT_IRQ_IF_ERR) {
1710 if (fbs_need_dec)
1711 active_ehi->err_mask |= AC_ERR_DEV;
1712 else {
1713 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1714 host_ehi->action |= ATA_EH_RESET;
1715 }
1716
1717 ata_ehi_push_desc(host_ehi, "interface fatal error");
1718 }
1719
1720 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1721 ata_ehi_hotplugged(host_ehi);
1722 ata_ehi_push_desc(host_ehi, "%s",
1723 irq_stat & PORT_IRQ_CONNECT ?
1724 "connection status changed" : "PHY RDY changed");
1725 }
1726
1727 /* okay, let's hand over to EH */
1728
1729 if (irq_stat & PORT_IRQ_FREEZE)
1730 ata_port_freeze(ap);
1731 else if (fbs_need_dec) {
1732 ata_link_abort(link);
1733 ahci_fbs_dec_intr(ap);
1734 } else
1735 ata_port_abort(ap);
1736 }
1737
1738 static void ahci_handle_port_interrupt(struct ata_port *ap,
1739 void __iomem *port_mmio, u32 status)
1740 {
1741 struct ata_eh_info *ehi = &ap->link.eh_info;
1742 struct ahci_port_priv *pp = ap->private_data;
1743 struct ahci_host_priv *hpriv = ap->host->private_data;
1744 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1745 u32 qc_active = 0;
1746 int rc;
1747
1748 /* ignore BAD_PMP while resetting */
1749 if (unlikely(resetting))
1750 status &= ~PORT_IRQ_BAD_PMP;
1751
1752 if (sata_lpm_ignore_phy_events(&ap->link)) {
1753 status &= ~PORT_IRQ_PHYRDY;
1754 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1755 }
1756
1757 if (unlikely(status & PORT_IRQ_ERROR)) {
1758 ahci_error_intr(ap, status);
1759 return;
1760 }
1761
1762 if (status & PORT_IRQ_SDB_FIS) {
1763 /* If SNotification is available, leave notification
1764 * handling to sata_async_notification(). If not,
1765 * emulate it by snooping SDB FIS RX area.
1766 *
1767 * Snooping FIS RX area is probably cheaper than
1768 * poking SNotification but some constrollers which
1769 * implement SNotification, ICH9 for example, don't
1770 * store AN SDB FIS into receive area.
1771 */
1772 if (hpriv->cap & HOST_CAP_SNTF)
1773 sata_async_notification(ap);
1774 else {
1775 /* If the 'N' bit in word 0 of the FIS is set,
1776 * we just received asynchronous notification.
1777 * Tell libata about it.
1778 *
1779 * Lack of SNotification should not appear in
1780 * ahci 1.2, so the workaround is unnecessary
1781 * when FBS is enabled.
1782 */
1783 if (pp->fbs_enabled)
1784 WARN_ON_ONCE(1);
1785 else {
1786 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1787 u32 f0 = le32_to_cpu(f[0]);
1788 if (f0 & (1 << 15))
1789 sata_async_notification(ap);
1790 }
1791 }
1792 }
1793
1794 /* pp->active_link is not reliable once FBS is enabled, both
1795 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1796 * NCQ and non-NCQ commands may be in flight at the same time.
1797 */
1798 if (pp->fbs_enabled) {
1799 if (ap->qc_active) {
1800 qc_active = readl(port_mmio + PORT_SCR_ACT);
1801 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1802 }
1803 } else {
1804 /* pp->active_link is valid iff any command is in flight */
1805 if (ap->qc_active && pp->active_link->sactive)
1806 qc_active = readl(port_mmio + PORT_SCR_ACT);
1807 else
1808 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1809 }
1810
1811
1812 rc = ata_qc_complete_multiple(ap, qc_active);
1813
1814 /* while resetting, invalid completions are expected */
1815 if (unlikely(rc < 0 && !resetting)) {
1816 ehi->err_mask |= AC_ERR_HSM;
1817 ehi->action |= ATA_EH_RESET;
1818 ata_port_freeze(ap);
1819 }
1820 }
1821
1822 static void ahci_port_intr(struct ata_port *ap)
1823 {
1824 void __iomem *port_mmio = ahci_port_base(ap);
1825 u32 status;
1826
1827 status = readl(port_mmio + PORT_IRQ_STAT);
1828 writel(status, port_mmio + PORT_IRQ_STAT);
1829
1830 ahci_handle_port_interrupt(ap, port_mmio, status);
1831 }
1832
1833 irqreturn_t ahci_thread_fn(int irq, void *dev_instance)
1834 {
1835 struct ata_port *ap = dev_instance;
1836 struct ahci_port_priv *pp = ap->private_data;
1837 void __iomem *port_mmio = ahci_port_base(ap);
1838 unsigned long flags;
1839 u32 status;
1840
1841 spin_lock_irqsave(&ap->host->lock, flags);
1842 status = pp->intr_status;
1843 if (status)
1844 pp->intr_status = 0;
1845 spin_unlock_irqrestore(&ap->host->lock, flags);
1846
1847 spin_lock_bh(ap->lock);
1848 ahci_handle_port_interrupt(ap, port_mmio, status);
1849 spin_unlock_bh(ap->lock);
1850
1851 return IRQ_HANDLED;
1852 }
1853 EXPORT_SYMBOL_GPL(ahci_thread_fn);
1854
1855 static void ahci_hw_port_interrupt(struct ata_port *ap)
1856 {
1857 void __iomem *port_mmio = ahci_port_base(ap);
1858 struct ahci_port_priv *pp = ap->private_data;
1859 u32 status;
1860
1861 status = readl(port_mmio + PORT_IRQ_STAT);
1862 writel(status, port_mmio + PORT_IRQ_STAT);
1863
1864 pp->intr_status |= status;
1865 }
1866
1867 irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance)
1868 {
1869 struct ata_port *ap_this = dev_instance;
1870 struct ahci_port_priv *pp = ap_this->private_data;
1871 struct ata_host *host = ap_this->host;
1872 struct ahci_host_priv *hpriv = host->private_data;
1873 void __iomem *mmio = hpriv->mmio;
1874 unsigned int i;
1875 u32 irq_stat, irq_masked;
1876
1877 VPRINTK("ENTER\n");
1878
1879 spin_lock(&host->lock);
1880
1881 irq_stat = readl(mmio + HOST_IRQ_STAT);
1882
1883 if (!irq_stat) {
1884 u32 status = pp->intr_status;
1885
1886 spin_unlock(&host->lock);
1887
1888 VPRINTK("EXIT\n");
1889
1890 return status ? IRQ_WAKE_THREAD : IRQ_NONE;
1891 }
1892
1893 irq_masked = irq_stat & hpriv->port_map;
1894
1895 for (i = 0; i < host->n_ports; i++) {
1896 struct ata_port *ap;
1897
1898 if (!(irq_masked & (1 << i)))
1899 continue;
1900
1901 ap = host->ports[i];
1902 if (ap) {
1903 ahci_hw_port_interrupt(ap);
1904 VPRINTK("port %u\n", i);
1905 } else {
1906 VPRINTK("port %u (no irq)\n", i);
1907 if (ata_ratelimit())
1908 dev_warn(host->dev,
1909 "interrupt on disabled port %u\n", i);
1910 }
1911 }
1912
1913 writel(irq_stat, mmio + HOST_IRQ_STAT);
1914
1915 spin_unlock(&host->lock);
1916
1917 VPRINTK("EXIT\n");
1918
1919 return IRQ_WAKE_THREAD;
1920 }
1921 EXPORT_SYMBOL_GPL(ahci_hw_interrupt);
1922
1923 irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1924 {
1925 struct ata_host *host = dev_instance;
1926 struct ahci_host_priv *hpriv;
1927 unsigned int i, handled = 0;
1928 void __iomem *mmio;
1929 u32 irq_stat, irq_masked;
1930
1931 VPRINTK("ENTER\n");
1932
1933 hpriv = host->private_data;
1934 mmio = hpriv->mmio;
1935
1936 /* sigh. 0xffffffff is a valid return from h/w */
1937 irq_stat = readl(mmio + HOST_IRQ_STAT);
1938 if (!irq_stat)
1939 return IRQ_NONE;
1940
1941 irq_masked = irq_stat & hpriv->port_map;
1942
1943 spin_lock(&host->lock);
1944
1945 for (i = 0; i < host->n_ports; i++) {
1946 struct ata_port *ap;
1947
1948 if (!(irq_masked & (1 << i)))
1949 continue;
1950
1951 ap = host->ports[i];
1952 if (ap) {
1953 ahci_port_intr(ap);
1954 VPRINTK("port %u\n", i);
1955 } else {
1956 VPRINTK("port %u (no irq)\n", i);
1957 if (ata_ratelimit())
1958 dev_warn(host->dev,
1959 "interrupt on disabled port %u\n", i);
1960 }
1961
1962 handled = 1;
1963 }
1964
1965 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1966 * it should be cleared after all the port events are cleared;
1967 * otherwise, it will raise a spurious interrupt after each
1968 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1969 * information.
1970 *
1971 * Also, use the unmasked value to clear interrupt as spurious
1972 * pending event on a dummy port might cause screaming IRQ.
1973 */
1974 writel(irq_stat, mmio + HOST_IRQ_STAT);
1975
1976 spin_unlock(&host->lock);
1977
1978 VPRINTK("EXIT\n");
1979
1980 return IRQ_RETVAL(handled);
1981 }
1982 EXPORT_SYMBOL_GPL(ahci_interrupt);
1983
1984 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1985 {
1986 struct ata_port *ap = qc->ap;
1987 void __iomem *port_mmio = ahci_port_base(ap);
1988 struct ahci_port_priv *pp = ap->private_data;
1989
1990 /* Keep track of the currently active link. It will be used
1991 * in completion path to determine whether NCQ phase is in
1992 * progress.
1993 */
1994 pp->active_link = qc->dev->link;
1995
1996 if (qc->tf.protocol == ATA_PROT_NCQ)
1997 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1998
1999 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2000 u32 fbs = readl(port_mmio + PORT_FBS);
2001 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2002 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2003 writel(fbs, port_mmio + PORT_FBS);
2004 pp->fbs_last_dev = qc->dev->link->pmp;
2005 }
2006
2007 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2008
2009 ahci_sw_activity(qc->dev->link);
2010
2011 return 0;
2012 }
2013
2014 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2015 {
2016 struct ahci_port_priv *pp = qc->ap->private_data;
2017 u8 *rx_fis = pp->rx_fis;
2018
2019 if (pp->fbs_enabled)
2020 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2021
2022 /*
2023 * After a successful execution of an ATA PIO data-in command,
2024 * the device doesn't send D2H Reg FIS to update the TF and
2025 * the host should take TF and E_Status from the preceding PIO
2026 * Setup FIS.
2027 */
2028 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2029 !(qc->flags & ATA_QCFLAG_FAILED)) {
2030 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2031 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2032 } else
2033 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2034
2035 return true;
2036 }
2037
2038 static void ahci_freeze(struct ata_port *ap)
2039 {
2040 void __iomem *port_mmio = ahci_port_base(ap);
2041
2042 /* turn IRQ off */
2043 writel(0, port_mmio + PORT_IRQ_MASK);
2044 }
2045
2046 static void ahci_thaw(struct ata_port *ap)
2047 {
2048 struct ahci_host_priv *hpriv = ap->host->private_data;
2049 void __iomem *mmio = hpriv->mmio;
2050 void __iomem *port_mmio = ahci_port_base(ap);
2051 u32 tmp;
2052 struct ahci_port_priv *pp = ap->private_data;
2053
2054 /* clear IRQ */
2055 tmp = readl(port_mmio + PORT_IRQ_STAT);
2056 writel(tmp, port_mmio + PORT_IRQ_STAT);
2057 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2058
2059 /* turn IRQ back on */
2060 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2061 }
2062
2063 void ahci_error_handler(struct ata_port *ap)
2064 {
2065 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2066 /* restart engine */
2067 ahci_stop_engine(ap);
2068 ahci_start_engine(ap);
2069 }
2070
2071 sata_pmp_error_handler(ap);
2072
2073 if (!ata_dev_enabled(ap->link.device))
2074 ahci_stop_engine(ap);
2075 }
2076 EXPORT_SYMBOL_GPL(ahci_error_handler);
2077
2078 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2079 {
2080 struct ata_port *ap = qc->ap;
2081
2082 /* make DMA engine forget about the failed command */
2083 if (qc->flags & ATA_QCFLAG_FAILED)
2084 ahci_kick_engine(ap);
2085 }
2086
2087 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2088 {
2089 void __iomem *port_mmio = ahci_port_base(ap);
2090 struct ata_device *dev = ap->link.device;
2091 u32 devslp, dm, dito, mdat, deto;
2092 int rc;
2093 unsigned int err_mask;
2094
2095 devslp = readl(port_mmio + PORT_DEVSLP);
2096 if (!(devslp & PORT_DEVSLP_DSP)) {
2097 dev_err(ap->host->dev, "port does not support device sleep\n");
2098 return;
2099 }
2100
2101 /* disable device sleep */
2102 if (!sleep) {
2103 if (devslp & PORT_DEVSLP_ADSE) {
2104 writel(devslp & ~PORT_DEVSLP_ADSE,
2105 port_mmio + PORT_DEVSLP);
2106 err_mask = ata_dev_set_feature(dev,
2107 SETFEATURES_SATA_DISABLE,
2108 SATA_DEVSLP);
2109 if (err_mask && err_mask != AC_ERR_DEV)
2110 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2111 }
2112 return;
2113 }
2114
2115 /* device sleep was already enabled */
2116 if (devslp & PORT_DEVSLP_ADSE)
2117 return;
2118
2119 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2120 rc = ahci_stop_engine(ap);
2121 if (rc)
2122 return;
2123
2124 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2125 dito = devslp_idle_timeout / (dm + 1);
2126 if (dito > 0x3ff)
2127 dito = 0x3ff;
2128
2129 /* Use the nominal value 10 ms if the read MDAT is zero,
2130 * the nominal value of DETO is 20 ms.
2131 */
2132 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2133 ATA_LOG_DEVSLP_VALID_MASK) {
2134 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2135 ATA_LOG_DEVSLP_MDAT_MASK;
2136 if (!mdat)
2137 mdat = 10;
2138 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2139 if (!deto)
2140 deto = 20;
2141 } else {
2142 mdat = 10;
2143 deto = 20;
2144 }
2145
2146 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2147 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2148 (deto << PORT_DEVSLP_DETO_OFFSET) |
2149 PORT_DEVSLP_ADSE);
2150 writel(devslp, port_mmio + PORT_DEVSLP);
2151
2152 ahci_start_engine(ap);
2153
2154 /* enable device sleep feature for the drive */
2155 err_mask = ata_dev_set_feature(dev,
2156 SETFEATURES_SATA_ENABLE,
2157 SATA_DEVSLP);
2158 if (err_mask && err_mask != AC_ERR_DEV)
2159 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2160 }
2161
2162 static void ahci_enable_fbs(struct ata_port *ap)
2163 {
2164 struct ahci_port_priv *pp = ap->private_data;
2165 void __iomem *port_mmio = ahci_port_base(ap);
2166 u32 fbs;
2167 int rc;
2168
2169 if (!pp->fbs_supported)
2170 return;
2171
2172 fbs = readl(port_mmio + PORT_FBS);
2173 if (fbs & PORT_FBS_EN) {
2174 pp->fbs_enabled = true;
2175 pp->fbs_last_dev = -1; /* initialization */
2176 return;
2177 }
2178
2179 rc = ahci_stop_engine(ap);
2180 if (rc)
2181 return;
2182
2183 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2184 fbs = readl(port_mmio + PORT_FBS);
2185 if (fbs & PORT_FBS_EN) {
2186 dev_info(ap->host->dev, "FBS is enabled\n");
2187 pp->fbs_enabled = true;
2188 pp->fbs_last_dev = -1; /* initialization */
2189 } else
2190 dev_err(ap->host->dev, "Failed to enable FBS\n");
2191
2192 ahci_start_engine(ap);
2193 }
2194
2195 static void ahci_disable_fbs(struct ata_port *ap)
2196 {
2197 struct ahci_port_priv *pp = ap->private_data;
2198 void __iomem *port_mmio = ahci_port_base(ap);
2199 u32 fbs;
2200 int rc;
2201
2202 if (!pp->fbs_supported)
2203 return;
2204
2205 fbs = readl(port_mmio + PORT_FBS);
2206 if ((fbs & PORT_FBS_EN) == 0) {
2207 pp->fbs_enabled = false;
2208 return;
2209 }
2210
2211 rc = ahci_stop_engine(ap);
2212 if (rc)
2213 return;
2214
2215 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2216 fbs = readl(port_mmio + PORT_FBS);
2217 if (fbs & PORT_FBS_EN)
2218 dev_err(ap->host->dev, "Failed to disable FBS\n");
2219 else {
2220 dev_info(ap->host->dev, "FBS is disabled\n");
2221 pp->fbs_enabled = false;
2222 }
2223
2224 ahci_start_engine(ap);
2225 }
2226
2227 static void ahci_pmp_attach(struct ata_port *ap)
2228 {
2229 void __iomem *port_mmio = ahci_port_base(ap);
2230 struct ahci_port_priv *pp = ap->private_data;
2231 u32 cmd;
2232
2233 cmd = readl(port_mmio + PORT_CMD);
2234 cmd |= PORT_CMD_PMP;
2235 writel(cmd, port_mmio + PORT_CMD);
2236
2237 ahci_enable_fbs(ap);
2238
2239 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2240
2241 /*
2242 * We must not change the port interrupt mask register if the
2243 * port is marked frozen, the value in pp->intr_mask will be
2244 * restored later when the port is thawed.
2245 *
2246 * Note that during initialization, the port is marked as
2247 * frozen since the irq handler is not yet registered.
2248 */
2249 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2250 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2251 }
2252
2253 static void ahci_pmp_detach(struct ata_port *ap)
2254 {
2255 void __iomem *port_mmio = ahci_port_base(ap);
2256 struct ahci_port_priv *pp = ap->private_data;
2257 u32 cmd;
2258
2259 ahci_disable_fbs(ap);
2260
2261 cmd = readl(port_mmio + PORT_CMD);
2262 cmd &= ~PORT_CMD_PMP;
2263 writel(cmd, port_mmio + PORT_CMD);
2264
2265 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2266
2267 /* see comment above in ahci_pmp_attach() */
2268 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2269 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2270 }
2271
2272 int ahci_port_resume(struct ata_port *ap)
2273 {
2274 ahci_power_up(ap);
2275 ahci_start_port(ap);
2276
2277 if (sata_pmp_attached(ap))
2278 ahci_pmp_attach(ap);
2279 else
2280 ahci_pmp_detach(ap);
2281
2282 return 0;
2283 }
2284 EXPORT_SYMBOL_GPL(ahci_port_resume);
2285
2286 #ifdef CONFIG_PM
2287 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2288 {
2289 const char *emsg = NULL;
2290 int rc;
2291
2292 rc = ahci_deinit_port(ap, &emsg);
2293 if (rc == 0)
2294 ahci_power_down(ap);
2295 else {
2296 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2297 ata_port_freeze(ap);
2298 }
2299
2300 return rc;
2301 }
2302 #endif
2303
2304 static int ahci_port_start(struct ata_port *ap)
2305 {
2306 struct ahci_host_priv *hpriv = ap->host->private_data;
2307 struct device *dev = ap->host->dev;
2308 struct ahci_port_priv *pp;
2309 void *mem;
2310 dma_addr_t mem_dma;
2311 size_t dma_sz, rx_fis_sz;
2312
2313 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2314 if (!pp)
2315 return -ENOMEM;
2316
2317 if (ap->host->n_ports > 1) {
2318 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2319 if (!pp->irq_desc) {
2320 devm_kfree(dev, pp);
2321 return -ENOMEM;
2322 }
2323 snprintf(pp->irq_desc, 8,
2324 "%s%d", dev_driver_string(dev), ap->port_no);
2325 }
2326
2327 /* check FBS capability */
2328 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2329 void __iomem *port_mmio = ahci_port_base(ap);
2330 u32 cmd = readl(port_mmio + PORT_CMD);
2331 if (cmd & PORT_CMD_FBSCP)
2332 pp->fbs_supported = true;
2333 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2334 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2335 ap->port_no);
2336 pp->fbs_supported = true;
2337 } else
2338 dev_warn(dev, "port %d is not capable of FBS\n",
2339 ap->port_no);
2340 }
2341
2342 if (pp->fbs_supported) {
2343 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2344 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2345 } else {
2346 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2347 rx_fis_sz = AHCI_RX_FIS_SZ;
2348 }
2349
2350 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2351 if (!mem)
2352 return -ENOMEM;
2353 memset(mem, 0, dma_sz);
2354
2355 /*
2356 * First item in chunk of DMA memory: 32-slot command table,
2357 * 32 bytes each in size
2358 */
2359 pp->cmd_slot = mem;
2360 pp->cmd_slot_dma = mem_dma;
2361
2362 mem += AHCI_CMD_SLOT_SZ;
2363 mem_dma += AHCI_CMD_SLOT_SZ;
2364
2365 /*
2366 * Second item: Received-FIS area
2367 */
2368 pp->rx_fis = mem;
2369 pp->rx_fis_dma = mem_dma;
2370
2371 mem += rx_fis_sz;
2372 mem_dma += rx_fis_sz;
2373
2374 /*
2375 * Third item: data area for storing a single command
2376 * and its scatter-gather table
2377 */
2378 pp->cmd_tbl = mem;
2379 pp->cmd_tbl_dma = mem_dma;
2380
2381 /*
2382 * Save off initial list of interrupts to be enabled.
2383 * This could be changed later
2384 */
2385 pp->intr_mask = DEF_PORT_IRQ;
2386
2387 /*
2388 * Switch to per-port locking in case each port has its own MSI vector.
2389 */
2390 if ((hpriv->flags & AHCI_HFLAG_MULTI_MSI)) {
2391 spin_lock_init(&pp->lock);
2392 ap->lock = &pp->lock;
2393 }
2394
2395 ap->private_data = pp;
2396
2397 /* engage engines, captain */
2398 return ahci_port_resume(ap);
2399 }
2400
2401 static void ahci_port_stop(struct ata_port *ap)
2402 {
2403 const char *emsg = NULL;
2404 int rc;
2405
2406 /* de-initialize port */
2407 rc = ahci_deinit_port(ap, &emsg);
2408 if (rc)
2409 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2410 }
2411
2412 void ahci_print_info(struct ata_host *host, const char *scc_s)
2413 {
2414 struct ahci_host_priv *hpriv = host->private_data;
2415 void __iomem *mmio = hpriv->mmio;
2416 u32 vers, cap, cap2, impl, speed;
2417 const char *speed_s;
2418
2419 vers = readl(mmio + HOST_VERSION);
2420 cap = hpriv->cap;
2421 cap2 = hpriv->cap2;
2422 impl = hpriv->port_map;
2423
2424 speed = (cap >> 20) & 0xf;
2425 if (speed == 1)
2426 speed_s = "1.5";
2427 else if (speed == 2)
2428 speed_s = "3";
2429 else if (speed == 3)
2430 speed_s = "6";
2431 else
2432 speed_s = "?";
2433
2434 dev_info(host->dev,
2435 "AHCI %02x%02x.%02x%02x "
2436 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2437 ,
2438
2439 (vers >> 24) & 0xff,
2440 (vers >> 16) & 0xff,
2441 (vers >> 8) & 0xff,
2442 vers & 0xff,
2443
2444 ((cap >> 8) & 0x1f) + 1,
2445 (cap & 0x1f) + 1,
2446 speed_s,
2447 impl,
2448 scc_s);
2449
2450 dev_info(host->dev,
2451 "flags: "
2452 "%s%s%s%s%s%s%s"
2453 "%s%s%s%s%s%s%s"
2454 "%s%s%s%s%s%s%s"
2455 "%s%s\n"
2456 ,
2457
2458 cap & HOST_CAP_64 ? "64bit " : "",
2459 cap & HOST_CAP_NCQ ? "ncq " : "",
2460 cap & HOST_CAP_SNTF ? "sntf " : "",
2461 cap & HOST_CAP_MPS ? "ilck " : "",
2462 cap & HOST_CAP_SSS ? "stag " : "",
2463 cap & HOST_CAP_ALPM ? "pm " : "",
2464 cap & HOST_CAP_LED ? "led " : "",
2465 cap & HOST_CAP_CLO ? "clo " : "",
2466 cap & HOST_CAP_ONLY ? "only " : "",
2467 cap & HOST_CAP_PMP ? "pmp " : "",
2468 cap & HOST_CAP_FBS ? "fbs " : "",
2469 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2470 cap & HOST_CAP_SSC ? "slum " : "",
2471 cap & HOST_CAP_PART ? "part " : "",
2472 cap & HOST_CAP_CCC ? "ccc " : "",
2473 cap & HOST_CAP_EMS ? "ems " : "",
2474 cap & HOST_CAP_SXS ? "sxs " : "",
2475 cap2 & HOST_CAP2_DESO ? "deso " : "",
2476 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2477 cap2 & HOST_CAP2_SDS ? "sds " : "",
2478 cap2 & HOST_CAP2_APST ? "apst " : "",
2479 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2480 cap2 & HOST_CAP2_BOH ? "boh " : ""
2481 );
2482 }
2483 EXPORT_SYMBOL_GPL(ahci_print_info);
2484
2485 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2486 struct ata_port_info *pi)
2487 {
2488 u8 messages;
2489 void __iomem *mmio = hpriv->mmio;
2490 u32 em_loc = readl(mmio + HOST_EM_LOC);
2491 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2492
2493 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2494 return;
2495
2496 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2497
2498 if (messages) {
2499 /* store em_loc */
2500 hpriv->em_loc = ((em_loc >> 16) * 4);
2501 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2502 hpriv->em_msg_type = messages;
2503 pi->flags |= ATA_FLAG_EM;
2504 if (!(em_ctl & EM_CTL_ALHD))
2505 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2506 }
2507 }
2508 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2509
2510 MODULE_AUTHOR("Jeff Garzik");
2511 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2512 MODULE_LICENSE("GPL");
Linux for the MCST Elbrus 2000 architecture