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Lynx framebuffers multidomain implementation.
[linux/elbrus.git] / drivers / mcst / mckk / mckk_ioctl.h
blob11d16dbc68a8a65a2eae9982827c9eb7cce22791
1
2 #define ME90_DEBUG_MSG_LINE_SIZE 128
3 #define ME90_DEBUG_MSG_LINE_NUM 500
4
5 /*
6 * Get driver last tracer info
7 */
8
9 /*ARGSUSED*/
10 static int mckk_get_driver_trace_ioctl(
11 mcb_state_t *state,
12 caddr_t arg,
13 int mode)
14 {
15 drv_trace_msg_t drv_tracer_msg;
16 int moved_size = 0;
17 int added_size = 0;
18 int rval = 0;
19 int cur_line = 0;
20
21 ME90_LOG(state, ME90_DL_TRACE,
22 "mckk_get_driver_trace_ioctl started\n");
23
24 if (ddi_copyin(arg, (caddr_t) & drv_tracer_msg,
25 sizeof (drv_trace_msg_t)/*, mode*/)) {
26 ME90_LOG(state, ME90_DL_ERROR,
27 "mckk_get_driver_trace_ioctl: ddi_copyin failed\n");
28 return EFAULT;
29 }
30 cur_line = me90_debug_buf_line;
31 if (me90_debug_buf_overflow && me90_debug_msg_buf != NULL) {
32 moved_size = min(drv_tracer_msg.msg_buf_size,
33 ME90_DEBUG_MSG_LINE_NUM *
34 ME90_DEBUG_MSG_LINE_SIZE -
35 cur_line * ME90_DEBUG_MSG_LINE_SIZE);
36 rval = ddi_copyout(&me90_debug_msg_buf[cur_line *
37 ME90_DEBUG_MSG_LINE_SIZE],
38 drv_tracer_msg.msg_buf_addr, moved_size/*, mode*/);
39 if (rval != 0) {
40 ME90_LOG(state, ME90_DL_ERROR,
41 "mckk_get_driver_trace_ioctl: ddi_copyout"
42 " failed \n");
43 return EFAULT;
44 }
45 }
46 if (cur_line > 0 && moved_size < drv_tracer_msg.msg_buf_size &&
47 me90_debug_msg_buf != NULL) {
48 added_size = min(drv_tracer_msg.msg_buf_size - moved_size,
49 cur_line * ME90_DEBUG_MSG_LINE_SIZE);
50 rval = ddi_copyout(me90_debug_msg_buf,
51 &drv_tracer_msg.msg_buf_addr[moved_size],
52 added_size/*, mode*/);
53 if (rval != 0) {
54 ME90_LOG(state, ME90_DL_ERROR,
55 "mckk_get_driver_trace_ioctl: ddi_copyout "
56 "failed\n");
57 return EFAULT;
58 }
59 }
60 drv_tracer_msg.msg_line_num = (moved_size + added_size) /
61 ME90_DEBUG_MSG_LINE_SIZE;
62 drv_tracer_msg.msg_line_size = ME90_DEBUG_MSG_LINE_SIZE;
63 if (ddi_copyout((caddr_t) & drv_tracer_msg, arg,
64 sizeof (drv_trace_msg_t)/*, mode*/)) {
65 ME90_LOG(state, ME90_DL_ERROR,
66 "mckk_get_driver_trace_ioctl: ddi_copyout failed\n");
67 return EFAULT;
68 }
69 ME90_LOG(state, ME90_DL_TRACE,
70 "mckk_get_driver_trace_ioctl succeeded\n");
71 return 0;
72 }
73
74 /*
75 * Load MP-driver code to base memory of module
76 */
77 /*ARGSUSED*/
78 static int mckk_load_mp_drv_code_ioctl(
79 mcb_state_t *state,
80 caddr_t arg,
81 int mode)
82 {
83 bmem_trans_desk_t mp_driver_code;
84 int rval = 0;
85
86 if (ddi_copyin(arg, (caddr_t)&mp_driver_code,
87 sizeof (bmem_trans_desk_t)) /*,mode*/) {
88 ME90_LOG(state, ME90_DL_ERROR,
89 "mckk_load_mp_drv_code_ioctl ddi_copyin failed\n"
90 );
91 return (EFAULT);
92 }
93 ME90_LOG(state, ME90_DL_TRACE,
94 "mckk_load_mp_drv_code_ioctl from 0x%08x to 0x%08x"
95 " of BMEM size 0x%x bytes\n",
96 mp_driver_code.mem_address,
97 mp_driver_code.mp_bmem_address,
98 mp_driver_code.byte_size);
99 mutex_enter(&state->mutex); /* start MUTEX */
100 rval = me90_bmem_data_transfer(state,&mp_driver_code,1,mode,1,NULL,NULL);
101 if (rval != 0) {
102 mutex_exit(&state->mutex); /* end MUTEX */
103 ME90_LOG(state, ME90_DL_ERROR,
104 "mckk_load_mp_drv_code_ioctl BMEM load failed\n");
105 return rval;
106 }
107 state -> mp_drv_loaded = 1;
108 mutex_exit(&state->mutex); /* end MUTEX */
109 ME90_LOG(state, ME90_DL_TRACE,
110 "mckk_load_mp_drv_code_ioctl succeeded\n");
111 return 0;
112 }
113
114 /*
115 * Startup MP (driver ur any other code)
116 */
117
118 /*ARGSUSED*/
119 static int mckk_startup_mp_ioctl(
120 mcb_state_t *state,
121 int cmd,
122 caddr_t arg,
123 int mode)
124 {
125 int rval = 0;
126
127 if (arg != NULL) {
128 mutex_enter(&state->mutex); /* start MUTEX */
129 if (ddi_copyin(arg, (caddr_t) &state -> mp_init_code,
130 sizeof (bmem_trans_desk_t)/*, mode*/)) {
131 mutex_exit(&state->mutex); /* end MUTEX */
132 ME90_LOG(state, ME90_DL_ERROR,
133 "mckk_startup_mp_ioctl ddi_copyin failed for "
134 "MP init code desk\n");
135 return (EFAULT);
136 }
137 mutex_exit(&state->mutex); /* end MUTEX */
138 if (state -> mp_init_code.byte_size > MP_INIT_AREA_BMEM_SIZE) {
139 ME90_LOG(state, ME90_DL_ERROR,
140 "mckk_startup_mp_ioctl too long MP init code "
141 "%x > %x\n",
142 state -> mp_init_code.byte_size,
143 MP_INIT_AREA_BMEM_SIZE);
144 return (EINVAL);
145 }
146 ME90_LOG(state, ME90_DL_TRACE,
147 "mckk_startup_mp_ioctl MP init code load from 0x%08x "
148 "to 0x%08x of BMEM size 0x%x bytes\n",
149 state -> mp_init_code.mem_address,
150 state -> mp_init_code.mp_bmem_address,
151 state -> mp_init_code.byte_size);
152 } else {
153 ME90_LOG(state, ME90_DL_TRACE,
154 "mckk_startup_mp_ioctl started to load MP ROM"
155 " driver\n");
156 }
157 rval = me90_startup_mp(state, cmd, mode);
158 if (rval != 0) {
159 ME90_LOG(state, ME90_DL_TRACE,
160 "mckk_startup_mp_ioctl MP driver init failed\n");
161 } else {
162 ME90_LOG(state, ME90_DL_TRACE,
163 "mckk_startup_mp_ioctl MP driver init succeeded\n");
164 }
165 return (rval);
166 }
167
168 /*
169 * Reset MP of module
170 */
171 /*ARGSUSED*/
172 static int mckk_reset_mp_ioctl(
173 mcb_state_t *state,
174 int clean_bmem)
175 {
176 int rval = 0;
177
178 ME90_LOG(state, ME90_DL_TRACE,"mckk_reset_mp_ioctl started\n");
179 mutex_enter(&state->mutex); /* start MUTEX */
180 rval = me90_reset_mp(state, 1, clean_bmem);
181 mutex_exit(&state->mutex); /* end MUTEX */
182 if (rval != 0) {
183 ME90_LOG(state, ME90_DL_TRACE,
184 "mckk_reset_mp_ioctl finished with errors\n");
185 } else {
186 ME90_LOG(state, ME90_DL_TRACE,
187 "mckk_reset_mp_ioctl succeeded\n");
188 }
189 return 0;
190 }
191
192 /*
193 * Reset MP of module
194 */
195 /*ARGSUSED*/
196 static int mckk_set_mp_state_ioctl(
197 mcb_state_t *state,
198 int mp_state)
199 {
200 int rval = 0;
201
202 ME90_LOG(state, ME90_DL_TRACE,"mckk_set_mp_state_ioctl started\n");
203 mutex_enter(&state->mutex); /* start MUTEX */
204 if (mp_state & CLEAN_BMEM_MP_STATE)
205 me90_clean_base_memory(state);
206 if (mp_state & HALTED_MP_STATE)
207 rval = me90drv_reset_general_regs(state,1);
208 else
209 rval = me90drv_reset_general_regs(state,2);
210 mutex_exit(&state->mutex); /* end MUTEX */
211 if (rval != 0) {
212 ME90_LOG(state, ME90_DL_TRACE,
213 "mckk_set_mp_state_ioctl finished with errors\n");
214 } else {
215 ME90_LOG(state, ME90_DL_TRACE,
216 "mckk_set_mp_state_ioctl succeeded\n");
217 }
218 return 0;
219 }
220
221 /*
222 * Get driver modes and state info
223 */
224 /*ARGSUSED*/
225 static int mckk_get_driver_info_ioctl(
226 mcb_state_t *state,
227 caddr_t arg,
228 int mode)
229 {
230 int rval = 0;
231 mcb_drv_info_t driver_info;
232 #ifdef _MP_TIME_USE_
233 drv_intercom_t *drv_communication = NULL;
234 #endif /* _MP_TIME_USE_ */
235
236 ME90_LOG(state, ME90_DL_TRACE,
237 "mckk_get_driver_info_ioctl started\n");
238 #ifdef _MP_TIME_USE_
239 drv_communication =
240 (drv_intercom_t *) &state -> MC_BMEM[TR_CNTR_BUF_BMEM_ADDR];
241 #endif /* _MP_TIME_USE_ */
242 driver_info.sbus_clock_freq = me90_sbus_clock_freq;
243 driver_info.sbus_nsec_cycle = me90_sbus_nsec_cycle;
244 driver_info.mp_clock_freq = me90_mp_clock_freq;
245 driver_info.mp_nsec_cycle = me90_mp_nsec_cycle;
246 driver_info.device_type = state -> type_unit;
247 driver_info.mp_rom_drv_enable = state -> mp_rom_drv_enable;
248 #ifdef _MP_TIME_USE_
249 READ_MP_TIME(driver_info.cur_hr_time);
250 #else
251 driver_info.cur_hr_time = ddi_gethrtime();
252 #endif /* _MP_TIME_USE_ */
253 if (ddi_copyout((caddr_t) & driver_info, arg,
254 sizeof (mcb_drv_info_t)/*, mode*/)) {
255 ME90_LOG(state, ME90_DL_ERROR,
256 "mckk_get_driver_info_ioctl: ddi_copyout failed\n");
257 rval = EFAULT;
258 }
259 if (rval != 0) {
260 ME90_LOG(state, ME90_DL_TRACE,
261 "mckk_get_driver_info_ioctl: finished\n");
262 } else {
263 ME90_LOG(state, ME90_DL_TRACE,
264 "mckk_get_driver_info_ioctl succeeded\n");
265 }
266 return rval;
267 }
268
269 /*
270 * Set locking of reset module on error
271 */
272 /*ARGSUSED*/
273 static int mckk_lock_reset_module_on_error_ioctl(mcb_state_t *state)
274 {
275 int rval = 0;
276 mc_wr_reg_t tlrm_write_value;
277
278 ME90_LOG(state, ME90_DL_TRACE,
279 "mckk_lock_reset_module_on_error_ioctl started\n");
280 tlrm_write_value.RGEN_write = 0;
281 tlrm_write_value.TLRM_write = 1;
282 #ifndef WITHOUT_TWISTING
283 b2l_convertor_off(state->dip);
284 #endif
285 state->MC_CNTR_ST_REGS->MC_TLRM_write =
286 tlrm_write_value.RGEN_write;
287 #ifndef WITHOUT_TWISTING
288 b2l_convertor_on(state->dip);
289 #endif
290 state -> set_tlrm = 1;
291 ME90_LOG(state, ME90_DL_TRACE,
292 "mckk_lock_reset_module_on_error_ioctl succeeded\n");
293 return rval;
294 }
295
296 /*
297 * Reset locking of reset module on error
298 */
299 /*ARGSUSED*/
300 static int mckk_unlock_reset_module_on_error_ioctl(mcb_state_t *state)
301 {
302 int rval = 0;
303 mc_wr_reg_t tlrm_write_value;
304
305 ME90_LOG(state, ME90_DL_TRACE,
306 "mckk_unlock_reset_module_on_error_ioctl started\n");
307 tlrm_write_value.RGEN_write = 0;
308 tlrm_write_value.TLRM_write = 0;
309 #ifndef WITHOUT_TWISTING
310 b2l_convertor_off(state->dip);
311 #endif
312 state -> MC_CNTR_ST_REGS -> MC_TLRM_write =
313 tlrm_write_value.RGEN_write;
314 #ifndef WITHOUT_TWISTING
315 b2l_convertor_on(state->dip);
316 #endif
317 state -> set_tlrm = 0;
318 ME90_LOG(state, ME90_DL_TRACE,
319 "mckk_unlock_reset_module_on_error_ioctl succeeded\n");
320 return rval;
321 }
322
323 /*
324 * Write register of channel adapter
325 */
326 /*ARGSUSED*/
327 static int mckk_write_adapter_reg_ioctl(
328 mcb_state_t *state,
329 caddr_t arg,
330 int mode)
331 {
332 dev_reg_spec_t device_reg_write_args;
333 mp_drv_args_t device_reg_access_args;
334 int rval = 0;
335
336 if (ddi_copyin(arg, (caddr_t) &device_reg_write_args,
337 sizeof (dev_reg_spec_t)/*, mode*/)) {
338 ME90_LOG(state, ME90_DL_ERROR,
339 "mckk_write_adapter_reg_ioctl: ddi_copyin failed\n");
340 return EFAULT;
341 }
342 ME90_LOG(state, ME90_DL_TRACE,
343 "mckk_write_adapter_reg_ioctl started\n");
344 device_reg_access_args.dev_adapter_access.address =
345 device_reg_write_args.address;
346 device_reg_access_args.dev_adapter_access.reg_value =
347 device_reg_write_args.reg_value;
348 rval = me90drv_submit_mp_task(state,device_adapter_write_mp_task,
349 &device_reg_access_args, 0, NULL, NULL, 0);
350 if (rval != 0) {
351 ME90_LOG(state, ME90_DL_TRACE,
352 "mckk_write_adapter_reg_ioctl failed\n");
353 return rval;
354 }
355 ME90_LOG(state, ME90_DL_TRACE,
356 "mckk_write_adapter_reg_ioctl finished\n");
357 return 0;
358 }
359
360 /*
361 * Read register of channel adapter
362 */
363 /*ARGSUSED*/
364 static int mckk_read_adapter_reg_ioctl(
365 mcb_state_t *state,
366 caddr_t arg,
367 int mode)
368 {
369 dev_reg_spec_t device_reg_read_args;
370 mp_drv_args_t device_reg_access_args;
371 sparc_drv_args_t access_results;
372 int rval = 0;
373
374 if (ddi_copyin(arg, (caddr_t) &device_reg_read_args,
375 sizeof (dev_reg_spec_t)/*, mode*/)) {
376 ME90_LOG(state, ME90_DL_ERROR,
377 "mckk_read_adapter_reg_ioctl: ddi_copyin failed\n");
378 return EFAULT;
379 }
380 ME90_LOG(state, ME90_DL_TRACE,
381 "mckk_read_adapter_reg_ioctl started\n");
382 device_reg_access_args.dev_adapter_access.address =
383 device_reg_read_args.address;
384 device_reg_access_args.dev_adapter_access.reg_value = 0;
385 device_reg_read_args.mp_error_code = 0;
386 rval = me90drv_submit_mp_task(state,device_adapter_read_mp_task,
387 &device_reg_access_args, 0, NULL, &access_results, 0);
388 device_reg_read_args.reg_value =
389 device_reg_access_args.dev_adapter_access.reg_value;
390 if (rval != 0) {
391 ME90_LOG(state, ME90_DL_TRACE,
392 "mckk_read_adapter_reg_ioctl failed\n");
393 } else if (access_results.reg_read_results.mp_error_code != 0) {
394 rval = EINVAL;
395 device_reg_read_args.mp_error_code =
396 access_results.reg_read_results.mp_error_code;
397 ME90_LOG(state, ME90_DL_TRACE,
398 "mckk_read_adapter_reg_ioctl failed with error"
399 " detected by MP driver %d\n",
400 access_results.reg_read_results.mp_error_code);
401 }
402 if (ddi_copyout((caddr_t) &device_reg_read_args, arg,
403 sizeof (dev_reg_spec_t)/*, mode*/)) {
404 ME90_LOG(state, ME90_DL_ERROR,
405 "mckk_read_adapter_reg_ioctl: ddi_copyout failed\n");
406 return EFAULT;
407 }
408 ME90_LOG(state, ME90_DL_TRACE,
409 "mckk_read_adapter_reg_ioctl finished\n");
410 return rval;
411 }
412
413 /*
414 * Set driver general modes
415 */
416 /*ARGSUSED*/
417 static int mckk_set_drv_general_mode_ioctl(
418 mcb_state_t *state,
419 int drv_mode_to_set)
420 {
421 ME90_LOG(state, ME90_DL_TRACE,
422 "mckk_set_drv_general_mode_ioctl to 0x%x\n",
423 drv_mode_to_set);
424 mutex_enter(&state->mutex); /* start MUTEX */
425 state -> drv_general_modes |= drv_mode_to_set;
426 mutex_exit(&state->mutex); /* end MUTEX */
427 ME90_LOG(state, ME90_DL_TRACE,
428 "mckk_set_drv_general_mode_ioctl succeeded\n");
429 return 0;
430 }
431
432 /*
433 * Reset driver general modes
434 */
435 /*ARGSUSED*/
436 static int mckk_reset_drv_general_mode_ioctl(
437 mcb_state_t *state,
438 int drv_mode_to_reset)
439 {
440 ME90_LOG(state, ME90_DL_TRACE,
441 "mckk_reset_drv_general_mode_ioctl to 0x%x\n",
442 drv_mode_to_reset);
443 mutex_enter(&state->mutex); /* start MUTEX */
444 state -> drv_general_modes &= ~drv_mode_to_reset;
445 mutex_exit(&state->mutex); /* end MUTEX */
446 ME90_LOG(state, ME90_DL_TRACE,
447 "mckk_reset_drv_general_mode_ioctl succeeded\n");
448 return 0;
449 }
450
451 /*
452 * Get driver general modes
453 */
454 /*ARGSUSED*/
455 static int mckk_get_drv_general_mode_ioctl(
456 mcb_state_t *state,
457 caddr_t arg,
458 int mode)
459 {
460 ME90_LOG(state, ME90_DL_TRACE,
461 "mckk_get_drv_general_mode_ioctl started\n");
462 if (ddi_copyout((caddr_t) & state -> drv_general_modes, arg,
463 sizeof (state -> drv_general_modes)/*, mode*/)) {
464 ME90_LOG(state, ME90_DL_ERROR,
465 "mckk_get_drv_general_mode_ioctl: ddi_copyout "
466 "failed\n");
467 return EFAULT;
468 }
469 ME90_LOG(state, ME90_DL_TRACE,
470 "mckk_ioctl get current driver general mode flags"
471 " succeeded\n");
472 return 0;
473 }
474
475 /*
476 * Put driver general modes
477 */
478 /*ARGSUSED*/
479 static int mckk_put_drv_general_mode_ioctl(
480 mcb_state_t *state,
481 int drv_modes_to_put)
482 {
483
484 ME90_LOG(state, ME90_DL_TRACE,
485 "mckk_put_drv_general_mode_ioctl to 0x%x\n",
486 drv_modes_to_put);
487 mutex_enter(&state->mutex); /* start MUTEX */
488 state -> drv_general_modes = drv_modes_to_put;
489 mutex_exit(&state->mutex); /* end MUTEX */
490 ME90_LOG(state, ME90_DL_TRACE,
491 "mckk_put_drv_general_mode_ioctl succeeded\n");
492 return 0;
493 }
494
495 /*
496 * Wait for asynchronous transfer finish
497 */
498 /*ARGSUSED*/
499 static int mckk_wait_for_async_trans_ioctl(
500 mcb_state_t *state,
501 int channel,
502 caddr_t arg,
503 int mode)
504 {
505 me90drv_chnl_state_t *channel_state = NULL;
506 me90drv_aiotrans_wait_t waiting_request;
507 caddr_t *user_trans_res_info_pp = NULL;
508 me90drv_trans_buf_t *trans_buf_p = NULL;
509 me90drv_trans_spec_t *transfer_spec = NULL;
510 caddr_t user_results_p = NULL;
511 int rval = 0;
512
513 channel_state = &state -> all_channels_state[channel];
514 if (ddi_copyin(arg, (caddr_t) &waiting_request,
515 sizeof (me90drv_aiotrans_wait_t)/*, mode*/)) {
516 ME90_LOG(state, ME90_DL_ERROR,
517 "mckk_wait_for_async_trans_ioctl: ddi_copyin "
518 "failed in the channel %d\n", channel);
519 return EFAULT;
520 }
521 ME90_LOG(state, ME90_DL_TRACE,
522 "mckk_wait_for_async_trans_ioctl in the "
523 "channel %d with waiting time %d usec\n", channel,
524 waiting_request.waiting_time);
525 user_trans_res_info_pp = waiting_request.trans_res_info_pp;
526 if (user_trans_res_info_pp == NULL) {
527 ME90_LOG(state, ME90_DL_ERROR,
528 "mckk_wait_for_async_trans_ioctl: NULL pointer of I/O "
529 "request results info in the channel %d\n", channel);
530 return EINVAL;
531 }
532 rval = me90_wait_async_trans(state, channel,
533 waiting_request.waiting_time, &trans_buf_p);
534 if (rval == 0) {
535 #if defined(__BLOCK_BUFFER_USE__)
536 if (trans_buf_p -> trans_buf_desc.drv_buf_used)
537 transfer_spec = (me90drv_trans_spec_t *)
538 trans_buf_p -> drv_buf_p ->
539 transfer_spec;
540 else
541 /* transfer_spec = trans_buf_p ->
542 trans_buf_desc.bp -> b_private;*/
543 transfer_spec = trans_buf_p ->
544 trans_buf_desc.uio_p -> transfer_spec;
545 #else /* ! __BLOCK_BUFFER_USE__ */
546 transfer_spec = trans_buf_p -> transfer_spec;
547 #endif /* __BLOCK_BUFFER_USE__ */
548 user_results_p = transfer_spec -> user_results_p;
549 rval = me90drv_set_trans_results(state,
550 transfer_spec -> trans_res_info,
551 NULL,
552 (me90drv_trans_info_t *) user_results_p,
553 mode);
554 }
555 if (ddi_copyout((caddr_t) &user_results_p,
556 (caddr_t) user_trans_res_info_pp,
557 sizeof (caddr_t)/*, mode*/)) {
558 ME90_LOG(state, ME90_DL_ERROR,
559 "mckk_wait_for_async_trans_ioctl: ddi_copyout failed "
560 "for waiting in the channel %d\n", channel);
561 rval = EFAULT;
562 }
563 if (trans_buf_p != NULL)
564 me90drv_release_async_trans(state, channel, trans_buf_p);
565 ME90_LOG(state, ME90_DL_TRACE,
566 "mckk_wait_for_async_trans_ioctl in the"
567 " channel %d completed with res %d\n", channel, rval);
568 return rval;
569 }
570
571 /*
572 * Wait for transfer in progress
573 */
574 /*ARGSUSED*/
575 static int
576 mckk_wait_for_trans_in_progress_ioctl(
577 mcb_state_t *state,
578 int channel,
579 caddr_t arg,
580 int mode)
581 {
582 me90drv_chnl_state_t *channel_state = NULL;
583 clock_t timeout_usec = (clock_t) arg;
584 clock_t cur_clock_ticks = 0;
585 clock_t timeout_clock_ticks = 0;
586 int rval = 0;
587
588 ME90_LOG(state, ME90_DL_TRACE,
589 "mckk_wait_for_trans_in_progress_ioctl wait for transfer in "
590 "progress for channel %d and time %d usec\n",
591 channel, timeout_usec);
592 channel_state = &state -> all_channels_state[channel];
593 drv_getparm(LBOLT,(u_long *) &cur_clock_ticks);
594 timeout_clock_ticks =
595 cur_clock_ticks + drv_usectohz(timeout_usec);
596 mutex_enter(&state->mutex); /* start MUTEX */
597 while (1) {
598 rval = 0;
599 if (channel_state -> in_progress) {
600 break;
601 }
602 rval = cv_timedwait(&state -> trans_start_cv, &state->mutex,
603 timeout_clock_ticks);
604 if (rval < 0) {
605 rval = ETIME;
606 break;
607 }
608 }
609 mutex_exit(&state->mutex); /* end MUTEX */
610 if (rval != 0) {
611 ME90_LOG(state, ME90_DL_TRACE,
612 "mckk_ioctl wait for transfer in progress timeouted "
613 "for channel %d error %d\n", channel, rval);
614 } else {
615 ME90_LOG(state, ME90_DL_TRACE,
616 "mckk_ioctl wait for transfer in progress successed "
617 "for channel %d\n", channel);
618 }
619 return rval;
620 }
621
622 /*
623 * Output last transfer state and results info
624 */
625 /*ARGSUSED*/
626 static int
627 mckk_output_last_trans_state_ioctl(
628 mcb_state_t *state,
629 int channel)
630 {
631 me90drv_chnl_state_t *channel_state = NULL;
632
633 ME90_LOG(state, ME90_DL_TRACE,
634 "mckk_output_last_trans_state_ioctl started\n");
635 channel_state = &state -> all_channels_state[channel];
636 if (channel_state -> last_term_trans_buf != NULL)
637 me90_output_trans_state(state,
638 channel_state -> last_term_trans_buf);
639 else
640 ME90_LOG(state, ME90_DL_ERROR,
641 "mckk_output_last_trans_state_ioctl: empty last "
642 "transfer buf pointer\n");
643 ME90_LOG(state, ME90_DL_TRACE,
644 "mckk_output_last_trans_state_ioctl finished\n");
645 return 0;
646 }
647
648 /*
649 * Wait for transfer in progress
650 */
651 /*ARGSUSED*/
652 static int
653 mckk_restart_board_ioctl(mcb_state_t *state)
654 {
655 int rval = 0;
656 me90drv_rd_reg_t gen_reg_state;
657
658 ME90_LOG(state, ME90_DL_TRACE, "mckk_restart_board_ioctl started\n");
659 gen_reg_state.ME90DRV_RGEN_read = 0;
660 rval = me90_retrieve_trans_mode(state, 0, 1, gen_reg_state);
661 if (rval != 0) {
662 ME90_LOG(state, ME90_DL_TRACE,
663 "mckk_restart_board_ioctl cannot restart the board\n");
664 } else {
665 ME90_LOG(state, ME90_DL_TRACE,
666 "mckk_restart_board_ioctl succeeded\n");
667 }
668 return rval;
669 }
670
671 /*
672 * Driver ioctl entry point
673 */
674 /*ARGSUSED*/
675
676 static int
677 mckk_ioctl ( struct inode *inode, struct file *file,
678 unsigned int cmd, unsigned long arg)
679 {
680 mcb_state_t *state;
681 dev_t dev;
682 int instance = 0;
683 int channel;
684 int mode = 0;
685 int rval = 0;
686 #ifdef _MP_TIME_USE_
687 drv_intercom_t * drv_communication = NULL;
688 u_int * cur_mp_time = NULL;
689 #endif /* _MP_TIME_USE_ */
690
691 ME90_LOG(NULL, ME90_DL_TRACE,"mckk_ioctl started for instance %d with cmd 0x%x\n", instance, cmd);
692 dev = MKDEV(mckk_major, iminor(inode));
693 instance = MCB_INST(dev);
694 channel = MCB_CHAN(dev);
695 state = mckk_states[instance];
696 if (state == NULL) {
697 printk("~%s~_ioctl: unattached instance %d\n", mod_name, instance);
698 return (ENXIO);
699 };
700 #ifdef _MP_TIME_USE_
701 drv_communication =
702 (drv_intercom_t *) &state -> MC_BMEM[TR_CNTR_BUF_BMEM_ADDR];
703 cur_mp_time = &drv_communication -> processing_time.mp_timer;
704 #endif /* _MP_TIME_USE_ */
705 switch (cmd) {
706 case MCBIO_LOAD_MP_DRV_CODE :
707 return mckk_load_mp_drv_code_ioctl(state,
708 (caddr_t)arg, mode);
709 case MCBIO_STARTUP_MP_DRV :
710 case MCBIO_STARTUP_MP_ROM_DRV :
711 case MCBIO_STARTUP_MP_CODE :
712 return mckk_startup_mp_ioctl(state, cmd, (caddr_t)arg,
713 mode);
714 case MCBIO_RESET_MP :
715 return mckk_reset_mp_ioctl(state, arg);
716 case MCBIO_SET_MP_STATE :
717 return mckk_set_mp_state_ioctl(state, arg);
718 case MCBIO_GET_DRIVER_INFO :
719 return mckk_get_driver_info_ioctl(state, (caddr_t)arg,
720 mode);
721 case MCBIO_LOCK_RESET_MODULE_ON_ERROR :
722 return mckk_lock_reset_module_on_error_ioctl(state);
723 case MCBIO_UNLOCK_RESET_MODULE_ON_ERROR :
724 return mckk_unlock_reset_module_on_error_ioctl(state);
725
726 case MCBIO_GET_DRIVER_TRACE_MSG :
727 return mckk_get_driver_trace_ioctl(state, (caddr_t)arg,
728 mode);
729 case MCBIO_WRITE_DEV_ADAPTER_REG :
730 return mckk_write_adapter_reg_ioctl(state, (caddr_t)arg,
731 mode);
732 case MCBIO_READ_DEV_ADAPTER_REG :
733 return mckk_read_adapter_reg_ioctl(state, (caddr_t)arg,
734 mode);
735 case MCBIO_SET_DRV_GENERAL_MODE :
736 return mckk_set_drv_general_mode_ioctl(state, arg);
737 case MCBIO_RESET_DRV_GENERAL_MODE :
738 return mckk_reset_drv_general_mode_ioctl(state, arg);
739 case MCBIO_GET_DRV_GENERAL_MODES :
740 return mckk_get_drv_general_mode_ioctl(state,
741 (caddr_t)arg, mode);
742 case MCBIO_PUT_DRV_GENERAL_MODES :
743 return mckk_put_drv_general_mode_ioctl(state, arg);
744 case MCBIO_SPECIFIED_TRANSFER :
745 {
746 trans_spec_t user_transfer_spec;
747 trans_spec_t transfer_spec;
748 trans_spec_t *transfer_spec_p;
749 trans_info_t *user_trans_res_info = NULL;
750 trans_info_t drv_trans_res_info;
751 trans_info_t *drv_trans_res_info_p;
752 int delete_kmem_bufs = 0;
753 int set_rval = 0;
754 iovec_t iov;
755 uio_t uio;
756 iovec_t *iov_p = NULL;
757 uio_t *uio_p = NULL;
758 #ifdef DEBUG
759 char * io_mode = NULL;
760 char * dev_access_mode = NULL;
761 #endif /* DEBUG */
762 #ifdef _MP_TIME_USE_
763 u_int req_receive_time = 0;
764 #else
765 hrtime_t req_receive_time = ddi_gethrtime();
766 #endif /* _MP_TIME_USE_ */
767
768 #ifdef _MP_TIME_USE_
769 READ_MP_TIME(req_receive_time);
770 #endif /* _MP_TIME_USE_ */
771
772 if (ddi_copyin((caddr_t)arg, (caddr_t) & user_transfer_spec,
773 sizeof (trans_spec_t)/*,
774 mode*/
775 )
776 )
777 {
778 ME90_LOG(state, ME90_DL_ERROR,
779 "mckk_ioctl ddi_copyin failed for transfer specification\n"
780 );
781 return (EFAULT);
782 }
783 #ifdef DEBUG
784 if (user_transfer_spec.io_mode_flags & DMA_TRANSFER_IO_MODE)
785 io_mode = "DMA";
786 else if (user_transfer_spec.io_mode_flags & PROG_TRANSFER_IO_MODE)
787 io_mode = "PROG";
788 else if (user_transfer_spec.io_mode_flags & PROG1_TRANSFER_IO_MODE)
789 io_mode = "PROG1";
790 else if (user_transfer_spec.io_mode_flags & BMEM_TRANSFER_IO_MODE)
791 io_mode = "BMEM";
792 else
793 io_mode = "???";
794 if (user_transfer_spec.dev_access_mode == DIRECT_DEV_ACCESS_MODE)
795 dev_access_mode = "DIRECT";
796 else if (user_transfer_spec.dev_access_mode ==
797 WITH_DEMAND_DEV_ACCESS_MODE)
798 dev_access_mode = "with DRQ";
799 else if (user_transfer_spec.dev_access_mode ==
800 ON_DEMAND_DEV_ACCESS_MODE)
801 dev_access_mode = "on DRQ";
802 else
803 dev_access_mode = "???";
804
805 ME90_LOG(state, ME90_DL_TRACE,
806 "mckk_ioctl specified transfer addr 0x%lx len 0x%lx %s %s"
807 " %s burst size 0x%02x"
808 " repeat %d\n",
809 user_transfer_spec.buf_base,
810 user_transfer_spec.buf_byte_size,
811 (user_transfer_spec.read_write_flag == B_READ) ? "READ" :
812 "WRITE",
813 io_mode,
814 dev_access_mode,
815 user_transfer_spec.burst_sizes,
816 user_transfer_spec.repeation_num
817 );
818 #endif /* DEBUG */
819 if ((user_transfer_spec.read_write_flag & B_READ) == 0 &&
820 (user_transfer_spec.read_write_flag & B_WRITE) == 0
821 )
822 {
823 ME90_LOG(state, ME90_DL_ERROR,
824 "mckk_ioctl invalid read/write flag %d\n",
825 user_transfer_spec.read_write_flag
826 );
827 return EINVAL;
828 }
829 if (!(user_transfer_spec.io_mode_flags & DMA_TRANSFER_IO_MODE) &&
830 !(user_transfer_spec.io_mode_flags & PROG_TRANSFER_IO_MODE) &&
831 !(user_transfer_spec.io_mode_flags & PROG1_TRANSFER_IO_MODE) &&
832 !(user_transfer_spec.io_mode_flags & BMEM_TRANSFER_IO_MODE)
833 )
834 {
835 ME90_LOG(state, ME90_DL_ERROR,
836 "mckk_ioctl invalid I/O transfer mode %d\n",
837 user_transfer_spec.io_mode_flags
838 );
839 return EINVAL;
840 }
841 if (user_transfer_spec.dev_access_mode != DIRECT_DEV_ACCESS_MODE
842 &&
843 user_transfer_spec.dev_access_mode != WITH_DEMAND_DEV_ACCESS_MODE
844 &&
845 user_transfer_spec.dev_access_mode != ON_DEMAND_DEV_ACCESS_MODE
846 )
847 {
848 ME90_LOG(state, ME90_DL_ERROR,
849 "mckk_ioctl invalid I/O device access mode %d\n",
850 user_transfer_spec.dev_access_mode
851 );
852 return EINVAL;
853 }
854 if (user_transfer_spec.burst_sizes == 0)
855 user_transfer_spec.burst_sizes = MCB_ENABLE_BURST_SIZES;
856 if ((user_transfer_spec.burst_sizes & MCB_ENABLE_BURST_SIZES) == 0)
857 {
858 ME90_LOG(state, ME90_DL_ERROR,
859 "mckk_ioctl empty mask of allowed 0x%02x"
860 " & enable 0x%02x burst sizes\n",
861 user_transfer_spec.burst_sizes,
862 MCB_ENABLE_BURST_SIZES
863 );
864 return EINVAL;
865 }
866 user_trans_res_info = user_transfer_spec.trans_res_info;
867 if (user_transfer_spec.async_trans) {
868 if (user_trans_res_info == NULL) {
869 ME90_LOG(state, ME90_DL_ERROR,
870 "mckk_ioctl cannot do asynchronous "
871 "transfer with NULL transfer results "
872 "info pointer\n");
873 return EINVAL;
874 }
875 /* Memory allocation */
876 transfer_spec_p = kmem_alloc(sizeof(trans_spec_t),
877 KM_NOSLEEP);
878 if (transfer_spec_p == NULL) {
879 ME90_LOG(state, ME90_DL_ERROR,
880 "mckk_ioctl cannot allocate kernel memory for"
881 " simple transfer specifications area\n");
882 return EINVAL;
883 }
884 drv_trans_res_info_p = kmem_alloc(sizeof(trans_info_t),
885 KM_NOSLEEP);
886 if (drv_trans_res_info_p == NULL) {
887 kmem_free(transfer_spec_p, sizeof(trans_spec_t));
888 ME90_LOG(state, ME90_DL_ERROR,
889 "mckk_ioctl cannot allocate kernel memory for"
890 " simple transfer results area\n");
891 return EINVAL;
892 }
893 iov_p = kmem_alloc(sizeof(iovec_t), KM_NOSLEEP);
894 if (iov_p == NULL) {
895 kmem_free(transfer_spec_p, sizeof(trans_spec_t));
896 kmem_free(drv_trans_res_info_p, sizeof(trans_info_t));
897 ME90_LOG(state, ME90_DL_ERROR,
898 "mckk_ioctl cannot allocate kernel memory for"
899 " iov structure area\n");
900 return EINVAL;
901 }
902 uio_p = kmem_alloc(sizeof(uio_t), KM_NOSLEEP);
903 if (uio_p == NULL) {
904 kmem_free(transfer_spec_p, sizeof(trans_spec_t));
905 kmem_free(drv_trans_res_info_p, sizeof(trans_info_t));
906 kmem_free(iov_p, sizeof(iovec_t));
907 ME90_LOG(state, ME90_DL_ERROR,
908 "mckk_ioctl cannot allocate kernel memory for"
909 " uio structure area\n");
910 return EINVAL;
911 }
912
913 } else {
914 transfer_spec_p = &transfer_spec;
915 drv_trans_res_info_p = &drv_trans_res_info;
916 iov_p = &iov;
917 uio_p = &uio;
918 }
919 /*
920 * Checking if buffer block in user or in kernel space... If user block then
921 * allocation kernel block for coping the first to the one. Later may
922 * be used ddi mapping user memory block to the kernel
923 * address space via pgd, pmd, pte (pgd, pmhd, pmld, pte in e2k terms)
924 */
925 /* if ((unsigned long)user_transfer_spec.buf_base < TASK_SIZE) {
926 // transfer_spec_p -> buf_base = kmalloc(sizeof(user_transfer_spec.buf_byte_size), GFP_KERNEL);
927 transfer_spec_p -> buf_base = kmalloc(user_transfer_spec.buf_byte_size, GFP_KERNEL);
928 if (transfer_spec_p -> buf_base <= 0) {
929 printk ("mckk_ioctl: Error allocated memory.
930 User memory block cannot be mapping to kernel... Failed\n");
931 return EFAULT;
932 }
933 if (ddi_copyin(user_transfer_spec.buf_base, transfer_spec_p -> buf_base,
934 user_transfer_spec.buf_byte_size )) {
935 kfree(transfer_spec_p -> buf_base);
936 printk ("mckk_ioctl: Error copy_from_user\n");
937 return EFAULT;
938 }
939 } else {
940 transfer_spec_p -> buf_base = user_transfer_spec.buf_base;
941 }
942 */
943 transfer_spec_p -> buf_base = user_transfer_spec.buf_base;
944 transfer_spec_p -> buf_byte_size = user_transfer_spec.buf_byte_size;
945 transfer_spec_p -> read_write_flag = user_transfer_spec.read_write_flag;
946 transfer_spec_p -> async_trans = user_transfer_spec.async_trans;
947 transfer_spec_p -> io_mode_flags = user_transfer_spec.io_mode_flags;
948 transfer_spec_p -> dev_access_mode = user_transfer_spec.dev_access_mode;
949 transfer_spec_p -> burst_sizes = user_transfer_spec.burst_sizes;
950 transfer_spec_p -> repeation_num = user_transfer_spec.repeation_num;
951 transfer_spec_p -> timer_interval = user_transfer_spec.timer_interval;
952 transfer_spec_p -> data_waiting_time = user_transfer_spec.data_waiting_time;
953 transfer_spec_p -> timing_interval_t0 = user_transfer_spec.timing_interval_t0;
954 transfer_spec_p -> user_results_p = (caddr_t) user_trans_res_info;
955 transfer_spec_p -> trans_res_info = drv_trans_res_info_p;
956 drv_trans_res_info_p -> req_receive_time = req_receive_time;
957 iov_p -> iov_base = user_transfer_spec.buf_base;
958 iov_p -> iov_len = user_transfer_spec.buf_byte_size;
959 memset((caddr_t) uio_p, 0, sizeof (uio_t));
960 uio_p -> uio_iov = iov_p;
961 uio_p -> uio_iovcnt = 1;
962 if ((unsigned long)user_transfer_spec.buf_base < TASK_SIZE)
963 uio_p -> uio_segflg = UIO_USERSPACE;
964 else
965 uio_p -> uio_segflg = UIO_SYSSPACE;
966 uio_p -> uio_resid = iov_p -> iov_len;
967 /* mckk_rdwr for testing only */
968 rval = mcb_rdwr(dev, uio_p,
969 user_transfer_spec.read_write_flag,
970 transfer_spec_p);
971 if (rval != 0)
972 if (user_transfer_spec.async_trans)
973 delete_kmem_bufs = 1;
974 if (user_trans_res_info != NULL)
975 {
976 set_rval = mcb_set_trans_results(state, drv_trans_res_info_p,
977 NULL, user_trans_res_info, mode);
978 if (set_rval != 0)
979 rval = set_rval;
980 }
981 if (rval != 0)
982 ME90_LOG(state, ME90_DL_ERROR,
983 "mckk_ioctl transfer finished with error %d for channel"
984 " %d\n",
985 rval,channel
986 );
987 if (delete_kmem_bufs) {
988 kmem_free(transfer_spec_p, sizeof(trans_spec_t));
989 kmem_free(drv_trans_res_info_p, sizeof(trans_info_t));
990 kmem_free(iov_p, sizeof(iovec_t));
991 kmem_free(uio_p, sizeof(uio_t));
992 }
993
994 /* if ((unsigned long)user_transfer_spec.buf_base < TASK_SIZE && !delete_kmem_bufs) {
995 if (ddi_copyout(transfer_spec_p -> buf_base, user_transfer_spec.buf_base,
996 user_transfer_spec.buf_byte_size )) {
997 printk ("mckk_ioctl: Error copy_to_user\n");
998 }
999 }*/
1000 return rval;
1001 }
1002 case MCBIO_WAIT_FOR_ASYNC_TRANS_END :
1003 return mckk_wait_for_async_trans_ioctl(state, channel,
1004 (caddr_t)arg, mode);
1005 case MCBIO_DRQ_WAITING_TRANSFER_NUM :
1006 {
1007 int cur_transfer_num = 0;
1008 me90drv_chnl_state_t *channel_state = NULL;
1009
1010 ME90_LOG(state, ME90_DL_TRACE,
1011 "mckk_ioctl get transfer num waiting for DRQ channel %d\n",
1012 channel
1013 );
1014 channel_state = &state -> all_channels_state[channel];
1015 mutex_enter(&state->mutex); /* start MUTEX */
1016 cur_transfer_num = channel_state -> drq_queue_size;
1017 if (ddi_copyout((caddr_t) & cur_transfer_num,
1018 (caddr_t) arg,
1019 sizeof (int) /*,
1020 mode */
1021 )
1022 )
1023 {
1024 ME90_LOG(state, ME90_DL_ERROR,
1025 "mckk_ioctl ddi_copyout failed for get waiting DRQ num\n"
1026 );
1027 rval = EFAULT;
1028 }
1029 mutex_exit(&state->mutex); /* end MUTEX */
1030 if (rval != 0)
1031 {
1032 ME90_LOG(state, ME90_DL_TRACE,
1033 "mckk_ioctl get transfer num waiting for DRQ finished "
1034 "with errors\n"
1035 );
1036 }
1037 else
1038 {
1039 ME90_LOG(state, ME90_DL_TRACE,
1040 "mckk_ioctl get transfer num waiting for DRQ successed\n"
1041 );
1042 }
1043 return rval;
1044 }
1045 case MCBIO_SET_MP_TIMER_INTR :
1046 {
1047 mp_tm_intr_set_t mp_timer_intr_set;
1048 mp_intr_spec_t * mp_timer_intr_spec = NULL;
1049 mp_drv_args_t mp_timer_set_args;
1050 int rval = 0;
1051
1052 if (ddi_copyin((caddr_t) arg,
1053 (caddr_t) & mp_timer_intr_set,
1054 sizeof (mp_tm_intr_set_t) /*,
1055 mode*/
1056 )
1057 )
1058 {
1059 ME90_LOG(state, ME90_DL_ERROR,
1060 "mckk_ioctl: ddi_copyin failed for set MP timer intr\n"
1061 );
1062 return EFAULT;
1063 }
1064 ME90_LOG(state, ME90_DL_TRACE,
1065 "mckk_ioctl set MP timer interrupt mode with interval %d"
1066 " max queue size %d\n",
1067 mp_timer_intr_set.interval,
1068 mp_timer_intr_set.max_queue_size
1069 );
1070 if (mp_timer_intr_set.interval <= 0)
1071 mp_timer_intr_set.interval = 1000; /* 1 mlsec */
1072 mutex_enter(&state->mutex); /* start MUTEX */
1073 mp_timer_intr_spec = &state -> mp_timer_intrs;
1074 if (mp_timer_intr_spec -> mp_intr_mode_on == 1)
1075 {
1076 mutex_exit(&state->mutex); /* end MUTEX */
1077 ME90_LOG(state, ME90_DL_ERROR,
1078 "mckk_ioctl: MP timer intr is seted already\n"
1079 );
1080 return EBUSY;
1081 }
1082 mp_timer_intr_spec -> interval = mp_timer_intr_set.interval;
1083 mp_timer_intr_spec -> max_queue_size =
1084 mp_timer_intr_set.max_queue_size;
1085 mp_timer_intr_spec -> losed_intr_num = 0;
1086 mp_timer_intr_spec -> total_intr_num = 0;
1087 mp_timer_intr_spec -> total_request_num = 0;
1088 mp_timer_set_args.mp_timer_set.timer_interval =
1089 mp_timer_intr_set.interval / me90_mp_nsec_cycle * 1000;
1090 rval = submit_mp_task(state,mp_timer_intr_set_mp_task,
1091 &mp_timer_set_args,
1092 1,
1093 NULL,
1094 NULL,
1095 0
1096 );
1097 if (rval == 0)
1098 mp_timer_intr_spec -> mp_intr_mode_on = 1;
1099 mutex_exit(&state->mutex); /* end MUTEX */
1100 if (rval != 0)
1101 {
1102 ME90_LOG(state, ME90_DL_TRACE,
1103 "mckk_ioctl: MP timer intr set failed\n"
1104 );
1105 }
1106 else
1107 {
1108 ME90_LOG(state, ME90_DL_TRACE,
1109 "mckk_ioctl: MP timer intr set successed\n"
1110 );
1111 }
1112 return rval;
1113 }
1114 case MCBIO_RESET_MP_TIMER_INTR :
1115 {
1116 mp_tm_intr_reset_t mp_timer_intr_reset;
1117 mp_intr_spec_t * mp_timer_intr_spec = NULL;
1118 mp_drv_args_t mp_timer_reset_args;
1119 int rval = 0;
1120
1121 ME90_LOG(state, ME90_DL_TRACE,
1122 "mckk_ioctl reset MP timer interrupt mode\n"
1123 );
1124 mutex_enter(&state->mutex); /* start MUTEX */
1125 mp_timer_intr_spec = &state -> mp_timer_intrs;
1126 if (mp_timer_intr_spec -> mp_intr_mode_on != 1)
1127 {
1128 ME90_LOG(state, ME90_DL_ERROR,
1129 "mckk_ioctl: MP timer intr is reseted already\n"
1130 );
1131 }
1132 mp_timer_intr_reset.total_intr_num =
1133 mp_timer_intr_spec -> total_intr_num;
1134 mp_timer_intr_reset.unclaimed_intr_num =
1135 mp_timer_intr_spec -> cur_queue_size;
1136 mp_timer_intr_reset.losed_intr_num =
1137 mp_timer_intr_spec -> losed_intr_num;
1138 mp_timer_reset_args.mp_timer_set.timer_interval = 0;
1139 rval = submit_mp_task(state,mp_timer_intr_set_mp_task,
1140 &mp_timer_reset_args,
1141 1,
1142 NULL,
1143 NULL,
1144 0
1145 );
1146 remove_mp_timer_intr(state);
1147 mp_timer_intr_spec -> mp_intr_mode_on = -1;
1148 mutex_exit(&state->mutex); /* end MUTEX */
1149 if (ddi_copyout((caddr_t) & mp_timer_intr_reset,
1150 (caddr_t) arg,
1151 sizeof (mp_tm_intr_reset_t)/*,
1152 mode*/
1153 )
1154 )
1155 {
1156 ME90_LOG(state, ME90_DL_ERROR,
1157 "mckk_ioctl: ddi_copyout failed for reset MP timer intr\n"
1158 );
1159 rval = EFAULT;
1160 }
1161 if (rval != 0)
1162 {
1163 ME90_LOG(state, ME90_DL_TRACE,
1164 "mckk_ioctl: MP timer intr reset finished\n"
1165 );
1166 }
1167 else
1168 {
1169 ME90_LOG(state, ME90_DL_TRACE,
1170 "mckk_ioctl: MP timer intr reset successed\n"
1171 );
1172 }
1173 return rval;
1174 }
1175 case MCBIO_WAIT_MP_TIMER_INTR :
1176 {
1177 mp_tm_intr_info_t mp_timer_intr_info;
1178 int rval = 0;
1179
1180 #ifdef _MP_TIME_USE_
1181 READ_MP_TIME(mp_timer_intr_info.drv_request_start_time);
1182 #else
1183 mp_timer_intr_info.drv_request_start_time = ddi_gethrtime();
1184 #endif /* _MP_TIME_USE_ */
1185 ME90_LOG(state, ME90_DL_TRACE,
1186 "mckk_ioctl wait for MP timer interrupt mode\n"
1187 );
1188 handle_mp_timer_intr_request(state,&mp_timer_intr_info);
1189 #ifdef _MP_TIME_USE_
1190 READ_MP_TIME(mp_timer_intr_info.drv_request_end_time);
1191 #else
1192 mp_timer_intr_info.drv_request_end_time = ddi_gethrtime();
1193 #endif /* _MP_TIME_USE_ */
1194 if (ddi_copyout((caddr_t) & mp_timer_intr_info,
1195 (caddr_t) arg,
1196 sizeof (mp_tm_intr_info_t)/*,
1197 mode*/
1198 )
1199 )
1200 {
1201 ME90_LOG(state, ME90_DL_ERROR,
1202 "mckk_ioctl: ddi_copyout failed for wait for MP timer"
1203 " intr\n"
1204 );
1205 rval = EFAULT;
1206 }
1207 if (rval != 0)
1208 {
1209 ME90_LOG(state, ME90_DL_TRACE,
1210 "mckk_ioctl: waiting for MP timer intr finished\n"
1211 );
1212 }
1213 else
1214 {
1215 ME90_LOG(state, ME90_DL_TRACE,
1216 "mckk_ioctl: waiting for MP timer intr successed\n"
1217 );
1218 }
1219 return rval;
1220 }
1221
1222 case MCBIO_WAIT_FOR_TRANSFER_IN_PROGRESS :
1223 return mckk_wait_for_trans_in_progress_ioctl(state,
1224 channel, (caddr_t)arg, mode);
1225
1226 case MCBIO_RESET_SBUS_LOGER :
1227 {
1228 mc_wr_reg_t reset_write_value;
1229 int clean_bmem = arg;
1230 int rval = 0;
1231
1232 ME90_LOG(state, ME90_DL_TRACE,
1233 "mckk_ioctl reset SBus loger and log memory\n"
1234 );
1235 reset_write_value.RGEN_write = 0;
1236 #ifndef WITHOUT_TWISTING
1237 b2l_convertor_off(state->dip);
1238 #endif
1239 state -> MC_CNTR_ST_REGS -> MC_TGRM_write =
1240 reset_write_value.RGEN_write;
1241 #ifndef WITHOUT_TWISTING
1242 b2l_convertor_on(state->dip);
1243 #endif
1244 if (clean_bmem)
1245 me90_clean_base_memory(state);
1246 ME90_LOG(state, ME90_DL_TRACE,
1247 "mckk_ioctl: reset SBus loger and log memory successed\n"
1248 );
1249 return rval;
1250 }
1251
1252 case MCBIO_OUT_LAST_TRANS_STATE :
1253 return mckk_output_last_trans_state_ioctl(state,
1254 channel);
1255 case MCBIO_RESTART_BOARD :
1256 return mckk_restart_board_ioctl(state);
1257
1258 case MCBIO_SET_CONNECTION_POLLING :
1259 {
1260 cnct_poll_set_t polling_setup_spec;
1261 int rval = 0;
1262
1263 if (ddi_copyin((caddr_t) arg,
1264 (caddr_t) & polling_setup_spec,
1265 sizeof (cnct_poll_set_t)/*,
1266 mode*/
1267 )
1268 )
1269 {
1270 ME90_LOG(state, ME90_DL_ERROR,
1271 "mckk_ioctl: ddi_copyin failed for set connection"
1272 " polling\n"
1273 );
1274 return EFAULT;
1275 }
1276 ME90_LOG(state, ME90_DL_TRACE,
1277 "mckk_ioctl set connection polling with interval %d"
1278 " and %s in the time %d msec\n",
1279 polling_setup_spec.interval,
1280 (polling_setup_spec.cpu_polling) ? "with CPU polling"
1281 : "without CPU polling",
1282 polling_setup_spec.setup_timeout
1283 );
1284 rval = mcb_set_connection_polling(state, &polling_setup_spec);
1285 ME90_LOG(state, ME90_DL_TRACE,
1286 "mckk_ioctl: set connection polling finished\n"
1287 );
1288 return rval;
1289 }
1290 case MCBIO_RESET_CONNECTION_POLLING :
1291 {
1292 int rval = 0;
1293
1294 ME90_LOG(state, ME90_DL_TRACE,
1295 "mckk_ioctl reset connection polling\n"
1296 );
1297 rval = mcb_reset_connection_polling(state, 0);
1298 ME90_LOG(state, ME90_DL_TRACE,
1299 "mckk_ioctl: reset connection polling finished\n"
1300 );
1301 return rval;
1302 }
1303 case MCBIO_POLL_CONNECTION_STATE :
1304 {
1305 poll_cnct_state_t state_spec;
1306 int rval = 0;
1307 poll_time_info_t drv_time_info;
1308 poll_time_info_t *usr_time_info = NULL;
1309
1310 if (ddi_copyin((caddr_t) arg,
1311 (caddr_t) & state_spec,
1312 sizeof (poll_cnct_state_t) /*,
1313 mode*/
1314 )
1315 )
1316 {
1317 ME90_LOG(state, ME90_DL_ERROR,
1318 "mckk_ioctl: ddi_copyin failed for poll connection state\n"
1319 );
1320 return EFAULT;
1321 }
1322 ME90_LOG(state, ME90_DL_TRACE,
1323 "mckk_ioctl poll connection state with mask 0x%x and"
1324 " timeout %d msec\n",
1325 state_spec.state_mask,
1326 state_spec.timeout
1327 );
1328 usr_time_info = state_spec.time_info;
1329 if (usr_time_info != NULL)
1330 state_spec.time_info = &drv_time_info;
1331 rval = mcb_poll_connection_state(state, &state_spec);
1332 if (usr_time_info != NULL)
1333 state_spec.time_info = usr_time_info;
1334 if (state_spec.connection_events_num != 0 &&
1335 state_spec.connection_events != NULL
1336 )
1337 {
1338 mutex_enter(&state->mutex); /* start MUTEX */
1339 if (state -> max_cnct_events_num == 0 ||
1340 state -> connection_events == NULL
1341 )
1342 {
1343 state_spec.connection_events_num = 0;
1344 state_spec.losed_events_num = state -> losed_events_num;
1345 }
1346 else
1347 {
1348 state_spec.connection_events_num =
1349 state -> cur_cnct_events_num;
1350 state_spec.losed_events_num = state -> losed_events_num;
1351 if (ddi_copyout((caddr_t) state -> connection_events,
1352 (caddr_t) state_spec.connection_events,
1353 state -> cur_cnct_events_num *
1354 sizeof (poll_event_info_t) /*,
1355 mode*/
1356 )
1357 )
1358 {
1359 ME90_LOG(state, ME90_DL_ERROR,
1360 "mckk_ioctl: events info ddi_copyout failed for "
1361 "poll connection state\n"
1362 );
1363 rval = EFAULT;
1364 }
1365 }
1366 state -> cur_cnct_events_num = 0;
1367 state -> losed_events_num = 0;
1368 mutex_exit(&state->mutex); /* end MUTEX */
1369 }
1370 if (ddi_copyout((caddr_t) & state_spec,
1371 (caddr_t) arg,
1372 sizeof (poll_cnct_state_t) /*,
1373 mode*/
1374 )
1375 )
1376 {
1377 ME90_LOG(state, ME90_DL_ERROR,
1378 "mckk_ioctl: ddi_copyout failed for poll connection"
1379 " state\n"
1380 );
1381 return EFAULT;
1382 }
1383 if (usr_time_info != NULL)
1384 {
1385 if (ddi_copyout((caddr_t) & drv_time_info,
1386 (caddr_t) usr_time_info,
1387 sizeof (poll_time_info_t)/*,
1388 mode*/
1389 )
1390 )
1391 {
1392 ME90_LOG(state, ME90_DL_ERROR,
1393 "mckk_ioctl: time info ddi_copyout failed for poll "
1394 "connection state\n"
1395 );
1396 return EFAULT;
1397 }
1398 }
1399 ME90_LOG(state, ME90_DL_TRACE,
1400 "mckk_ioctl: poll connection state finished\n"
1401 );
1402 return rval;
1403 }
1404 default :
1405 ME90_LOG(state, ME90_DL_ERROR,
1406 "mckk_ioctl invalid 'ioctl' command 0x%x\n",
1407 cmd
1408 );
1409 return (ENOTTY);
1410 }
1411 }
1412
1413 /*
1414 * Set the simple transfer results info
1415 */
1416 /*ARGSUSED*/
1417 int
1418 mcb_set_trans_results(
1419 mcb_state_t *state,
1420 trans_info_t *drv_trans_res_info_p,
1421 trans_info_t *drv_results_p,
1422 trans_info_t *user_trans_res_info_p,
1423 int mode)
1424 {
1425 int rval = 0;
1426
1427 ME90_LOG(state, ME90_DL_TRACE,
1428 "mckk_set_trans_results started\n");
1429
1430 #ifdef _MP_TIME_USE_
1431 READ_MP_TIME(drv_trans_res_info_p -> transfer_finish);
1432 #else
1433 drv_trans_res_info_p -> transfer_finish = ddi_gethrtime();
1434 #endif /* _MP_TIME_USE_ */
1435 if (ddi_copyout((caddr_t) drv_trans_res_info_p,
1436 (caddr_t) user_trans_res_info_p,
1437 sizeof (trans_info_t)/*, mode*/)) {
1438 ME90_LOG(state, ME90_DL_ERROR,
1439 "mckk_set_trans_results ddi_copyout failed for"
1440 " transfer results\n");
1441 rval = EFAULT;
1442 }
1443
1444 ME90_LOG(state, ME90_DL_TRACE,
1445 "mckk_set_trans_results finished\n");
1446 return rval;
1447 }
Linux for the MCST Elbrus 2000 architecture