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Lynx framebuffers multidomain implementation.
[linux/elbrus.git] / drivers / mcst / mokx / mokx_get_event.c
blob9d042df4c52c4558420e6a59924224c19d435ba8
1
2 char *p_DEFAULT = "default";
3
4 char *get_event(int event)
5 {
6 char *p;
7 int n_print;
8
9 switch (event) {
10 case 0:
11 p = NULL;
12 break;
13
14 case INTR_TRWD_EVENT:
15 p = "INTR_TRWD\t";
16 break;
17 case INTR_TRWD_UNXP_EVENT:
18 p = "INTR_TRWD_UNXP\t";
19 break;
20 case INTR_READY_EVENT:
21 p = "INTR_READY\t";
22 break;
23 case INTR_READY_DMA_EVENT:
24 p = "INTR_READY_DMA\t";
25 break;
26 case INTR_MSG_READY_UNXP_EVENT:
27 p = "INTR_MSG_READY_UNXP\t";
28 break;
29 case INTR_MSG_READY_DMA_UNXP_EVENT:
30 p = "INTR_MSG_READY_DMA_UNXP\t";
31 break;
32 case INTR_TDMA_EVENT:
33 p = "INTR_TDMA\t\t";
34 break;
35 case INTR_SIGN1_READ_EVENT:
36 p = "INTR_SIGN1_READ\t";
37 break;
38 case INTR_RMSG_EVENT:
39 p = "INTR_RMSG\t\t";
40 break;
41 case INTR_RMSG_UNXP_EVENT:
42 p = "INTR_RMSG_UNXP\t";
43 break;
44 case INTR_RDC_EVENT:
45 p = "INTR_RDC\t\t";
46 break;
47 case INTR_TDC_UNXP_EVENT:
48 p = "INTR_TDC_UNXP\t";
49 break;
50 case INTR_TDC_DSF_PD_NULL_EVENT:
51 p = "INTR_TDCDSFPDNULL\t";
52 break;
53 case READ_NOT_PROCESS_EVENT:
54 p = "READ_NOT_PROCESS\t";
55 break;
56 case READ_NOT_SELF_PROCESS_EVENT:
57 p = "NOT_SELF_PROCESS\t";
58 break;
59 case READ_WAIT_SELF_PROCESS_EVENT:
60 p = "WAIT_SELF_PROCESS\t";
61 break;
62 case READ_TRY_SIGNAL_PROCESS_EVENT:
63 p = "TRY_SIGNAL_PROCESS\t";
64 break;
65 case READ_PROCESS_EVENT:
66 p = "READ_PROCESS\t";
67 break;
68 case READ_SELF_PROCESS_EVENT:
69 p = "READ_SELF_PROCESS\t";
70 break;
71 case READ_SELF_WAIT_EVENT:
72 p = "READ_SELF_WAIT\t";
73 break;
74 case INTR_DSF_EVENT:
75 p = "INTR_DSF\t\t";
76 break;
77 case INTR_TDC_EVENT:
78 p = "INTR_TDC\t\t";
79 break;
80 case INTR_SIGN1_WRITE_EVENT:
81 p = "INTR_SIGN1_WRITE\t";
82 break;
83 case INTR_RGP3M_EVENT:
84 p = "INTR_RGP3M\t";
85 break;
86 case INTR_RGP2M_EVENT:
87 p = "INTR_RGP2M\t";
88 break;
89 case INTR_RGP1M_EVENT:
90 p = "INTR_RGP1M\t";
91 break;
92 case INTR_SIGN3_READ_EVENT:
93 p = "INTR_SIGN3_READ\t";
94 break;
95 case INTR_RGP0M_EVENT:
96 p = "INTR_RGP0M\t";
97 break;
98 case INTR_SIGN2_WRITE_EVENT:
99 p = "INTR_SIGN2_WRITE\t";
100 break;
101 case INTR_RGP3M_UNXP_EVENT:
102 p = "INTR_RGP3M_UNXP\t";
103 break;
104 case INTR_RGP1M_UNXP_EVENT:
105 p = "INTR_RGP1M_UNXP\t";
106 break;
107 case WRITE_1_EVENT:
108 p = "WRITE_1_\t\t";
109 break;
110 case WRITE_11_EVENT:
111 p = "WRITE_11_\t";
112 break;
113 case WRITE_111_EVENT:
114 p = "WRITE_111_\t";
115 break;
116 case WRITE_PMSTAT_EVENT:
117 p = "WRITE_PMSTAT\t";
118 break;
119 case WRITE_SNDMSGBAD_EVENT:
120 p = "WRITE_SNDMSGBAD\t";
121 break;
122 case WRITE_SNDNGMSG_EVENT:
123 p = "WRITE_SNDNGMSG\t";
124 break;
125 case WRITE_BAD1_EVENT:
126 p = "WRITE_BAD1\t";
127 break;
128 case WRITE_0_EVENT:
129 p = "WRITE_0_\t\t";
130 break;
131 case WRITE_00_EVENT:
132 p = "WRITE_00_\t\t";
133 break;
134 case WRITE_000_EVENT:
135 p = "WRITE_000_\t";
136 break;
137 case WRITE_ISDSF_EVENT:
138 p = "WRITE_ISDSF\t";
139 break;
140 case READ_1_EVENT:
141 p = "READ_1_\t\t";
142 break;
143 case READ_11_EVENT:
144 p = "READ_11_\t\t";
145 break;
146 case READ_111_EVENT:
147 p = "READ_111_\t\t";
148 break;
149 case READ_TRWD_WAS_EVENT:
150 p = "READ_TRWD_WAS\t";
151 break;
152 case READ_TRWD_WAS_LONG_EVENT:
153 p = "READ_TRWD_WAS_LONG\t";
154 break;
155 case READ_TRWD_WAS_TIMEOUT_EVENT:
156 p = "READ_TRWD_WAS_TIMEOUT\t";
157 break;
158 case READ_BAD1_EVENT:
159 p = "READ_BAD1\t";
160 break;
161 case READ_BAD2_EVENT:
162 p = "READ_BAD2\t";
163 break;
164 case READ_BADSIZE_EVENT:
165 p = "READ_BADSIZE\t";
166 break;
167 case READ_PMSTAT_EVENT:
168 p = "READ_PMSTAT\t";
169 break;
170 case READ_SNDMSGBAD_EVENT:
171 p = "READ_SNDMSGBAD\t";
172 break;
173 case SNDMSGOK_EVENT:
174 p = "SNDMSGOK\t";
175 break;
176 case SNDMSGBAD_EVENT:
177 p = "SNDMSGBAD\t";
178 break;
179 case READ_SNDNGMSG_EVENT:
180 p = "READ_SNDNGMSG\t";
181 break;
182 case READ_BAD3_EVENT:
183 p = "READ_BAD3\t";
184 break;
185 case SNDMSG_PMSTAT_EVENT:
186 p = "SNDMSG_PMSTAT\t";
187 break;
188 case SNDMSG_BAD_EVENT:
189 p = "SNDMSG_BAD\t";
190 break;
191 case SNDNGMSG_EVENT:
192 p = "SNDNGMSG\t\t";
193 break;
194 case INTR_FAIL_SND_SGP3_EVENT:
195 p = "INTR_FAIL_SND_SGP3\t";
196 break;
197 case INTR_FAIL_SND_SGP1_EVENT:
198 p = "INTR_FAIL_SND_SGP1\t";
199 break;
200 case WRITE_FAIL_SND_SGP2_EVENT:
201 p = "WRITE_FAIL_SND_SGP2\t";
202 break;
203 case READ_FAIL_SND_SGP0_EVENT:
204 p = "READ_FAIL_SND_SGP0\t";
205 break;
206 case WRR_EVENT:
207 p = "WRR_EVENT\t\t";
208 break;
209 case RDR_EVENT:
210 p = "RDR_EVENT\t\t";
211 break;
212 case READ_0_EVENT:
213 p = "READ_0_\t\t";
214 break;
215 case READ_00_EVENT:
216 p = "READ_00_\t\t";
217 break;
218 case READ_000_EVENT:
219 p = "READ_000_\t";
220 break;
221 case MSG_RST_EVENT:
222 p = "MSG_RST\t\t";
223 break;
224 case WRITE_IRQ_COUNT_EVENT:
225 p = "WRITE_IRQ_COUNT\t";
226 break;
227 case READ_IRQ_COUNT1_EVENT:
228 p = "READ_IRQ_COUNT1\t";
229 break;
230 case READ_IRQ_COUNT2_EVENT:
231 p = "READ_IRQ_COUNT2\t";
232 break;
233 case BROAD_TRY_WAKEUP_EVENT:
234 p = "BROAD_TRY_WAKEUP\t";
235 break;
236 case BROAD_RUNNING_EVENT:
237 p = "BROAD_RUNNING\t";
238 break;
239 case WAIT_TRY_SCHTO_EVENT:
240 p = "WAIT_TRY_SCHTO\t";
241 break;
242 case WAIT_RET_SCHT0_EVENT:
243 p = "WAIT_RET_SCHT0\t";
244 break;
245 case WAIT_RET_SCHT1_EVENT:
246 p = "WAIT_RET_SCHT1\t";
247 break;
248 case WAIT_RET_SCHT2_EVENT:
249 p = "WAIT_RET_SCHT2\t";
250 break;
251 case RDMA_BROADCAST:
252 p = "RDMA_BROADCAST\t";
253 break;
254 case INTR_SIE_EVENT:
255 p = "INTR_SIE\t\t";
256 break;
257 case INTR_CMIE_EVENT:
258 p = "INTR_CMIE\t";
259 break;
260 case INTR_START_EVENT:
261 p = "INTR_START_EVENT\t";
262 break;
263 case INTR_EXIT_EVENT:
264 p = "INTR_EXIT_EVENT\t";
265 break;
266 case MAIN_FAIL_SND_CS_SUL_Msg_EVENT:
267 p = "FAIL_SND_SUL_Msg\t";
268 break;
269 case MAIN_FAIL_SND_CS_SL_Msg_EVENT:
270 p = "FAIL_SND_SL_Msg\t";
271 break;
272 case MAIN_FAIL_SND_NEED_BYPASS_EVENT:
273 p = "FAIL_SND_NEED_BYPASS\t";
274 break;
275 case INTR_FAIL_SND_MSG_BAD_BUFFER_EVENT:
276 p = "FAIL_SND_MSG_BAD_BUF\t";
277 break;
278 case INTR_ERR_BAD_BUFFER_EVENT:
279 p = "ERR_BAD_BUFFER\t";
280 break;
281 case READ_SIGN1_EVENT:
282 p = "READ_SIGN1\t";
283 break;
284 case INTR_UNEXP2_READ_EVENT:
285 p = "INTR_UNEXP2_READ\t";
286 break;
287 case READ_BAD_SYNHR_EVENT:
288 p = "READ_BAD_SYNHR\t";
289 break;
290 case READ_DEF2_EVENT:
291 p = "READ_DEF2_\t";
292 break;
293 case WRITE_DSF_EVENT:
294 p = "WRITE_DSF_\t";
295 break;
296 case INTR_SIGN2_READ_EVENT:
297 p = "INTR_SIGN2_READ\t";
298 break;
299 case MAIN_FAIL_SND_CS_SIR_Msg_EVENT:
300 p = "MAIN_FAIL_SND_CS_SIR_Msg\t";
301 break;
302 case RDMA_BAD_RDC_EVENT:
303 p = "BAD_RDC_EVENT\t";
304 break;
305 case RDMA_INTER1_EVENT:
306 p = "INTER1_EVENT\t";
307 break;
308 case RDMA_INTER2_EVENT:
309 p = "INTER2_EVENT\t";
310 break;
311 case RDMA_INTER3_EVENT:
312 p = "INTER3_EVENT\t";
313 break;
314 case READ_LOSS_EVENT:
315 p = "READ_LOSS_EVENT\t";
316 break;
317 case START_HANDLER_IRQ:
318 p = "START_HANDLER_IRQ\t";
319 break;
320 case READ_BAD_WAIT_EVENT:
321 p = "READ_BAD_WAIT\t";
322 break;
323 case READ_TRY_RDMA_EVENT:
324 p = "READ_TRY_RDMA\t";
325 break;
326 case READ_NULL_IRQ_EVENT_EVENT:
327 p = "READ_NULL_IRQ\t";
328 break;
329 case READ_DEF_IRQ_EVENT_EVENT:
330 p = "READ_DEF_IRQ\t";
331 break;
332 case RDMA_0_OPEN:
333 p = "RDMA_0_OPEN\t";
334 break;
335 case RDMA_00_OPEN:
336 p = "RDMA_00_OPEN\t";
337 break;
338 case RDMA_000_OPEN:
339 p = "RDMA_000_OPEN\t";
340 break;
341 case RDMA_1_OPEN:
342 p = "RDMA_1_OPEN\t";
343 break;
344 case INTR_RGP0M_UNXP_EVENT:
345 p = "INTR_RGP0M_UNXP_EVENT\t";
346 break;
347 case READ_TIMEOUT_EVENT:
348 p = "READ_TIMEOUT_\t";
349 break;
350 case READ_RET_WAIT_EVENT:
351 p = "READ_RET_WAIT_\t";
352 break;
353 case WRITE_TDMA_On_EVENT:
354 p = "WRITE_TDMA_On_\t";
355 break;
356 case WRITE_DMA_TBC_EVENT:
357 p = "WRITE_DMA_TBC_\t";
358 break;
359 case READ_RDMA_On_EVENT:
360 p = "READ_RDMA_On_\t";
361 break;
362 case READ_DMA_RBC_EVENT:
363 p = "READ_DMA_RBC_\t";
364 break;
365 case READ_SIGN2_EVENT:
366 p = "READ_SIGN2_EVENT\t";
367 break;
368 case RDMA_INIT:
369 p = "RDMA_INIT\t";
370 break;
371 case RDMA_TEST_STAT:
372 p = "RDMA_TEST_STAT\t";
373 break;
374 case RDMA_INTR:
375 p = "RDMA_INTR\t";
376 break;
377 case INTR_GP0_EVENT:
378 p = "INTR_GP0\t";
379 break;
380 case NO_FREE_BUFF_EVENT:
381 p = "NO_FREE_BUFF\t";
382 break;
383 case RDMA_E_TIMER_IO_EVENT:
384 p = "RDMA_E_TIMER_IO\t";
385 break;
386 default:
387 n_print = sprintf(p_DEFAULT, "0x%x\t", event);
388 p_DEFAULT[n_print] = 0;
389 p = p_DEFAULT;
390 }
391 return p;
392 }
393
394 void get_event_rdma(int need_lock)
395 {
396 unsigned int event_cur;
397 rdma_addr_struct_t clkr;
398 unsigned long flags = 0;
399 char *p1, *p2, *preg;
400
401
402 if (need_lock)
403 raw_spin_lock_irqsave(&mu_fix_event, flags);
404 printk("************get_event_rdma START*****************************"
405 "***************\n");
406 if (rdma_event.event_last_get)
407 event_cur = rdma_event.event_last_get;
408 else
409 event_cur = rdma_event.event_cur;
410 while (1) {
411 clkr.addr = rdma_event.event[event_cur].clkr;
412 if (clkr.addr == 0L)
413 goto contin;
414 switch (rdma_event.event[event_cur].event) {
415 case RDMA_INIT:
416 p1 = "RDMA_INIT";
417 break;
418 case RDMA_TEST_STAT:
419 p1 = "RDMA_TEST_STAT";
420 break;
421 case RDMA_INTR:
422 p1 = "RDMA_INTR";
423 break;
424 case RDMA_SEND_MSG:
425 p1 = "RDMA_SEND_MSG";
426 break;
427
428 default:
429 goto not_fun;
430 }
431 switch (rdma_event.event[event_cur].val1) {
432 case START_EVENT:
433 p2 = "START_EVENT";
434 break;
435 case RETURN_EVENT:
436 p2 = "RETURN_EVENT";
437 break;
438 case TRY_SLEEP_EVENT:
439 p2 = "TRY_SLEEP";
440 break;
441 case WAKE_UPPED_EVENT:
442 p2 = "WAKE_UPPED";
443 break;
444 case TIME_OUT_EVENT:
445 p2 = "TIME_OUT";
446 break;
447 case BAD_IRC_COUNT_EVENT:
448 p2 = "BAD_IRC_COUNT";
449 break;
450 case BAD_COUNT_MSG:
451 p2 = "BAD_COUNT_MSG";
452 break;
453 case TRY_WAKE_UP_EVENT:
454 p2 = "TRY_WAKE_UP";
455 break;
456 case E2K_HALT_OK_EVENT:
457 p2 = "E2K_HALT_OK";
458 break;
459 case TEST_SEND_MSG_START:
460 p2 = "TEST_SEND_MSG_START";
461 break;
462 case TEST_SEND_MSG_FINISH:
463 p2 = "TEST_SEND_MSG_FINISH";
464 break;
465 case BIG_COUNT_MSG:
466 p2 = "BIG_COUNT_MSG";
467 break;
468 case TDC_EVENT:
469 p2 = "TDC_EVENT";
470 break;
471 case RDC_EVENT:
472 p2 = "RDC_EVENT";
473 break;
474 case RDM_EVENT:
475 p2 = "RDM_EVENT";
476 break;
477 case RX_TRWD_EVENT:
478 p2 = "RX_TRWD_EVENT";
479 break;
480 case TRY_RDMA_EVENT:
481 p2 = "TRY_RDMA_EVENT";
482 break;
483 case RX_READY_EVENT:
484 p2 = "RX_READY_EVENT";
485 break;
486 case TX_READY_EVENT:
487 p2 = "TX_READY_EVENT";
488 break;
489 case TRY_TDMA_EVENT:
490 p2 = "TRY_TDMA_EVENT";
491 break;
492 case TX_TRWD_EVENT:
493 p2 = "TX_TRWD_EVENT";
494 break;
495 case MSG_CS_ERROR_EVENT:
496 p2 = "MSG_CS_ERROR";
497 break;
498 case ES_ERROR_EVENT:
499 p2 = "ES_ERROR";
500 break;
501 case TCS_ERROR_EVENT:
502 p2 = "TCS_ERROR";
503 break;
504 case TDC_TRY_TDMA0_UNEXPECT_EVENT:
505 p2 = "TDC_TRY_TDMA0_UNEXP";
506 break;
507 case TDC_TXR_FREE_UNEXPECT_EVENT:
508 p2 = "TDC_TXR_FREE_UNEXP";
509 break;
510 case RDC_TRY_RDMA0_UNEXPECT_EVENT:
511 p2 = "RDC_TRY_RDMA0_UNEXP";
512 break;
513 case RDC_RXR_FREE_UNEXPECT_EVENT:
514 p2 = "RDC_RXR_FREE_UNEXP";
515 break;
516 case RDC_TX_READY0_UNEXPECT_EVENT:
517 p2 = "RDC_TRDMA_TX_READY0_UNEXP";
518 break;
519 case RX_TRWD_RX_TRWD_UNEXPECT_EVENT:
520 p2 = "RX_TRWD_RX_TRWD_UNEXP";
521 break;
522 case RX_TRWD_RXR_FREE0_UNEXPECT_EVENT:
523 p2 = "RX_TRWD_RXR_FREE0_UNEXP";
524 break;
525 case RX_TRWD_TRY_RDMA_UNEXPECT_EVENT:
526 p2 = "RX_TRWD_TRY_RDMA_UNEXP";
527 break;
528 case RX_READY_RX_READY_UNEXPECT_EVENT:
529 p2 = "RX_READY_RX_READY_UNEXP";
530 break;
531 case RX_READY_TX_TRWD0_UNEXPECT_EVENT:
532 p2 = "RX_READY_TX_TRWD0_UNEXP";
533 break;
534 case TX_READY_TX_READY_UNEXPECT_EVENT:
535 p2 = "TX_READY_TX_READY_UNEXP";
536 break;
537 case TX_READY_RX_TRWD0_UNEXPECT_EVENT:
538 p2 = "TX_READY_RX_TRWD0_UNEXP";
539 break;
540 case TX_TRWD_TX_TRWD_UNEXPECT_EVENT:
541 p2 = "TX_TRWD_TX_TRWD_UNEXP";
542 break;
543 case TX_TRWD_RX_READY1_UNEXPECT_EVENT:
544 p2 = "TX_TRWD_RX_READY1_UNEXP";
545 break;
546 case TX_TRWD_RX_READY2_UNEXPECT_EVENT:
547 p2 = "TX_TRWD_RX_READY2_UNEXP";
548 break;
549 case TX_TRWD_TRY_TDMA_UNEXPECT_EVENT:
550 p2 = "TX_TRWD_TRY_TDMA_UNEXP";
551 break;
552 case TX_TRWD_TXR_FREE0_UNEXPECT_EVENT:
553 p2 = "TX_TRWD_TXR_FREE0_UNEXP";
554 break;
555 case TRY_TDMA_TRY_TDMA_UNEXPECT_EVENT:
556 p2 = "TRY_TDMA_TRY_TDMA_UNEXP";
557 break;
558 case TRY_TDMA_TXR_FREE0_UNEXPECT_EVENT:
559 p2 = "TRY_TDMA_TXR_FREE0_UNEXP";
560 break;
561 case TRY_TDMA_RX_READY0_UNEXPECT_EVENT:
562 p2 = "TRY_TDMA_RX_READY0_UNEXP";
563 break;
564 case TIME_OUT_TXR_FREE_UNEXPECT_EVENT:
565 p2 = "TIME_OUT_TXR_FREE_UNEXP";
566 break;
567 case TIME_OUT_RXR_FREE_UNEXPECT_EVENT:
568 p2 = "TIME_OUT_RXR_FREE_UNEXP";
569 break;
570 case TIME_OUT_TXR_FREE0_UNEXPECT_EVENT:
571 p2 = "TIME_OUT_TXR_FREE0_UNEXP";
572 break;
573 case TIME_OUT_RXR_FREE0_UNEXPECT_EVENT:
574 p2 = "TIME_OUT_RXR_FREE0_UNEXP";
575 break;
576 case TIME_OUT_RX_TRWD_UNEXPECT_EVENT:
577 p2 = "TIME_OUT_RX_TRWD_UNEXP";
578 break;
579 case TIME_OUT_TX_TRWD_UNEXPECT_EVENT:
580 p2 = "TIME_OUT_TX_TRWD_UNEXP";
581 break;
582 case TIME_OUT_TRY_RDMA_UNEXPECT_EVENT:
583 p2 = "TIME_OUT_TRY_RDMA_UNEXP";
584 break;
585 case TIME_OUT_TRY_TDMA_UNEXPECT_EVENT:
586 p2 = "TIME_OUT_TRY_TDMA_UNEXP";
587 break;
588 case TIME_OUT_RX_READY_UNEXPECT_EVENT:
589 p2 = "TIME_OUT_RX_READY_UNEXP";
590 break;
591 case TIME_OUT_TX_READY_UNEXPECT_EVENT:
592 p2 = "TIME_OUT_TX_READY_UNEXP";
593 break;
594
595 case TIME_out_TXR_FREE_UNEXPECT_EVENT:
596 p2 = "TIME_out_TXR_FREE_UNEXP";
597 break;
598 case TIME_out_RXR_FREE_UNEXPECT_EVENT:
599 p2 = "TIME_out_RXR_FREE_UNEXP";
600 break;
601 case TIME_out_RX_TRWD_UNEXPECT_EVENT:
602 p2 = "TIME_out_RX_TRWD_UNEXP";
603 break;
604 case TIME_out_TX_TRWD_UNEXPECT_EVENT:
605 p2 = "TIME_out_TX_TRWD_UNEXP";
606 break;
607 case TIME_out_TRY_RDMA_UNEXPECT_EVENT:
608 p2 = "TIME_out_TRY_RDMA_UNEXP";
609 break;
610 case TIME_out_TRY_TDMA_UNEXPECT_EVENT:
611 p2 = "TIME_out_TRY_TDMA_UNEXP";
612 break;
613 case TIME_out_RX_READY_UNEXPECT_EVENT:
614 p2 = "TIME_out_RX_READY_UNEXP";
615 break;
616 case TIME_out_TX_READY_UNEXPECT_EVENT:
617 p2 = "TIME_out_TX_READY_UNEXP";
618 break;
619 case INTR_MSG_READY_UNXP_EVENT:
620 p2 = "INTR_MSG_READY_UNXP";
621 break;
622 case RIRM_EVENT:
623 p2 = "RIRM_EVENT";
624 break;
625 case RIAM_EVENT:
626 p2 = "RIAM_EVENT";
627 break;
628 case SEND_ALL_UNEXPECT_EVENT:
629 p2 = "SEND_ALL_UNEXPECT";
630 break;
631 case MSF_ALL_UNEXPECT_EVENT:
632 p2 = "MSF_ALL_UNEXPECT";
633 break;
634 case DMRCL0_UNEXPECT_EVENT:
635 p2 = "DMRCL0_UNEXPECT";
636 break;
637 case MSF_COUNT_MAX_UNEXPECT_EVENT:
638 p2 = "MSF_COUNT_MAX_UNEXPECT";
639 break;
640
641 default:
642 printk("%u 0x%08x%08x %s\t\t\t0x%08x\t\t0x%08x\n",
643 rdma_event.event[event_cur].channel,
644 clkr.fields.haddr, clkr.fields.laddr,
645 p1, rdma_event.event[event_cur].val1,
646 rdma_event.event[event_cur].val2);
647 goto contin;
648 }
649 printk("%u 0x%08x%08x %s\t\t%s\t\t0x%08x\n",
650 rdma_event.event[event_cur].channel,
651 clkr.fields.haddr, clkr.fields.laddr,
652 p1, p2,
653 rdma_event.event[event_cur].val2);
654 goto contin;
655 not_fun:
656 switch (rdma_event.event[event_cur].event) {
657 case RDR_EVENT:
658 p1 = "RDR_EVENT";
659 break;
660 case WRR_EVENT:
661 p1 = "WRR_EVENT";
662 break;
663 default:
664 goto not_reg;
665 }
666 /*
667 switch (rdma_event.event[event_cur].val1) {
668 case SHIFT_IOL_CSR : preg = "IOL_CSR\0"; break;
669 case SHIFT_IO_CSR : preg = "IO_CSR\0"; break;
670 case SHIFT_IO_VID : preg = "IO_VID\0"; break;
671 case SHIFT_VID : preg = "VID\0"; break;
672 case SHIFT_DD_ID : preg = "DD_ID\0"; break;
673 case SHIFT_CH_IDT : preg = "CH_IDT\0"; break;
674 case SHIFT_DMD_ID : preg = "DMD_ID\0"; break;
675 case SHIFT_CS : preg = "CS\0"; break;
676 case SHIFT_N_IDT : preg = "N_IDT\0"; break;
677 case SHIFT_ES : preg = "ES\0"; break;
678 case SHIFT_IRQ_MC : preg = "IRQ_MC\0"; break;
679 case SHIFT_DMA_TCS : preg = "DMA_TCS\0"; break;
680 case SHIFT_DMA_TSA : preg = "DMA_TSA\0"; break;
681 case SHIFT_DMA_TBC : preg = "DMA_TBC\0"; break;
682 case SHIFT_DMA_RCS : preg = "DMA_RCS\0"; break;
683 case SHIFT_DMA_RSA : preg = "DMA_RSA\0"; break;
684 case SHIFT_DMA_RBC : preg = "DMA_RBC\0"; break;
685 case SHIFT_MSG_CS : preg = "MSG_CS\0"; break;
686 case SHIFT_TDMSG : preg = "TDMSG\0"; break;
687 case SHIFT_RDMSG : preg = "RDMSG\0"; break;
688 case SHIFT_DMA_HTSA : preg = "DMA_HTSA\0"; break;
689 case SHIFT_DMA_HRSA : preg = "DMA_HRSA\0"; break;
690 case SHIFT_CAM : preg = "CAM\0"; break;
691 default : preg = "UNKN\0";
692 }
693 */
694
695 if (rdma_event.event[event_cur].val1 == SHIFT_IOL_CSR)
696 preg = "IOL_CSR\0";
697 else if (rdma_event.event[event_cur].val1 == SHIFT_IO_VID)
698 preg = "IO_VID\0";
699 else if (rdma_event.event[event_cur].val1 == SHIFT_DD_ID)
700 preg = "DD_ID\0";
701 else if (rdma_event.event[event_cur].val1 == SHIFT_CH_IDT)
702 preg = "CH_IDT\0";
703 else if (rdma_event.event[event_cur].val1 == SHIFT_DMD_ID)
704 preg = "DMD_ID\0";
705 else if (rdma_event.event[event_cur].val1 == SHIFT_CS)
706 preg = "CS\0";
707 else if (rdma_event.event[event_cur].val1 == SHIFT_N_IDT)
708 preg = "N_IDT\0";
709 else if (rdma_event.event[event_cur].val1 == SHIFT_ES)
710 preg = "ES\0";
711 else if (rdma_event.event[event_cur].val1 == SHIFT_IRQ_MC)
712 preg = "IRQ_MC\0";
713 else if (rdma_event.event[event_cur].val1 == SHIFT_DMA_TCS)
714 preg = "DMA_TCS\0";
715 else if (rdma_event.event[event_cur].val1 == SHIFT_DMA_TSA)
716 preg = "DMA_TSA\0";
717 else if (rdma_event.event[event_cur].val1 == SHIFT_DMA_TBC)
718 preg = "DMA_TBC\0";
719 else if (rdma_event.event[event_cur].val1 == SHIFT_DMA_RCS)
720 preg = "DMA_RCS\0";
721 else if (rdma_event.event[event_cur].val1 == SHIFT_DMA_RSA)
722 preg = "DMA_RSA\0";
723 else if (rdma_event.event[event_cur].val1 == SHIFT_DMA_RBC)
724 preg = "DMA_RBC\0";
725 else if (rdma_event.event[event_cur].val1 == SHIFT_MSG_CS)
726 preg = "MSG_CS\0";
727 else if (rdma_event.event[event_cur].val1 == SHIFT_TDMSG)
728 preg = "TDMSG\0";
729 else if (rdma_event.event[event_cur].val1 == SHIFT_RDMSG)
730 preg = "RDMSG\0";
731 else if (rdma_event.event[event_cur].val1 == SHIFT_DMA_HTSA)
732 preg = "DMA_HTSA\0";
733 else if (rdma_event.event[event_cur].val1 == SHIFT_DMA_HRSA)
734 preg = "DMA_HRSA\0";
735 else if (rdma_event.event[event_cur].val1 == SHIFT_CAM)
736 preg = "CAM\0";
737 else
738 preg = "UNKN\0";
739
740 printk("%u 0x%08x%08x %s\t\t\t%s\t\t0x%08x\n",
741 rdma_event.event[event_cur].channel,
742 clkr.fields.haddr, clkr.fields.laddr,
743 p1, preg, rdma_event.event[event_cur].val2);
744 goto contin;
745 not_reg:
746 p1 = get_event(rdma_event.event[event_cur].event);
747 if (p1 == NULL) {
748 printk("0x%08x 0x%08x%08x 0x%08x 0x%08x 0x%08x\n",
749 rdma_event.event[event_cur].channel,
750 clkr.fields.haddr, clkr.fields.laddr,
751 rdma_event.event[event_cur].event,
752 rdma_event.event[event_cur].val1,
753 rdma_event.event[event_cur].val2);
754 } else {
755 printk("%u 0x%08x%08x %s 0x%08x 0x%08x\n",
756 rdma_event.event[event_cur].channel,
757 clkr.fields.haddr, clkr.fields.laddr,
758 p1, rdma_event.event[event_cur].val1,
759 rdma_event.event[event_cur].val2);
760 }
761 contin:
762 if (event_cur == (SIZE_EVENT - 1))
763 event_cur = 0;
764 else
765 event_cur += 1;
766 if (event_cur == rdma_event.event_cur)
767 break;
768 }
769 printk("************get_event_rdma FINISH**************************"
770 "******************\n");
771 if (need_lock)
772 raw_spin_unlock_irqrestore(&mu_fix_event, flags);
773 }
Linux for the MCST Elbrus 2000 architecture