drivers/mcst/mokx/mokx_mok_regs.h

   1 #ifndef __MOKX_REGS_H__
   2 #define __MOKX_REGS_H__
   3
   4 /*
   5  * Structure message MOK_X
   6  *
   7  * 31:28 - rezerv   (ÚÁÒÅÚÅÒ×ÉÒÏ×ÁÎÏ - 0)
   8  * 27:24 - msg_type (ÔÉÐ ÓÏÏÂÝÅÎÉÑ)
   9  * 23:16 - msg_addr (ÁÄÒÅÓ ÒÅÇÉÓÔÒÁ ÓÞÉÔÙ×ÁÎÉÑ/ÚÁÐÉÓÉ ÄÁÎÎÙÈ)
  10  * 15:0  - msg_data (ÄÁÎÎÙÅ)
  11  */
  12 #define RDMA_MOK_X_TYPE_MSG_MASK        0x0f000000
  13 #define RDMA_MOK_X_ADDR_MSG_MASK        0x00ff0000
  14 #define RDMA_MOK_X_DATA_MSG_MASK        0x0000ffff
  15 #define MOK_X_SHIFT_ADDR                16
  16
  17 /*
  18  * Type messages mask
  19  */
  20 /* úÁÐÉÓØ ÒÅÇÉÓÔÒÁ MOK_X */
  21 #define RDMA_MOK_X_REG_WRITE                    0x00000000
  22 /* þÔÅÎÉÅ ÒÅÇÉÓÔÒÁ MOK_X */
  23 #define RDMA_MOK_X_REG_READ                     0x01000000
  24 /* úÁÐÉÓØ ÒÅÇÉÓÔÒÁ MOK_X ÎÁ ÐÒÏÔÉ×ÏÐÏÌÏÖÎÏÊ ÓÔÏÒÏÎÅ */
  25 #define RDMA_MOK_X_REMOTE_REG_WRITE             0x02000000
  26 /* þÔÅÎÉÅ ÒÅÇÉÓÔÒÁ MOK_X ÎÁ ÐÒÏÔÉ×ÏÐÏÌÏÖÎÏÊ ÓÔÏÒÏÎÅ */
  27 #define RDMA_MOK_X_REMOTE_REG_READ              0x03000000
  28 /* ïÔ×ÅÔ ÎÁ ÚÁÐÒÏÓ ÞÔÅÎÉÑ ÒÅÇÉÓÔÒÁ MOK_X ÎÁ ÐÒÏÔÉ×ÏÐÏÌÏÖÎÏÊ ÓÔÏÒÏÎÅ */
  29 #define RDMA_MOK_X_REMOTE_REG_RESPONSE          0x04000000
  30 /* úÁÐÉÓØ ÒÅÇÉÓÔÒÁ RDMA ÎÁ ÐÒÏÔÉ×ÏÐÏÌÏÖÎÏÊ ÓÔÏÒÏÎÅ ËÁÂÅÌÑ */
  31 #define RDMA_MOK_X_REMOTE_SYSTEM_REG_WRITE      0x05000000
  32 /* þÔÅÎÉÅ ÒÅÇÉÓÔÒÁ RDMA ÎÁ ÐÒÏÔÉ×ÏÐÏÌÏÖÎÏÊ ÓÔÏÒÏÎÅ ËÁÂÅÌÑ */
  33 #define RDMA_MOK_X_REMOTE_SYSTEM_REG_READ       0x06000000
  34 /* ïÔ×ÅÔ ÎÁ ÚÁÐÒÏÓ ÞÔÅÎÉÑ ÒÅÇÉÓÔÒÁ ÍÏÄÕÌÑ ÎÁ ÐÒÏÔÉ×ÏÐÏÌÏÖÎÏÊ ÓÔÏÒÏÎÅ ËÁÂÅÌÑ */
  35 #define RDMA_MOK_X_REMOTE_SYSTEM_REG_RESPONSE   0x07000000
  36 /* óÄ×ÉÇ ËÏÄÁ ÏÐÅÒÁÃÉÉ */
  37 #define RDMA_MOK_X_MSG_SHIFT                    24
  38
  39 /* íÌÁÄÛÉÅ 16 ÒÁÚÒÑÄÏ× ÒÅÇÉÓÔÒÁ */
  40 #define RDMA_MOK_X_LOW_REG                      0x00000000
  41 /* óÔÁÒÛÉÅ 16 ÒÁÚÒÑÄÏ× ÒÅÇÉÓÔÒÁ */
  42 #define RDMA_MOK_X_HIGH_REG                     0x01000000
  43 /* íÁÓËÁ ÓÏÏÂÝÅÎÉÑ */
  44 #define RDMA_MOK_X_MASK                         0x00e00000
  45
  46 /*
  47  * Addrres registers MOK_X
  48  */
  49 /* MDIO */
  50 #define MOK_X_MGIO_CSR_H                        0x0
  51 #define MOK_X_MGIO_CSR_L                        0x1
  52 #define MOK_X_MGIO_DATA_H                       0x2
  53 #define MOK_X_MGIO_DATA_L                       0x3
  54 /* òÅÇÉÓÔÒ ËÏÎÆÉÇÕÒÁÃÉÉ É ÓÔÁÔÕÓÁ */
  55 #define MOK_X_CFG_STATUS                        0x4
  56 /* ôÅËÕÝÅÅ ËÏÌÉÞÅÓÔ×Ï ÐÁËÅÔÏ× × ÂÕÆÅÒÅ ÐÅÒÅÄÁÔÞÉËÁ - tranciever_used_wd */
  57 #define MOK_X_TRANCIEVER_USED_WD                0x5
  58 /* ôÅËÕÝÅÅ ËÏÌÉÞÅÓÔ×Ï ÐÁËÅÔÏ× × ÂÕÆÅÒÅ ÐÒÉÅÍÎÉËÁ - receiver_used_wd */
  59 #define MOK_X_RECIEVER_USED_WD                  0x6
  60 /* òÅÇÉÓÔÒ command */
  61 #define MOK_X_COMMAND                           0x7
  62 /* óÔÁÒÛÉÅ ÒÁÚÒÑÄÙ ÒÁÚÍÅÒÁ ÐÁÞËÉ ÄÌÑ ÄÏÐÏÌÎÉÔÅÌØÎÙÈ ÒÅÖÉÍÏ× ÐÅÒÅÄÁÞÉ */
  63 #define MOK_X_BURST_SIZE_H                      0x8
  64 /* íÌÁÄÛÉÅ ÒÁÚÒÑÄÙ ÒÁÚÍÅÒÁ ÐÁÞËÉ ÄÌÑ ÄÏÐÏÌÎÉÔÅÌØÎÙÈ ÒÅÖÉÍÏ× ÐÅÒÅÄÁÞÉ */
  65 #define MOK_X_BURST_SIZE_L                      0x9
  66 /* îÏÍÅÒ ÔÅÓÔÏ×ÏÇÏ ÒÅÖÉÍÁ: 1 -ÒÅÖÉÍ ÔÅÓÔÏ×ÙÈ ÐÁËÅÔÏ×,    */
  67 /*                         2 -ÒÅÖÉÍ ÔÅÓÔÏ×ÙÈ ÐÁËÅÔÏ× 1G, */
  68 /*                         0- ÐÏ ÕÍÏÌÞÁÎÉÀ ÛÔÁÔÎÙÊ .     */
  69 #define MOK_X_TEST_MODE_PACKETS                 0xa
  70 /* ÷ÅÒÓÉÑ  XGMII 10:8 - ×ÅÒÓÉÑ XGMII, 7:0 - ×ÅÒÓÉÑ ËÏÎÔÒÏÌÅÒÁ */
  71 #define MOK_X_XGMII_CONTROL                     0xf
  72 /* óÞÅÔÞÉË ÐÅÒÅÄÁÎÎÙÈ ÐÁËÅÔÏ× (0x10 - 0x13) */
  73 #define MOK_X_TRANSMITTED_PACKET_COUNTER0       0x10
  74 #define MOK_X_TRANSMITTED_PACKET_COUNTER1       0x11
  75 #define MOK_X_TRANSMITTED_PACKET_COUNTER2       0x12
  76 #define MOK_X_TRANSMITTED_PACKET_COUNTER3       0x13
  77 /* óÞÅÔÞÉË ÐÒÉÎÑÔÙÈ ÐÁËÅÔÏ× (0x14 - 0x17) */
  78 #define MOK_X_RECEIVED_PACKET_COUNTER0          0x14
  79 #define MOK_X_RECEIVED_PACKET_COUNTER1          0x15
  80 #define MOK_X_RECEIVED_PACKET_COUNTER2          0x16
  81 #define MOK_X_RECEIVED_PACKET_COUNTER3          0x17
  82 /* óÞÅÔÞÉË ÐÒÉÎÑÔÙÈ ÐÁËÅÔÏ× Ó ÏÛÉÂËÁÍÉ (0x18 - 0x1b) */
  83 #define MOK_X_RECEIVED_PACKET_ERR_COUNTER0      0x18
  84 #define MOK_X_RECEIVED_PACKET_ERR_COUNTER1      0x19
  85 #define MOK_X_RECEIVED_PACKET_ERR_COUNTER2      0x1a
  86 #define MOK_X_RECEIVED_PACKET_ERR_COUNTER3      0x1b
  87 /* óÞÅÔÞÉË ÎÅÐÒÉÎÑÔÙÈ ÐÁËÅÔÏ× (0x1c - 0x1f) */
  88 #define MOK_X_RECEIVED_PACKET_NOT_COUNTER0      0x1c
  89 #define MOK_X_RECEIVED_PACKET_NOT_COUNTER1      0x1d
  90 #define MOK_X_RECEIVED_PACKET_NOT_COUNTER2      0x1e
  91 #define MOK_X_RECEIVED_PACKET_NOT_COUNTER3      0x1f
  92
  93 /*
  94  * Register config/status MOK_X
  95  */
  96 /* 15,r  link - ÉÄÉËÁÔÏÒ ÓÏÅÄÉÎÅÎÉÑ. */
  97 #define MOK_X_CFG_LINK_SHIFT                    15
  98 #define MOK_X_CFG_LINK                  (1<<MOK_X_CFG_LINK_SHIFT)
  99 /* 14,r  enable - ÉÎÆÏÒÍÁÃÉÏÎÎÙÊ ÂÉÔ. õËÁÚÙ×ÁÅÔ ÎÁ ÔÏ, ÞÔÏ ÕÓÔÒÏÊÓÔ×Ï
 100 / *      ÍÏÖÅÔ ÂÙÔØ ÚÁÄÅÊÓÔ×Ï×ÁÎÏ ÄÌÑ ÐÒÉ£ÍÁ/ÐÅÒÅÄÁÞÉ ÄÁÎÎÙÈ. */
 101 #define MOK_X_CFG_ENABLE_SHIFT                  14
 102 #define MOK_X_CFG_ENABLE                (1<<MOK_X_CFG_ENABLE_SHIFT)
 103 /* 13,rw master - ÂÉÔ, ÕËÁÚÙ×ÁÀÝÉÊ ÎÁ ÔÏ ÞÔÏ ÜÔÁ ÓÔÏÒÏÎÁ ×ÅÄÕÝÁÑ. */
 104 #define MOK_X_CFG_MASTER_SHIFT                  13
 105 #define MOK_X_CFG_MASTER                (1<<MOK_X_CFG_MASTER_SHIFT)
 106 /* 12,rw slave - ÂÉÔ, ÕËÁÚÙ×ÁÀÝÉÊ ÎÁ ÔÏ ÞÔÏ ÜÔÁ ÓÔÏÒÏÎÁ ×ÅÄÏÍÁÑ. */
 107 #define MOK_X_CFG_SLAVE_SHIFT                   12
 108 #define MOK_X_CFG_SLAVE                 (1<<MOK_X_CFG_SLAVE_SHIFT)
 109 /* 11,rw enable_transmit - ÒÁÚÒÅÛÅÎÉÅ ÐÅÒÅÄÁÞÉ ÄÁÎÎÙÈ. */
 110 #define MOK_X_CFG_ENABLE_TRANSMIT_SHIFT         11
 111 #define MOK_X_CFG_ENABLE_TRANSMIT       (1<<MOK_X_CFG_ENABLE_TRANSMIT_SHIFT)
 112 /* 10,rw enable_receive - ÒÁÚÒÅÛÅÎÉÅ ÐÒÉ£ÍÁ ÄÁÎÎÙÈ. åÓÌÉ ÜÔÏÔ ÂÉÔ ÎÅ */
 113 /*       ÕÓÔÁÎÏ×ÌÅÎ, ÔÏ ×ÓÅ ×ÈÏÄÑÝÉÅ ÐÁËÅÔÙ ÄÁÎÎÙÈ ÉÇÎÏÒÉÒÕÀÔÓÑ.     */
 114 #define MOK_X_CFG_ENABLE_RECEIVE_SHIFT          10
 115 #define MOK_X_CFG_ENABLE_RECEIVE        (1<<MOK_X_CFG_ENABLE_RECEIVE_SHIFT)
 116 /* 9,rw  ready_to_receive - ÂÉÔ, ÒÁÚÒÅÛÁÀÝÉÊ ÐÒÉÎÉÍÁÔØ ÄÁÎÎÙÅ. åÓÌÉ ÜÔÏÔ ÂÉÔ */
 117 /*       ÎÅ ÕÓÔÁÎÏ×ÌÅÎ, ÔÏ ×ÓÅ ×ÈÏÄÑÝÉÅ ÐÁËÅÔÙ ÄÁÎÎÙÈ ÓÏÈÒÁÎÑÀÔÓÑ × ÐÒÉ£ÍÎÏÍ */
 118 /*       ÂÕÆÅÒÅ É ÂÕÆÅÒÅ ÐÅÒÅÄÁÔÞÉËÁ ÎÁ ÐÒÏÔÉ×ÏÐÏÌÏÖÎÏÊ ÓÔÏÒÏÎÅ.             */
 119 #define MOK_X_CFG_READY_TO_RECEIVE_SHIFT        9
 120 #define MOK_X_CFG_READY_TO_RECEIVE      (1<<MOK_X_CFG_READY_TO_RECEIVE_SHIFT)
 121 /* 8,rw  granted_last_packet - ÕÓÔÁÎÏ×ËÁ ÜÔÏÇÏ ÂÉÔÁ ÚÁÄÅÊÓÔ×ÕÅÔ ÍÅÈÁÎÉÚÍ */
 122 /*       ÇÁÒÁÎÔÉÒÏ×ÁÎÎÏÊ ÄÏÓÔÁ×ËÉ ÐÏÓÌÅÄÎÅÇÏ ÐÁËÅÔÁ × ÏÂÍÅÎÅ.            */
 123 #define MOK_X_CFG_GRANTED_LAST_PACKET_SHIFT     8
 124 #define MOK_X_CFG_GRANTED_LAST_PACKET   (1<<MOK_X_CFG_GRANTED_LAST_PACKET_SHIFT)
 125 /* 7,rw  granted_packet - ÕÓÔÁÎÏ×ËÁ ÜÔÏÇÏ ÂÉÔÁ ÚÁÄÅÊÓÔ×ÕÅÔ ÍÅÈÁÎÉÚÍ */
 126 /*       ÇÁÒÁÎÔÉÒÏ×ÁÎÎÏÊ ÄÏÓÔÁ×ËÉ ×ÓÅÈ ÐÁËÅÔÏ×.                           */
 127 #define MOK_X_CFG_GRANTED_PACKET_SHIFT          7
 128 #define MOK_X_CFG_GRANTED_PACKET        (1<<MOK_X_CFG_GRANTED_PACKET_SHIFT)
 129 /* 6,rw  in_ready_to_receive - ÕËÁÚÙ×ÁÅÔ ÞÔÏ ÐÒÏÔÉ×ÏÐÏÌÏÖÎÁÑ ÓÔÏÒÏÎÁ ÇÏÔÏ×Á */
 130 /*       ÐÒÉÎÉÍÁÔØ ÄÁÎÎÙÅ */
 131 #define MOK_X_CFG_IN_READY_TO_RECEIVE_SHIFT     6
 132 #define MOK_X_CFG_IN_READY_TO_RECEIVE   (1<<MOK_X_CFG_IN_READY_TO_RECEIVE_SHIFT)
 133 /* 5,rw  òÅÖÉÍ ÒÁÂÏÔÙ MODE1 */
 134 #define MOK_X_CFG_MODE1_SHIFT                   5
 135 #define MOK_X_CFG_MODE1                 (1<<MOK_X_CFG_MODE1_SHIFT)
 136 /* 4,rw  òÅÖÉÍ ÒÁÂÏÔÙ MODE2 */
 137 #define MOK_X_CFG_MODE2_SHIFT                   4
 138 #define MOK_X_CFG_MODE2                 (1<<MOK_X_CFG_MODE2_SHIFT)
 139 /* 3,rw  òÅÖÉÍ ÒÁÂÏÔÙ MODE3 */
 140 #define MOK_X_CFG_MODE3_SHIFT                   3
 141 #define MOK_X_CFG_MODE3                 (1<<MOK_X_CFG_MODE3_SHIFT)
 142 /* 2,    òÅÖÉÍ ÒÁÂÏÔÙ MODE4 */
 143 #define MOK_X_CFG_MODE4_SHIFT                   2
 144 #define MOK_X_CFG_MODE4                 (1<<MOK_X_CFG_MODE4_SHIFT)
 145 /* 1,    Timeout, ÓÏÏÂÝÅÎÉÅ ÎÅ ÐÅÒÅÄÁÎÏ */
 146 #define MOK_X_CFG_TIMEOUT_MSG_RECEIVE_SHIFT     1
 147 #define MOK_X_CFG_TIMEOUT_MSG_RECEIVE   (1<<MOK_X_CFG_TIMEOUT_MSG_RECEIVE_SHIFT)
 148 /* 0,    òÅÚÅÒ× 0 */
 149 #define MOK_X_CFG_RESERV_0              0x00000000
 150
 151 /*
 152  * Register MGIO_CSR MOK_X
 153  */
 154 /* 31-14 unused */
 155 #define MOK_X_MGIO_CSR_UNUSED1_MASQ     0xffffd000
 156 /* 13 RRDY (RESULT READY) rc */
 157 #define MOK_X_MGIO_CSR_RESULT READY     0x00002000
 158 /* 12-0 unused */
 159 #define MOK_X_MGIO_CSR_UNUSED0_MASQ     0x00001fff
 160
 161 /*
 162  * Register MGIO_DATA MOK_X
 163  */
 164 /* 31-30 - start of frame must be 01 */
 165 #define MOK_X_MGIO_DATA_START_FRAME     0x00000000
 166 /* 29-28 - operation code 01-write 10-read */
 167 #define MOK_X_MGIO_DATA_OPER_CODE_ADDR  0x00000000
 168 #define MOK_X_MGIO_DATA_OPER_CODE_WR    0x10000000
 169 #define MOK_X_MGIO_DATA_OPER_CODE_RD    0x30000000
 170 #define MOK_X_MGIO_DATA_OPER_CODE_RD_INC        0x20000000
 171
 172 /* 27-23 - phy address */
 173 #define MOK_X_MGIO_DATA_PHY_ADDR_MASQ   0x0f800000
 174 /* 22-18 - register address */
 175 #define MOK_X_MGIO_DATA_REG_ADDR_MASQ   0x007c0000
 176 /* 17-16 - must be 10 */
 177 #define MOK_X_MGIO_DATA_TMP_CODE        0x00020000
 178 /* 15-00 - on write command - data to be written */
 179 #define MOK_X_MGIO_DATA_DATA_MASQ       0x0000ffff
 180
 181 /*
 182  * Register command MOK_X
 183  * ëÏÍÁÎÄÁ, ÚÎÁÞÅÎÉÅ
 184  */
 185 /* 0x00, ÓÂÒÏÓ ÐÅÒÅÄÁÔÞÉËÁ */
 186 #define MOK_X_COMMAND_RESET                     0x00
 187 /* 0x01, ÓÂÒÏÓ transmitted packets counter */
 188 #define MOK_X_TRANSMITTED_PACKET_COUNTER_RESET  0x01
 189 /* 0x02, ÓÂÒÏÓ Received packets counter, Received packets with error counter, */
 190 /* Not received packets counter                                               */
 191 #define MOK_X_TRANSMITTED_PACKET_COUNTER_OTHER  0x02
 192 /* Reset PM8358*/
 193 #define MOK_X_RESET_PM8358                      0x03
 194 /* Reset VSC8488*/
 195 #define MOK_X_RESET_VSC8488                     0x03
 196
 197 /*
 198  * Address RDMA register for MOK_X
 199  * Bug: 5 ÒÁÚÒÑÄÏ× ÎÅ È×ÁÔÁÅÔ ÁÄÒÅÓÏ×ÁÔØ ×ÓÅ RDMA reg - ÉÓÐÒÁ×ÌÅÎÏ 16. éÓÐÒÁ×ÉÔØ
 200  * ÁÄÒÅÓÁ ÒÅÇÉÓÔÒÏ×.
 201  */
 202 #define RDMA_VID_H              0x00000000
 203 #define RDMA_VID_L              0x00010000
 204 #define RDMA_CS_H               0x00020000
 205 #define RDMA_CS_L               0x00030000
 206 #define RDMA_ES_H               0x00040000      /* Event Status */
 207 #define RDMA_ES_L               0x00050000      /* Event Status */
 208 #define RDMA_IRQ_MC_H           0x00060000      /* Interrupt Mask Control */
 209 #define RDMA_IRQ_MC_L           0x00070000      /* Interrupt Mask Control */
 210 #define RDMA_DMA_TCS_H          0x00080000      /* DMA Tx Control/Status */
 211 #define RDMA_DMA_TCS_L          0x00090000      /* DMA Tx Control/Status */
 212 #define RDMA_DMA_TSA_H          0x000a0000      /* DMA Tx Start Address */
 213 #define RDMA_DMA_TSA_L          0x000b0000      /* DMA Tx Start Address */
 214 #define RDMA_DMA_TBC_H          0x000c0000      /* DMA Tx Byte Counter */
 215 #define RDMA_DMA_TBC_L          0x000d0000      /* DMA Tx Byte Counter */
 216 #define RDMA_DMA_RCS_H          0x000e0000      /* DMA Rx Control/Status */
 217 #define RDMA_DMA_RCS_L          0x000f0000      /* DMA Rx Control/Status */
 218 #define RDMA_DMA_RSA_H          0x00100000      /* DMA Rx Start Address */
 219 #define RDMA_DMA_RSA_L          0x00110000      /* DMA Rx Start Address */
 220 #define RDMA_DMA_RBC_H          0x00120000      /* DMA Rx Byte Counter */
 221 #define RDMA_DMA_RBC_L          0x00130000      /* DMA Rx Byte Counter */
 222 #define RDMA_MSG_CS_H           0x00140000      /* Messages Control/Status */
 223 #define RDMA_MSG_CS_L           0x00150000      /* Messages Control/Status */
 224 #define RDMA_TDMSG_H            0x00160000      /* Tx Data_Messages Buffer */
 225 #define RDMA_TDMSG_L            0x00170000      /* Tx Data_Messages Buffer */
 226 #define RDMA_RDMSG_H            0x00180000      /* Rx Data_Messages Buffer */
 227 #define RDMA_RDMSG_L            0x00190000      /* Rx Data_Messages Buffer */
 228 #define RDMA_DMA_HTSA_H         0x001a0000      /* DMA Tx Start Address */
 229 #define RDMA_DMA_HTSA_L         0x001b0000      /* DMA Tx Start Address */
 230 #define RDMA_DMA_HRSA_H         0x001c0000      /* DMA Tx Start Address */
 231 #define RDMA_DMA_HRSA_L         0x001d0000      /* DMA Tx Start Address */
 232
 233 #if 0
 234 #define RDMA_CH_IDT_H           0x00030000
 235 #define RDMA_CH_IDT_L           0x00040000
 236 #define RDMA_DD_ID_H            0x00070000
 237 #define RDMA_DD_ID_L            0x00080000
 238 #define RDMA_DMD_ID_H           0x00090000
 239 #define RDMA_DMD_ID_L           0x000a0000
 240 #define RDMA_N_IDT_H            0x000b0000
 241 #define RDMA_N_IDT_L            0x000c0000
 242 #define RDMA_CAM_H              0x000c0000 /* CAM - channel alive management */
 243 #define RDMA_CAM_L              0x000c0000 /* CAM - channel alive management */
 244 #endif
 245
 246 #endif /* __MOKX_REGS_H__ */