drivers/mcst/msps/msps.h

   1 #ifndef _MCST_MSPS_DRV_H_
   2 #define _MCST_MSPS_DRV_H_
   3
   4
   5 /* #define MSPS_MAJOR          54 */
   6
   7 #define MAX_MSPS                6 /* one channel - one device */
   8 /*
   9  * temporary
  10  * 0, 2, 4 - input devices
  11  * 1, 3, 5 - output devices
  12  * later will be renamed to
  13  * msps_in0, msps_in1, msps_in2
  14  * msps_out0, msps_out1, msps_out2
  15  */
  16
  17 #include <linux/time.h>
  18 typedef long msps_hrtime_t;
  19
  20 #include "linux/mcst/msps_io.h"
  21
  22 /*
  23  * Macros to help debugging
  24  */
  25
  26 #define ERROR_MODE              1
  27 #define DEBUG_MODE              0
  28 #define DEBUG_DETAIL_MODE       0
  29
  30 #if DEBUG_MODE
  31 #warning * * * --- DEBUG_MODE (before commit you must off it) --- * * *
  32 #endif
  33
  34 /* Definitions */
  35
  36 #define MSPS_DMA_MASK           0xffffffff
  37
  38 /*
  39 [15: 0] Vendor ID       offset 0x00
  40 [15: 0] Device ID       offset 0x02
  41 [ 7: 0] Revision ID     offset 0x08
  42 [23: 0] Class Code      offset 0x09
  43 [ 7: 0] Header Type     offset 0x0e
  44  */
  45
  46 #define PCI_VENDOR_ID_MSPS      0x1fff
  47 #define PCI_DEVICE_ID_MSPS      0x800d
  48
  49
  50 #define BASE                    (base_addr)
  51
  52 #define REGS(r)                 (BASE + (r))
  53
  54 /*32 bit*/
  55 #define GET_MSPS_REG(r)         readl(REGS(r))
  56 #define SET_MSPS_REG(r, v)      writel(v, REGS(r))
  57
  58 #define GET_MSPS_REG_B(r, o)    readb(REGS(r) + o)
  59 #define SET_MSPS_REG_B(r, o, v) writeb(v, REGS(r) + o)
  60
  61 #define PAIR_NUMBER(x)          (x/2)
  62
  63
  64 #define MSPS_CHANNEL_NUMBERS    6
  65
  66 /* 0, 2, 4 - receive data */
  67 /* 1, 3, 5 - send data */
  68
  69 /* MSPS registers */
  70
  71 #define MSPS_II_0               ( 0x00 )  /* 32: R/W */
  72 #define MSPS_IM_0               ( 0x04 )  /* 32: R/W */
  73 #define MSPS_C_0                ( 0x08 )  /* 32: R/W */
  74 #define MSPS_CP_0               ( 0x0c )  /* 32: R/W */
  75
  76 #define MSPS_II_1               ( 0x10 )  /* 32: R/W */
  77 #define MSPS_IM_1               ( 0x14 )  /* 32: R/W */
  78 #define MSPS_C_1                ( 0x18 )  /* 32: R/W */
  79 #define MSPS_CP_1               ( 0x1c )  /* 32: R/W */
  80
  81 #define MSPS_II_2               ( 0x20 )  /* 32: R/W */
  82 #define MSPS_IM_2               ( 0x24 )  /* 32: R/W */
  83 #define MSPS_C_2                ( 0x28 )  /* 32: R/W */
  84 #define MSPS_CP_2               ( 0x2c )  /* 32: R/W */
  85
  86 #define MSPS_II_3               ( 0x30 )  /* 32: R/W */
  87 #define MSPS_IM_3               ( 0x34 )  /* 32: R/W */
  88 #define MSPS_C_3                ( 0x38 )  /* 32: R/W */
  89 #define MSPS_CP_3               ( 0x3c )  /* 32: R/W */
  90
  91 #define MSPS_II_4               ( 0x40 )  /* 32: R/W */
  92 #define MSPS_IM_4               ( 0x44 )  /* 32: R/W */
  93 #define MSPS_C_4                ( 0x48 )  /* 32: R/W */
  94 #define MSPS_CP_4               ( 0x4c )  /* 32: R/W */
  95
  96 #define MSPS_II_5               ( 0x50 )  /* 32: R/W */
  97 #define MSPS_IM_5               ( 0x54 )  /* 32: R/W */
  98 #define MSPS_C_5                ( 0x58 )  /* 32: R/W */
  99 #define MSPS_CP_5               ( 0x5c )  /* 32: R/W */
 100
 101 /* universal offset for up twentyfour registers */
 102 #define MSPS_II(i)              (  0x10 * i )
 103 #define MSPS_IM(i)              ( (0x10 * i) + 0x4 )
 104 #define MSPS_C(i)               ( (0x10 * i) + 0x8 )
 105 #define MSPS_CP(i)              ( (0x10 * i) + 0xc )
 106
 107
 108 #define MSPS_LCTL               ( 0x60 )  /* 32: R/W */
 109 #define MSPS_LCTL_EXT           (3)     /* byte for set extended flag */
 110  /*
 111   * register for test dma exchange and reset chanel
 112   * if any first three bits MSPS_TEST[2:0] setup then
 113   * for MSPS_TEST[0x00]: channel 1 plug to channel 0
 114   * for MSPS_TEST[0x08]: channel 3 plug to channel 2
 115   * for MSPS_TEST[0x16]: channel 4 plug to channel 5
 116   * for reset - needed setuo MSPS_TEST[24]: all chanell getting reset signal
 117   */
 118 #define MSPS_TEST               ( 0x64 )  /* 32: R/W */
 119
 120 #define MSPS_INTR               ( 0x68 )  /* 32: R */
 121
 122 /* registers for exchange without DMA */
 123 #define MSPS_INT_0              ( 0x70 )  /* 32: R/W */ /*  input register */
 124 #define MSPS_EXT_0              ( 0x74 )  /* 32: R/W */ /*  shift register */
 125 #define MSPS_INT_1              ( 0x78 )  /* 32: R/W */ /* output register */
 126 #define MSPS_EXT_1              ( 0x7c )  /* 32: R/W */ /*  shift register */
 127 #define MSPS_INT_2              ( 0x80 )  /* 32: R/W */ /*  input register */
 128 #define MSPS_EXT_2              ( 0x84 )  /* 32: R/W */ /*  shift register */
 129 #define MSPS_INT_3              ( 0x88 )  /* 32: R/W */ /* output register */
 130 #define MSPS_EXT_3              ( 0x8c )  /* 32: R/W */ /*  shift register */
 131 #define MSPS_INT_4              ( 0x90 )  /* 32: R/W */ /*  input register */
 132 #define MSPS_EXT_4              ( 0x94 )  /* 32: R/W */ /*  shift register */
 133 #define MSPS_INT_5              ( 0x98 )  /* 32: R/W */ /* output register */
 134 #define MSPS_EXT_5              ( 0x9c )  /* 32: R/W */ /*  shift register */
 135
 136 /*universal offset for up twelve registers*/
 137 #define MSPS_INT(i)             ( MSPS_INT_0 + (0x8 * i) )
 138 #define MSPS_EXT(i)             ( MSPS_EXT_0 + (0x8 * i) )
 139
 140
 141
 142 /* Defenitions for mutex and spinlock */
 143
 144 #define MUTEX_T                 struct mutex            /* struct semaphore */
 145 #define SPINLOCK_T              spinlock_t              /* raw_spinlock_t */
 146
 147 #define MINIT                   mutex_init              /* init_MUTEX */
 148 #define SINIT                   spin_lock_init          /* raw_spin_lock_init */
 149
 150 #define MLOCK                   mutex_lock              /* down */
 151 #define MUNLOCK                 mutex_unlock            /* up */
 152 #define SLOCK                   spin_lock               /* raw_spin_lock */
 153 #define SUNLOCK                 spin_unlock             /* raw_spin_unlock */
 154 #define SLOCK_IRQ               spin_lock_irq           /* raw_spin_lock_irq */
 155 #define SUNLOCK_IRQ             spin_unlock_irq         /* raw_spin_unlock_irq*/
 156 #define SLOCK_IRQSAVE           spin_lock_irqsave       /* _spin_lock_irqsave */
 157 #define SUNLOCK_IRQREST         spin_unlock_irqrestore  /* _irqrestore */
 158
 159
 160 /*
 161  * Structures and union
 162  */
 163
 164 typedef struct dma_data {
 165         dma_addr_t              phys;
 166         dma_addr_t              *virt;
 167         unsigned long           page;
 168         int                     size;
 169         int                     real_size;
 170         int                     user_size;
 171 } dma_data_t;
 172
 173 typedef struct dma_pool {
 174         dma_data_t              mem[2];
 175         int                     buffer; /* what buffer used now */
 176         int                     start;
 177         int                     done;
 178         long                    key;
 179         long                    rele;
 180         int                     twice;
 181         long                    wtime;
 182         wait_queue_head_t       wait_queue;
 183         msps_hrtime_t           s;
 184         msps_hrtime_t           e;
 185 } dma_pool_t;
 186
 187 typedef struct msps_dev {
 188         int                     present;
 189         int                     open;
 190         dma_pool_t              dma;
 191         struct pci_dev          *pdev;
 192         int                     minor; /* global number from 0 to 15 */
 193         MUTEX_T                 mutex; /* common mutex for registers */
 194         MUTEX_T                 ioctl_mutex; /* only for work with ioctl */
 195         int                     poll_flag;
 196         u_long                  interrupt_count;
 197 } msps_dev_t;
 198
 199
 200 #define MSPS_CHEN_ENABLE        0x1 /* not used */
 201 #define MSPS_START_DMA          0x2
 202 #define MSPS_START_DMA_CHEN     0x4
 203 #define MSPS_EXCH_DIRECT        0x8 /* not used,
 204                                      * mode: 1 - transmit, 0 - receiver */
 205
 206 /* MSPS LCTL registesr */
 207 typedef struct lctl_reg {
 208         unsigned int    chn0:   4; /* output */
 209         unsigned int    chn1:   4; /*  input */
 210         unsigned int    chn2:   4; /* output */
 211         unsigned int    chn3:   4; /*  input */
 212         unsigned int    chn4:   4; /* output */
 213         unsigned int    chn5:   4; /*  input */
 214         unsigned int    lext0:  1;
 215         unsigned int    lext1:  1;
 216         unsigned int    lext2:  1;
 217         unsigned int    lext3:  1;
 218         unsigned int    lext4:  1;
 219         unsigned int    lext5:  1;
 220         unsigned int    unusd:  2;
 221 } lctl_reg_t;
 222
 223 union lctl_register {
 224         lctl_reg_t      b;
 225         u32             r;
 226 };
 227
 228
 229 typedef struct lctl_b {
 230         unsigned char   chn0:   4; /* output */
 231         unsigned char   chn1:   4; /*  input */
 232 } lctl_b_t;
 233
 234 union lctl_byte {
 235         lctl_reg_t      b;
 236         u8              r;
 237 };
 238
 239
 240 typedef struct lctl_ext_b {
 241         unsigned int    lext0:  1;
 242         unsigned int    lext1:  1;
 243         unsigned int    lext2:  1;
 244         unsigned int    lext3:  1;
 245         unsigned int    lext4:  1;
 246         unsigned int    lext5:  1;
 247         unsigned int    unusd:  2;
 248 } lctl_ext_b;
 249
 250 union lctl_ext_byte {
 251         lctl_ext_b      b;
 252         u8              r;
 253 };
 254
 255
 256 /* MSPS TEST registesr */
 257 typedef struct test_reg {
 258         unsigned int    tst01:  1; /* test mode 0-1 */
 259         unsigned int    none1:  7; /* unused */
 260         unsigned int    tst23:  1; /* test mode 2-3 */
 261         unsigned int    none2:  7; /* unused */
 262         unsigned int    tst45:  1; /* test mode 4-5 */
 263         unsigned int    none3:  7; /* unused */
 264         unsigned int    reset:  1; /* reset all channels */
 265         unsigned int    none4:  7; /* unused */
 266 } test_reg_t;
 267
 268 union test_register {
 269         test_reg_t      b;
 270         u32             r;
 271 };
 272
 273
 274 /*
 275  * 0X[31-16][14         ][13-8][6          ][5-0]
 276  * 0X[ cntr][masktimeout][mask][intrtimeout][intr]
 277  */
 278 /* MSPS INTR registesr */
 279 typedef struct test_intr {
 280         unsigned int    chn0:   1; /* 0 */
 281         unsigned int    chn1:   1; /* 1 */
 282         unsigned int    chn2:   1; /* 2 */
 283         unsigned int    chn3:   1; /* 3 */
 284         unsigned int    chn4:   1; /* 4 */
 285         unsigned int    chn5:   1; /* 5 */
 286         unsigned int    intrtimeout: 1;/* 6 */
 287         unsigned int    u1:     1; /* 7 */
 288         unsigned int    mask:   6; /* 8-13 */
 289         unsigned int    masktimeout: 1;/* 14 */
 290         unsigned int    u2:     1; /* 15 */
 291         unsigned int    cntr:   16;/* 16-31 */
 292 } test_intr_t;
 293
 294 union intr_register {
 295         test_intr_t     b;
 296         u32             r;
 297 };
 298
 299
 300 /*
 301  * Macros-function
 302  */
 303
 304 #define GETBIT(r, b)            ((readl(REGS(r)) >> (b)) & 1)
 305
 306 #define SETBIT(r, b) {                  \
 307         unsigned long _treg;            \
 308         _treg = readl(REGS(r));         \
 309         _treg |= (1 << b);              \
 310         writel(_treg, REGS(r)); }
 311
 312 #define CLRBIT(r, b) {                  \
 313         unsigned long _treg;            \
 314         _treg = readl(REGS(r));         \
 315         _treg &= ~(1 << b);             \
 316         writel(_treg, REGS(r)); }
 317
 318
 319 /*
 320  * Functions defenition
 321  */
 322
 323 /* additional function */
 324 int             msps_reset(msps_dev_t *dev);
 325
 326 /* for DMA */
 327
 328 /* for interrupt */
 329
 330 /* for init and free */
 331 static int  __init msps_probe_pci(struct pci_dev *,
 332                                      const struct pci_device_id *);
 333 static void __exit msps_remove_one(struct pci_dev *pdev);
 334
 335
 336 /* extern functions */
 337
 338 #define NOTE_PRINT(fmt, args...) printk(KERN_NOTICE "msps [%d]\t" \
 339                                         fmt, pminor, ## args)
 340
 341 #undef DBG_PRINT
 342 #if ERROR_MODE
 343 #  ifdef __KERNEL__
 344 #    define ERROR_PRINT(fmt, args...) printk(KERN_ERR "msps [%d]:\terror:\t" \
 345                                              fmt, pminor, ## args)
 346 #    define WARNING_PRINT(fmt, args...) printk(KERN_WARNING "msps [%d]:\twarning:" \
 347                                                fmt, pminor, ## args)
 348 #  else
 349 #    define ERROR_PRINT(fmt, args...) fprintf(stderr, fmt, ## args)
 350 #    define WARNING_PRINT(fmt, args...) fprintf(stderr, fmt, ## args)
 351 #  endif
 352 #else
 353 #  define ERROR_PRINT(fmt, args...)
 354 #  define WARNING_PRINT(fmt, args...)
 355 #endif
 356
 357 /* by default DBG_PRINT on/off by trigger msps_debug */
 358 #  define DBG_PRINT(fmt, args...)                                       \
 359         if (msps_debug) printk(KERN_INFO "msps [%d]:\t" fmt, pminor, ## args)
 360 /* by default DETAIL_PRINT are off */
 361 #  define DETAIL_PRINT(fmt, args...)
 362
 363 #if DEBUG_MODE
 364 #  ifdef __KERNEL__
 365 #    undef DBG_PRINT
 366 #    define DBG_PRINT(fmt, args...) printk(KERN_DEBUG "msps [%d]:\t"    \
 367                                            fmt, pminor, ## args)
 368 #    if DEBUG_DETAIL_MODE
 369 #      undef DETAIL_PRINT
 370 #      define DETAIL_PRINT(fmt, args...) printk(KERN_NOTICE "msps [%d] more:\t" \
 371                                                 fmt, pminor, ## args)
 372 #    endif
 373 #  else
 374 #    define DBG_PRINT(fmt, args...) fprintf(stderr, fmt, ## args)
 375 #    ifdef DEBUG_DETAIL_MODE
 376 #      define DETAIL_PRINT(fmt, args...) fprintf(stderr, fmt, ## args)
 377 #    endif
 378 #  endif
 379 #endif
 380
 381
 382 #endif  /* !(_MCST_MSPS_DRV_H_) */