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Lynx framebuffers multidomain implementation.
[linux/elbrus.git] / drivers / mcst / rdma / rdma_intr.c
blobe0856eef1257f17fce5b4091b92d3bd8022c99de
1 void intr_channel(unsigned int evs, unsigned int tcs, unsigned int mcs);
2
3 void rdma_interrupt(struct pt_regs *regs)
4 {
5 register volatile unsigned int evs, tcs, mcs;
6
7 evs = RDR_rdma(SHIFT_CS);
8 if (evs & CS_SIE) {
9 WRR_rdma(SHIFT_CS, evs | CS_SIE);
10 event_intr(0, INTR_SIE_EVENT, 0, 0);
11 return;
12 }
13 if (evs & CS_BUS) {
14 event_intr(0, INTR_BUS_EVENT, 0, 0);
15 return;
16 }
17 while ((evs = RDR_rdma(SHIFT_ES(0))) & irq_mc) {
18 WRR_rdma(SHIFT_ES(0), evs & ~ES_SM_Ev);
19 tcs = RDR_rdma(SHIFT_DMA_TCS(0));
20 mcs = RDR_rdma(SHIFT_MSG_CS(0));
21 intr_channel(evs, tcs, mcs);
22
23 }
24 // ack_APIC_irq(); /* remove in apic.c */
25 return;
26 }
27
28 void intr_channel(unsigned int evs, unsigned int tcs, unsigned int mcs)
29 {
30 struct stat_rdma *pst;
31 rw_state_p pd = NULL;
32 rw_state_p pm = NULL;
33 dev_rdma_sem_t *dev_sem;
34 ulong cur_clock;
35 register volatile unsigned int tbc;
36 unsigned int int_cnt;
37 rdma_state_inst_t *xspi = &rdma_state->rdma_sti[0];
38
39 /// pcibios_read_config_dword(bus_number_rdma, devfn_rdma, 0x40, &int_cnt);
40 /// event_intr(0, INTR_START_EVENT, evs, int_cnt);
41 pst = &stat_rdma;
42 pst->rdma_intr++;
43
44 if (evs & ES_RGP3M_Ev) {
45 dev_rdma_sem_t *dev_sem;
46 rw_state_p pcam, pd;
47 if (RDR_rdma(SHIFT_CAM(0))) {
48 WRR_rdma(SHIFT_CAM(0), 0);
49 pcam = &xspi->talive;
50 pd = &xspi->rw_states_d[READER];
51 pd->trwd_was = 0;
52 dev_sem = &pcam->dev_rdma_sem;
53 raw_spin_lock(&dev_sem->lock);
54 if (pcam->stat == 1) {
55 pcam->clkr = E2K_GET_DSREG(clkr);
56 pcam->int_cnt = int_cnt;
57 rdma_cv_broadcast_rdma(&pcam->dev_rdma_sem);
58 }
59 raw_spin_unlock(&dev_sem->lock);
60 } else {
61 if (state_cam == RDMA_UNSET_CAM) {
62 pcam = &xspi->talive;
63 dev_sem = &pcam->dev_rdma_sem;
64 raw_spin_lock(&dev_sem->lock);
65 if (pcam->stat == 1) {
66 pcam->clkr = E2K_GET_DSREG(clkr);
67 pcam->int_cnt = int_cnt;
68 rdma_cv_broadcast_rdma(&pcam->dev_rdma_sem);
69 }
70 raw_spin_unlock(&dev_sem->lock);
71 } else {
72 WRR_rdma(SHIFT_CAM(0), tr_atl);
73 pcam = &xspi->ralive;
74 dev_sem = &pcam->dev_rdma_sem;
75 raw_spin_lock(&dev_sem->lock);
76 if (pcam->stat == 1)
77 rdma_cv_broadcast_rdma(&pcam->dev_rdma_sem);
78 raw_spin_unlock(&dev_sem->lock);
79 }
80 }
81 }
82 cur_clock = (unsigned long)jiffies;
83 if (evs & ES_CMIE_Ev) {
84 WRR_rdma(SHIFT_MSG_CS(0), MSG_CS_Msg_Rst);
85 event_intr(0, INTR_CMIE_EVENT, 0, 0);
86 pst->es_cmie++;
87 return;
88 }
89 if (evs & ES_RDC_Ev) {
90 pd = xspi->rw_states_rd;
91 xspi->rw_states_rd = 0;
92 if (pd == NULL) {
93 event_intr(0, INTR_RDC_PD_NULL_EVENT,
94 intr_rdc_count[0], tcs);
95 pst->pd_rd++;
96 goto ES_RDC_Ev_label;
97 }
98 dev_sem = &pd->dev_rdma_sem;
99 raw_spin_lock(&dev_sem->lock);
100 intr_rdc_count[0]++;
101 event_intr(0, INTR_RDC_EVENT, pd->int_ac, intr_rdc_count[0]);
102 pd->clock_rdc = cur_clock;
103 switch (pd->int_ac) {
104 case 2:
105 pd->int_ac = 3;
106 event_intr(0, INTR_SIGN2_READ_EVENT, 0,
107 dev_sem->num_obmen);
108 dev_sem->time_broadcast = E2K_GET_DSREG(clkr);
109 rdma_cv_broadcast_rdma(&pd->dev_rdma_sem);
110 break;
111 case 0:
112 case 1:
113 case 3:
114 default:
115 event_intr(0, INTR_UNEXP2_READ_EVENT, pd->int_ac,
116 dev_sem->num_obmen);
117 pst->rdc_unxp++;
118 break;
119 }
120 raw_spin_unlock(&dev_sem->lock);
121 if (rfsm)
122 WRR_rdma(SHIFT_DMA_RBC(0), 0x0);
123 pd->rbc = 0;
124 pst->es_rdc++;
125 rdc_byte += allign_dma(pd->size_trb);
126 if (rdc_byte >> 10) {
127 pst->rdc_kbyte += (rdc_byte >> 10);
128 rdc_byte &= 0x3ff;
129 }
130 ES_RDC_Ev_label:
131 evs = evs & ~ES_RDC_Ev;
132 }
133 if (evs & (ES_TDC_Ev | ES_DSF_Ev)) {
134 pd = xspi->rw_states_wr;
135 if (pd == NULL) {
136 event_intr(0, INTR_TDC_DSF_PD_NULL_EVENT,
137 intr_rdc_count[0], tcs);
138 goto ES_TDC_Ev_label;
139 }
140 xspi->rw_states_wr = 0;
141 dev_sem = &pd->dev_rdma_sem;
142 raw_spin_lock(&dev_sem->lock);
143 pd->dsf = 0;
144 pd->clock_tdc = cur_clock;
145 if (evs & ES_DSF_Ev) {
146 tbc = RDR_rdma(SHIFT_DMA_TBC(0));
147 WRR_rdma(SHIFT_DMA_TCS(0), DMA_TCS_Tx_Rst);
148 pd->dsf = tcs;
149 event_intr(tbc, INTR_DSF_EVENT, pd->int_ac, tcs);
150 } else {
151 event_intr(0, INTR_TDC_EVENT, pd->int_ac,
152 dev_sem->num_obmen);
153 }
154 switch (pd->int_ac) {
155 case 2:
156 pd->int_ac = 3;
157 event_intr(0, INTR_SIGN1_WRITE_EVENT, pd->int_ac,
158 dev_sem->num_obmen);
159 rdma_cv_broadcast_rdma(&pd->dev_rdma_sem);
160 break;
161 case 0:
162 case 1:
163 case 3:
164 default:
165 pst->tdc_dsf_unxp++;
166 event_intr(0, INTR_TDC_UNXP_EVENT, pd->int_ac,
167 dev_sem->num_obmen);
168 break;
169 }
170 raw_spin_unlock(&dev_sem->lock);
171
172 if (evs & ES_DSF_Ev) {
173 pst->es_dsf++;
174 if (tcs &DMA_TCS_DPS_Err)
175 pst->dma_tcs_dps_err++;
176 else
177 if (tcs &DMA_TCS_DPCRC_Err)
178 pst->dma_tcs_dpcrc_err++;
179 else
180 if (tcs &DMA_TCS_DPTO_Err)
181 pst->dma_tcs_dpto_err++;
182 else
183 if (tcs &DMA_TCS_DPID_Err)
184 pst->dma_tcs_dpid_err++;
185 if (evs & ES_TDC_Ev) {
186 pst->es_dsf_tdc++;
187 }
188 } else {
189 pst->es_tdc++;
190 }
191 ES_TDC_Ev_label:
192 evs = evs & (~(ES_TDC_Ev |ES_DSF_Ev));
193 }
194 if (evs & ES_RDM_Ev) {
195 int rdmc = (evs & ES_RDMC)>>27;
196 int msg;
197
198 pst->es_rdm++;
199 if (rdmc == 0)
200 rdmc = 32;
201 while (rdmc--) {
202 msg = RDR_rdma(SHIFT_RDMSG(0));
203 pst->rdm++;
204
205 if ((msg & MSG_OPER) == MSG_READY) {
206 pst->rec_ready++;
207 switch ((msg & MSG_ABONENT) >> SHIFT_ABONENT) {
208 case 0:
209 case 1:
210 case 2:
211 case 3:
212 pd = &xspi->rw_states_d[WRITER];
213 break;
214 default:
215 event_intr(0, INTR_MSG_READY_UNXP_EVENT,
216 msg, 0);
217 continue;
218 }
219 dev_sem = &pd->dev_rdma_sem;
220 raw_spin_lock(&dev_sem->lock);
221 event_intr(0, INTR_READY_EVENT, pd->int_ac,
222 dev_sem->num_obmen);
223 switch (pd->int_ac) {
224 case 1:
225 break;
226 case 0:
227 raw_spin_unlock(&dev_sem->lock);
228 pst->READY_UNXP++;
229 continue;
230 break;
231 case 2:
232 raw_spin_unlock(&dev_sem->lock);
233 pst->miss_READY_2++;
234 continue;
235 break;
236 case 3:
237 raw_spin_unlock(&dev_sem->lock);
238 pst->miss_READY_3++;
239 continue;
240 break;
241 default:
242 raw_spin_unlock(&dev_sem->lock);
243 continue;
244 }
245 pd->msg = msg;
246 pd->clock_receive_ready = cur_clock;
247 pd->int_ac = 2;
248 event_intr(0, INTR_TDMA_EVENT, pd->real_size,
249 pd->dma);
250 xspi->rw_states_wr = pd;
251 if (RDR_rdma(SHIFT_DMA_TBC(0))) {
252 pd->int_ac = 5;
253 rdma_cv_broadcast_rdma(&pd->dev_rdma_sem);
254
255 raw_spin_unlock(&dev_sem->lock);
256 continue;
257 }
258 if (RDR_rdma(SHIFT_DMA_TCS(0)) &
259 DMA_TCS_TDMA_On) {
260 pd->int_ac = 5;
261 rdma_cv_broadcast_rdma(&pd->dev_rdma_sem);
262 raw_spin_unlock(&dev_sem->lock);
263 continue;
264 }
265 if (!pd->dma) {
266 pd->int_ac = 5;
267 rdma_cv_broadcast_rdma(&pd->dev_rdma_sem);
268 raw_spin_unlock(&dev_sem->lock);
269 continue;
270 }
271 WRR_rdma(SHIFT_DMA_TCS(0), DMA_TCS_Tx_Rst);
272 WRR_rdma(SHIFT_DMA_TSA(0), pd->dma);
273 WRR_rdma( SHIFT_DMA_TBC(0), pd->real_size);
274 WRR_rdma(SHIFT_DMA_TCS(0),
275 DMA_TCS_TE | DMA_TCS_TCO |
276 (pd->tm?DMA_TCS_TTM:0) | DMA_TCS_DRCL);
277 pd->tm?pst->try_TDMA_tm++:pst->try_TDMA++;
278 raw_spin_unlock(&dev_sem->lock);
279 continue;
280 } else
281 if ((msg & MSG_OPER) == MSG_TRWD) {
282 int chann;
283
284 pst->rec_trwd++;
285 switch ((msg & MSG_ABONENT) >> SHIFT_ABONENT) {
286 case 0:
287 case 1:
288 case 2:
289 case 3:
290 chann = msg & MSG_ABONENT;
291 pd = &xspi->rw_states_d[READER];
292 break;
293 default:
294 event_intr(0, INTR_MSG_TRWD_UNXP_EVENT,
295 msg, 0);
296 continue;
297 }
298 dev_sem = &pd->dev_rdma_sem;
299 pd->clock_receive_trwd = cur_clock;
300 raw_spin_lock(&dev_sem->lock);
301 event_intr(0, INTR_TRWD_EVENT, pd->int_ac,
302 dev_sem->num_obmen);
303 switch (pd->int_ac) {
304 case 1:
305 pd->int_ac = 2;
306 pd->msg = msg;
307 event_intr(0, INTR_SIGN1_READ_EVENT,
308 pd->int_ac, dev_sem->num_obmen);
309 rdma_cv_broadcast_rdma(&pd->dev_rdma_sem);
310 raw_spin_unlock(&dev_sem->lock);
311 continue;
312 break;
313 case 0:
314 pd->trwd_was++;
315 pd->msg = msg;
316 pst->trwd_was++;
317 pst->TRWD_UNXP++;
318 event_intr(0, INTR_TRWD_UNXP_EVENT,
319 pd->int_ac, dev_sem->num_obmen);
320 raw_spin_unlock(&dev_sem->lock);
321 continue;
322 break;
323 case 2:
324 pd->trwd_was++;
325 pst->trwd_was++;
326 pd->msg = msg;
327 pst->miss_TRWD_2++;
328 event_intr(0, INTR_TRWD_UNXP_EVENT,
329 pd->int_ac, dev_sem->num_obmen);
330 raw_spin_unlock(&dev_sem->lock);
331 continue;
332 break;
333 case 3:
334 pd->trwd_was++;
335 pd->msg = msg;
336 pst->trwd_was++;
337 pst->miss_TRWD_3++;
338 event_intr(0, INTR_TRWD_UNXP_EVENT,
339 pd->int_ac, dev_sem->num_obmen);
340 raw_spin_unlock(&dev_sem->lock);
341 continue;
342 break;
343 case 4:
344 pd->trwd_was++;
345 pd->msg = msg;
346 pst->miss_TRWD_4++;
347 event_intr(0, INTR_TRWD_UNXP_EVENT,
348 pd->int_ac, dev_sem->num_obmen);
349 raw_spin_unlock(&dev_sem->lock);
350 continue;
351 break;
352 default:
353 pd->trwd_was++;
354 pd->msg = msg;
355 event_intr(0, INTR_TRWD_UNXP_EVENT,
356 pd->int_ac, dev_sem->num_obmen);
357 raw_spin_unlock(&dev_sem->lock);
358 continue;
359 }
360 } else { /* if (msg & MSG_TRWD) { */
361 pm = &xspi->rw_states_m[0];
362 dev_sem = &pm->dev_rdma_sem;
363 raw_spin_lock(&dev_sem->lock);
364 if (pm->stat == RDMA_IOC_DR) {
365 event_intr(0, INTR_RMSG_EVENT,
366 pd->int_ac, 0);
367 pm->msg = msg;
368 pst->rdm_EXP++;
369 rdma_cv_broadcast_rdma(&pm->dev_rdma_sem);
370 raw_spin_unlock(&dev_sem->lock);
371 } else {
372 event_intr(0, INTR_RMSG_UNXP_EVENT,
373 pd->int_ac, 0);
374 raw_spin_unlock(&dev_sem->lock);
375 pst->rdm_UNXP++;
376 }
377 }
378 }
379 evs = evs & ~ES_RDM_Ev;
380 }
381 if (evs & ES_MSF_Ev) {
382 dev_rdma_sem_t *dev_sem;
383 rw_state_p pcam, pd;
384
385 WRR_rdma(SHIFT_CAM(0), 0);
386 WRR_rdma(SHIFT_MSG_CS(0), msg_cs_dmrcl | MSG_CS_Msg_Rst);
387 event_ioctl(0, INTR_MSF_EVENT, 1, 0);
388 pcam = &xspi->talive;
389 pd = &xspi->rw_states_d[READER];
390 pd->trwd_was = 0;
391 dev_sem = &pcam->dev_rdma_sem;
392 raw_spin_lock(&dev_sem->lock);
393 if (pcam->stat == 1) {
394 pcam->clkr = E2K_GET_DSREG(clkr);
395 pcam->int_cnt = int_cnt;
396 rdma_cv_broadcast_rdma(&pcam->dev_rdma_sem);
397 }
398 raw_spin_unlock(&dev_sem->lock);
399 }
400 if (evs & ES_RGP2M_Ev) {
401 pst->es_rgp2++;
402 evs &= ~ES_RGP2M_Ev;
403 }
404 if (evs & ES_RGP1M_Ev) {
405 pst->es_rgp1++;
406 evs &= ~ES_RGP1M_Ev;
407 }
408 if (evs & ES_RGP0M_Ev) {
409 pst->es_rgp0++;
410 if (enable_exit_gp0) {
411 pd = &xspi->rw_states_d[READER];
412 if (pd == NULL) {
413 goto GP0_label;
414 }
415 dev_sem = &pd->dev_rdma_sem;
416 raw_spin_lock(&dev_sem->lock);
417 pd->state_GP0 = 1;
418 switch (pd->int_ac) {
419 case 1:
420 rdma_cv_broadcast_rdma(&pd->dev_rdma_sem);
421 break;
422 case 0:
423 case 2:
424 case 3:
425 default:
426 break;
427 }
428 raw_spin_unlock(&dev_sem->lock);
429 }
430 GP0_label:
431 evs &= ~ES_RGP0M_Ev;
432 }
433 if (evs & ES_RLM_Ev) {
434 pst->es_rlm++;
435 evs &= ~ES_RLM_Ev;
436 }
437 if (evs & ES_RULM_Ev) {
438 pst->es_rulm++;
439 evs &= ~ES_RULM_Ev;
440 }
441 if (evs & ES_RIAM_Ev) {
442 dev_rdma_sem_t *dev_sem;
443 rw_state_p pcam;
444
445 WRR_rdma(SHIFT_CAM(0), tr_atl);
446 time_ID_ANS = E2K_GET_DSREG(clkr);
447 pcam = &xspi->ralive;
448 dev_sem = &pcam->dev_rdma_sem;
449 raw_spin_lock(&dev_sem->lock);
450 if (pcam->stat == 1) {
451 pcam->clkr = E2K_GET_DSREG(clkr);
452 pcam->int_cnt = int_cnt;
453 rdma_cv_broadcast_rdma(&pcam->dev_rdma_sem);
454 }
455 raw_spin_unlock(&dev_sem->lock);
456 pst->es_riam++;
457 evs &= ~ES_RIAM_Ev;
458 event_intr(0, INTR_RIAM_EVENT, 0, pst->es_riam);
459 }
460 if (evs & ES_RIRM_Ev) {
461 dev_rdma_sem_t *dev_sem;
462 rw_state_p pcam;
463
464 WRR_rdma(SHIFT_CAM(0), tr_atl);
465 time_ID_REQ = E2K_GET_DSREG(clkr);
466 pcam = &xspi->ralive;
467 dev_sem = &pcam->dev_rdma_sem;
468 raw_spin_lock(&dev_sem->lock);
469 if (pcam->stat == 1) {
470 pcam->clkr = E2K_GET_DSREG(clkr);
471 pcam->int_cnt = int_cnt;
472 rdma_cv_broadcast_rdma(&pcam->dev_rdma_sem);
473 }
474 raw_spin_unlock(&dev_sem->lock);
475 pst->es_rirm++;
476 evs &= ~ES_RIRM_Ev;
477 event_intr(0, INTR_RIRM_EVENT, 0, pst->es_rirm);
478 }
479 event_intr(0, INTR_EXIT_EVENT, 0, 0);
480 return;
481 }
Linux for the MCST Elbrus 2000 architecture