drivers/mcst/spi_test/spi_test_mod.c

   1 #include <linux/cpumask.h>
   2 #include <asm/mpspec.h>
   3 #include <linux/module.h>
   4 #include <linux/pci.h>
   5 #include <linux/string.h>
   6 #include <linux/proc_fs.h>
   7 #include <linux/delay.h>
   8
   9 static struct i2c_spi_t {
  10         void __iomem *cntrl_base;
  11         void __iomem *data_base;
  12         unsigned char dev_number;
  13 } i2c_spig;
  14
  15
  16 char tch[1024];
  17 struct proc_dir_entry *proc_dev;
  18
  19 #define E3M_MULTIFUNC_VENDOR    PCI_VENDOR_ID_INTEL
  20 #define E3M_MULTIFUNC_DEVICE    0x0002
  21
  22 #define MAX_SPI_DEVICE_NR                                       3
  23
  24 #define SPI_CONTROL                                             0x00
  25 #define SPI_STATUS                                              0x04
  26 #define SPI_OPCODE                                              0x08
  27 #define SPI_ADDRESS                                             0x0C
  28 #define SPI_MODE                                                0x10
  29
  30 #define SPI_WREN_CMD                                            6
  31 #define SPI_WRDI_CMD                                            4
  32 #define SPI_WRSR_CMD                                            5
  33 #define SPI_RDSR_CMD                                            1
  34 #define SPI_READ_CMD                                            3
  35 #define SPI_WRITE_CMD                                           2
  36 #define SPI_RDPC_CMD                                            0x13
  37 #define SPI_WRPC_CMD                                            0x12
  38
  39 #define SPI_STATUS_BUSY_SHIFT                           0
  40 #define SPI_STATUS_INTR_SHIFT                           1
  41 #define SPI_STATUS_FAIL_SHIFT                           2
  42
  43 #define SPI_STATUS_BUSY                                         (1 << SPI_STATUS_BUSY_SHIFT)
  44 #define SPI_STATUS_INTR                                         (1 << SPI_STATUS_INTR_SHIFT)
  45 #define SPI_STATUS_FAIL                                         (1 << SPI_STATUS_FAIL_SHIFT)
  46
  47 #define SPI_MODE_INTR_SHIFT                           4
  48 #define SPI_MODE_INTR                                           (1 << SPI_MODE_INTR_SHIFT)
  49
  50 #define SPI_DEVICE_0                                            0
  51 #define SPI_DEVICE_1                                            1
  52 #define SPI_DEVICE_2                                            2
  53 #define SPI_DEVICE_3                                            3
  54
  55 #define SPI_ADDRESS_SIZE_8                                      0
  56 #define SPI_ADDRESS_SIZE_16                                     1
  57 #define SPI_ADDRESS_SIZE_24                                     2
  58 #define SPI_ADDRESS_SIZE_32                                     3
  59
  60 #define MAX_SPI_BYTES                                           64
  61
  62 #define SPI_DEVICE_SHIFT                                0
  63
  64 #define MAX_SPI_ADDRESS_SIZE_SHIFT                      3
  65 #define SPI_ADDRESS_SIZE_SHIFT                          2
  66
  67 #define SPI_DATA_SIZE_SHIFT                             4
  68 #define SPI_ADDRESS_PHASE_SHIFT                         11
  69
  70 #define SPI_ADDRESS_PHASE_ENABLE                        (1 << SPI_ADDRESS_PHASE_SHIFT)
  71 #define SPI_ADDRESS_PHASE_DISABLE                       (0 << SPI_ADDRESS_PHASE_SHIFT)
  72
  73 #define SPI_DATA_PHASE_SHIFT                            12
  74
  75 #define SPI_DATA_PHASE_ENABLE                           (1 << SPI_DATA_PHASE_SHIFT)
  76 #define SPI_DATA_PHASE_DISABLE                          (0 << SPI_DATA_PHASE_SHIFT)
  77
  78 #define SPI_TRANS_TYPE_SHIFT                            13
  79
  80 #define SPI_TRANS_READ                                          (0 << SPI_TRANS_TYPE_SHIFT)
  81 #define SPI_TRANS_WRITE                                         (1 << SPI_TRANS_TYPE_SHIFT)
  82
  83 #define SPI_START_SHIFT                                         14
  84
  85 #define SPI_START                                                       (1 << SPI_START_SHIFT)
  86
  87 #define SPI_KILL_SHIFT                                          15
  88
  89 #define SPI_KILL                                                        (1 << SPI_KILL_SHIFT)
  90
  91 #define SPI_CMOS_CNTRL_AREA_SIZE                        0x40
  92 #define SPI_CMOS_DATA_AREA_SIZE                         0x40
  93
  94 #define I2C_SPI_DEFAULT_IRQ                             23
  95
  96 static int spi_ops(struct i2c_spi_t *i2c_spi, unsigned int dev_number, unsigned char cmd_code);
  97 static int spi_read(struct i2c_spi_t *i2c_spi, unsigned int cmos_addr)
  98 {
  99   void  *i2c_spi_cntrl = i2c_spi->cntrl_base;
 100   void  *i2c_spi_data = i2c_spi->data_base;
 101   unsigned char data;
 102   unsigned int cmd = 0;
 103   unsigned int tmp;
 104
 105   /* Set READ operation code */
 106 //niki  E2K_WRITE_MAS_W(i2c_spi_cntrl + SPI_OPCODE, SPI_RDPC_CMD, MAS_IOADDR);
 107     writel(SPI_RDPC_CMD, i2c_spi_cntrl + SPI_OPCODE);
 108
 109   /* Set addr offset */
 110 //niki  E2K_WRITE_MAS_W(i2c_spi_cntrl + SPI_ADDRESS, cmos_addr, MAS_IOADDR);
 111     writel(cmos_addr, i2c_spi_cntrl + SPI_ADDRESS);
 112
 113   /* Clean int & fail bits */
 114 //niki   E2K_WRITE_MAS_W(i2c_spi_cntrl + SPI_STATUS, 0x6, MAS_IOADDR);
 115     writel(0x6, i2c_spi_cntrl + SPI_STATUS);
 116
 117   /* Set Device number, Address size, Data size offset */
 118   cmd = i2c_spi->dev_number << SPI_DEVICE_SHIFT |
 119       SPI_ADDRESS_SIZE_8 << SPI_ADDRESS_SIZE_SHIFT |
 120       1 << SPI_DATA_SIZE_SHIFT |
 121       SPI_ADDRESS_PHASE_ENABLE |
 122       SPI_DATA_PHASE_ENABLE |
 123       SPI_TRANS_READ |
 124       SPI_START;
 125
 126 //niki  E2K_WRITE_MAS_W(i2c_spi_cntrl + SPI_CONTROL, cmd, MAS_IOADDR);
 127     writel(cmd, i2c_spi_cntrl + SPI_CONTROL);
 128
 129   while((tmp = readl(i2c_spi_cntrl + SPI_STATUS)/*niki E2K_READ_MAS_W(i2c_spi_cntrl + SPI_STATUS, MAS_IOADDR)*/) &
 130          (SPI_STATUS_BUSY))
 131          {
 132             if(tmp & SPI_STATUS_FAIL)
 133                 break;
 134          }
 135
 136   if (readl(i2c_spi_cntrl + SPI_STATUS) /* niki E2K_READ_MAS_W(i2c_spi_cntrl + SPI_STATUS, MAS_IOADDR) */& SPI_STATUS_FAIL) {
 137     printk("spi_read: Error - Transfer Failed");
 138     return -1;
 139   }
 140   data = readb (i2c_spi_data);//niki E2K_READ_MAS_B(i2c_spi_data, MAS_IOADDR);
 141   return (int)data;
 142 }
 143
 144 static int spi_write(struct i2c_spi_t *i2c_spi, unsigned char val, unsigned int cmos_addr)
 145 {
 146
 147   unsigned int cmd;
 148   void *i2c_spi_cntrl = i2c_spi->cntrl_base;
 149   void *i2c_spi_data = i2c_spi->data_base;
 150   unsigned int tmp;
 151
 152   if(spi_ops(i2c_spi, i2c_spi->dev_number, SPI_WREN_CMD) == -1) {
 153     printk("%s: Error - Failed to enable write operation", __FUNCTION__);
 154     return -1;
 155   }
 156
 157   //niki E2K_WRITE_MAS_B(i2c_spi_data, val, MAS_IOADDR);
 158     writeb(val, i2c_spi_data);
 159
 160   /* Clean int & fail bits */
 161    //niki E2K_WRITE_MAS_W(i2c_spi_cntrl + SPI_STATUS, 0x6, MAS_IOADDR);
 162     writel(0x6, i2c_spi_cntrl + SPI_STATUS);
 163
 164   /* Set WRITE operation code */
 165   //niki E2K_WRITE_MAS_W(i2c_spi_cntrl + SPI_OPCODE, SPI_WRPC_CMD, MAS_IOADDR);
 166   writel(SPI_WRPC_CMD, i2c_spi_cntrl + SPI_OPCODE);
 167
 168   /* Set addr offset */
 169   //niki E2K_WRITE_MAS_W(i2c_spi_cntrl + SPI_ADDRESS, cmos_addr, MAS_IOADDR);
 170   writel(cmos_addr, i2c_spi_cntrl + SPI_ADDRESS);
 171
 172   /* Set Device number, Address size, Data size offset */
 173   cmd = i2c_spi->dev_number << SPI_DEVICE_SHIFT |
 174       SPI_ADDRESS_SIZE_8 << SPI_ADDRESS_SIZE_SHIFT |
 175       1 << SPI_DATA_SIZE_SHIFT |
 176       SPI_ADDRESS_PHASE_ENABLE |
 177       SPI_DATA_PHASE_ENABLE |
 178       SPI_TRANS_WRITE |
 179       SPI_START;
 180
 181   //niki E2K_WRITE_MAS_W(i2c_spi_cntrl + SPI_CONTROL, cmd, MAS_IOADDR);
 182   writel(cmd, i2c_spi_cntrl + SPI_CONTROL);
 183
 184   while((tmp = readl(i2c_spi_cntrl + SPI_STATUS)/*niki E2K_READ_MAS_W(i2c_spi_cntrl + SPI_STATUS, MAS_IOADDR)*/) &
 185          (SPI_STATUS_BUSY))
 186          {
 187             if(tmp & SPI_STATUS_FAIL)
 188                 break;
 189          }
 190
 191   if (/*niki E2K_READ_MAS_W(i2c_spi_cntrl + SPI_STATUS, MAS_IOADDR)*/ readl(i2c_spi_cntrl + SPI_STATUS) & SPI_STATUS_FAIL) {
 192     printk("spi_write: Error - Transfer Failed");
 193     return -1;
 194   }
 195   return 1;
 196 }
 197
 198
 199 static int spi_interrupt_unlock(struct i2c_spi_t *i2c_spi, unsigned int mode)
 200 {
 201 //niki  E2K_WRITE_MAS_W(i2c_spi->cntrl_base + SPI_MODE, mode, MAS_IOADDR);
 202     writel(mode, i2c_spi->cntrl_base + SPI_MODE);
 203   return 1;
 204 }
 205
 206 static unsigned int spi_interrupt_lock(struct i2c_spi_t *i2c_spi)
 207 {
 208   unsigned int mode = readl(i2c_spi->cntrl_base + SPI_MODE);//E2K_READ_MAS_W(i2c_spi->cntrl_base + SPI_MODE, MAS_IOADDR);
 209   // mode &= (~SPI_MODE_INTR);
 210   //niki E2K_WRITE_MAS_W(i2c_spi->cntrl_base + SPI_MODE, mode & (~SPI_MODE_INTR), MAS_IOADDR);
 211   writel(mode & (~SPI_MODE_INTR),i2c_spi->cntrl_base + SPI_MODE);
 212   return mode;
 213 }
 214
 215 static int spi_interrupt_reset(struct i2c_spi_t *i2c_spi)
 216 {
 217   unsigned int status = readl(i2c_spi->cntrl_base + SPI_STATUS);//E2K_READ_MAS_W(i2c_spi->cntrl_base + SPI_STATUS, MAS_IOADDR);
 218
 219   //niki E2K_WRITE_MAS_W(i2c_spi->cntrl_base + SPI_STATUS, status, MAS_IOADDR);
 220   writel(status, i2c_spi->cntrl_base + SPI_STATUS);
 221   return 1;
 222 }
 223
 224 static int spi_ops(struct i2c_spi_t *i2c_spi, unsigned int dev_number, unsigned char cmd_code)
 225 {
 226   unsigned int cmd;
 227   void *i2c_spi_cntrl = i2c_spi->cntrl_base;
 228   if (dev_number > MAX_SPI_DEVICE_NR) {
 229     printk("spi_ops: Error - Device number is to large: %d (Max: %d)", dev_number, MAX_SPI_DEVICE_NR);
 230     return -1;
 231   }
 232   switch(cmd_code) {
 233     case SPI_READ_CMD:
 234     case SPI_WRITE_CMD:
 235     case SPI_RDPC_CMD:
 236     case SPI_WRPC_CMD:
 237       printk("spi_ops: Error - Wrong command code: %d", cmd_code);
 238       return -1;
 239     default:
 240       break;
 241   }
 242
 243   //niki E2K_WRITE_MAS_W(i2c_spi_cntrl + SPI_OPCODE, cmd_code, MAS_IOADDR);
 244   writel(cmd_code, i2c_spi_cntrl + SPI_OPCODE);
 245
 246   cmd = dev_number << SPI_DEVICE_SHIFT |
 247       SPI_ADDRESS_PHASE_DISABLE |
 248       SPI_DATA_PHASE_DISABLE |
 249       SPI_START;
 250   //niki E2K_WRITE_MAS_W(i2c_spi_cntrl + SPI_CONTROL, cmd, MAS_IOADDR);
 251   writel(cmd, i2c_spi_cntrl + SPI_CONTROL);
 252
 253   while((/* niki E2K_READ_MAS_W(i2c_spi_cntrl + SPI_STATUS, MAS_IOADDR)*/ readl(i2c_spi_cntrl + SPI_STATUS) &
 254          (SPI_STATUS_INTR | SPI_STATUS_FAIL)) == 0);
 255
 256   if (/*niki E2K_READ_MAS_W(i2c_spi_cntrl + SPI_STATUS, MAS_IOADDR)*/ readl(i2c_spi_cntrl + SPI_STATUS) & SPI_STATUS_FAIL) {
 257     printk("spi_ops: Error - Operation Failed");
 258     return -1;
 259   }
 260   return 1;
 261 }
 262
 263 static void proc_read(char *ch);
 264
 265 static int proc_read_spi_test(char *page, char **start,
 266            off_t off, int count,
 267            int *eof, void *data)
 268 {
 269     proc_read(&tch[0]);
 270     memcpy(page, tch, strlen(tch));
 271     return strlen(tch);
 272
 273 }
 274
 275
 276 static void proc_read(char *ch)
 277 {
 278     int j, i = 0;
 279     int h, m, s, delta, r0;
 280
 281   i += sprintf(&ch[i],"Ctrl %x\n",spi_read(&i2c_spig,  0x18));
 282
 283   i += sprintf(&ch[i],"S/N: ");
 284   for (j = 0; j < 8; j++) {
 285     i += sprintf(&ch[i],"%2.2x",spi_read(&i2c_spig,  0x10 + j));
 286   }
 287
 288
 289   r0 = spi_read(&i2c_spig,  0x0);
 290   r0 |= 1;
 291   spi_write(&i2c_spig, r0, 0x0);
 292
 293   i += sprintf(&ch[i], "\n");
 294   s = spi_read(&i2c_spig,  0x2);
 295   s = (s >> 4) * 10 + (s & 0xf);
 296   m = spi_read(&i2c_spig,  0x3);
 297   m = (m >> 4) * 10 + (m & 0xf);
 298   h = spi_read(&i2c_spig,  0x4);
 299   h = (h >> 4) * 10 + (h & 0xf);
 300
 301   r0 &= 0xfe;
 302   spi_write(&i2c_spig, r0, 0x0);
 303
 304   i += sprintf(&ch[i],"RTC %.2dh %.2dm %.2ds\n",h, m, s);
 305
 306   msleep(2000);
 307
 308   r0 = spi_read(&i2c_spig,  0x0);
 309   r0 |= 1;
 310   spi_write(&i2c_spig, r0, 0x0);
 311
 312   delta = s;
 313   s = spi_read(&i2c_spig,  0x2);
 314   s = (s >> 4) * 10 + (s & 0xf);
 315   m = spi_read(&i2c_spig,  0x3);
 316   m = (m >> 4) * 10 + (m & 0xf);
 317   h = spi_read(&i2c_spig,  0x4);
 318   h = (h >> 4) * 10 + (h & 0xf);
 319
 320   r0 &= 0xfe;
 321   spi_write(&i2c_spig, r0, 0x0);
 322
 323   delta = ((delta = (s - delta)) >= 0)? (delta): (delta * -1);
 324   i += sprintf(&ch[i],"Time delay 2 sec %.2dh %.2dm %.2ds delta = %d\n",h, m, s, delta);
 325
 326   i += sprintf(&ch[i],"SPI TEST");
 327   if (delta < 1) {
 328     sprintf(&ch[i],"  ERROR\n");
 329   } else
 330     i += sprintf(&ch[i],"  OK\n");
 331
 332 }
 333
 334 static int spi_test_init_module(void)
 335 {
 336   char tmp;
 337  // int  j, i = 0;
 338   struct pci_dev *dev;
 339   unsigned int mode;
 340
 341   printk("test_fm33256: Scanning PCI bus for ioapic/pic/timer i2c/spi controller ...");
 342   dev = pci_get_device(E3M_MULTIFUNC_VENDOR, E3M_MULTIFUNC_DEVICE, 0);
 343   if (dev) {
 344     printk("found on bus %d device %d\n",
 345                dev->bus->number, PCI_SLOT(dev->devfn));
 346   }else{
 347     printk("!!! NOT FOUND !!!\n");
 348     return -1;
 349   }
 350   printk("test_fm33256: control base addr = 0x%x, data base addr = 0x%x\n",
 351              (unsigned int) pci_resource_start( dev, 0), (unsigned int) pci_resource_start( dev, 1));
 352   i2c_spig.cntrl_base = ioremap( pci_resource_start(dev, 0), pci_resource_len(dev, 0) ); // niki pci_resource_start( dev, 0);
 353   i2c_spig.data_base = ioremap( pci_resource_start(dev, 1), pci_resource_len(dev, 1) ); // niki pci_resource_start( dev, 1);
 354   i2c_spig.dev_number = 1;
 355
 356   mode = spi_interrupt_lock(&i2c_spig);
 357   tmp = spi_read(&i2c_spig,  0x18);
 358
 359   //proc_read(&tch[0]);
 360
 361   proc_dev = create_proc_entry("spi_test", 0444, NULL);
 362   if(proc_dev == NULL)
 363     return -1;
 364   strcpy((char *)proc_dev->name, "spi_test");
 365   //    strcpy(device->proc_dev->value, proc_name);
 366   proc_dev->data = NULL;
 367   proc_dev->read_proc = proc_read_spi_test;
 368   proc_dev->write_proc = NULL;
 369
 370 //  printk("%s \n", tch);
 371   spi_interrupt_reset(&i2c_spig);
 372   spi_interrupt_unlock(&i2c_spig, mode);
 373
 374
 375  return 0;
 376 }
 377
 378 static void spi_test_exit_module(void)
 379 {
 380   iounmap(i2c_spig.cntrl_base);
 381   iounmap(i2c_spig.data_base);
 382   remove_proc_entry( "spi_test", proc_dev );
 383 }
 384
 385
 386 module_init(spi_test_init_module);
 387 module_exit(spi_test_exit_module);
 388
 389 MODULE_DESCRIPTION( "SPI Test of e3s" );
 390 MODULE_AUTHOR     ( "Aleksey Nikiforov" );
 391 MODULE_LICENSE    ( "GPL" );
 392
 393