| blob | 967d4f1fe9b4c2bc772443ac89c8c6e0c57cbfaa |
1 /*******************************************************************
2 *Copyright (c) 2012 by Silicon Motion, Inc. (SMI)
3 *Permission is hereby granted, free of charge, to any person obtaining a copy
4 *of this software and associated documentation files (the "Software"), to deal
5 *in the Software without restriction, including without limitation the rights to
6 *use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
7 *of the Software, and to permit persons to whom the Software is furnished to
8 *do so, subject to the following conditions:
9 *
10 *THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 *EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
12 *OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 *NONINFRINGEMENT. IN NO EVENT SHALL Mill.Chen and Monk.Liu OR COPYRIGHT
14 *HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
15 *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
16 *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
17 *OTHER DEALINGS IN THE SOFTWARE.
18 *******************************************************************/
25 #ifdef CONFIG_FB_LYNXFB_DOMAINS
26 #define primaryWaitVerticalSync(delay, domain) waitNextVerticalSync(0, delay, domain)
29 {
30 /* state != 0 means turn on both timing & plane en_bit */
36 /* Set the primary display control */
39 /* Turn on/off the Panel display control */
41 /* Timing should be enabled first before enabling the plane
42 * because changing at the same time does not guarantee that
43 * the plane will also enabled or disabled.
44 */
45 ulDisplayCtrlReg =
47 PANEL_DISPLAY_CTRL_TIMING_LSB);
50 ulDisplayCtrlReg =
52 PANEL_DISPLAY_CTRL_PLANE_LSB);
53 /* Added some masks to mask out the reserved bits.
54 * Sometimes, the reserved bits are set/reset randomly when
55 * writing to the PRIMARY_DISPLAY_CTRL, therefore, the register
56 * reserved bits are needed to be masked out.
57 */
58 ulReservedBits =
62 PANEL_DISPLAY_CTRL_RESERVED_3_MASK_LSB);
64 /* Somehow the register value on the plane is not set
65 * until a few delay. Need to write
66 * and read it a couple times
67 */
69 cnt++;
75 /* printk
76 * ("Set Panel Plane enbit:after tried %d times\n",
77 * cnt);
78 */
80 /* When turning off, there is no rule on the programming
81 * sequence since whenever the clock is off, then it does not
82 * matter whether the plane is enabled or disabled.
83 * Note: Modifying the plane bit will take effect on the
84 * next vertical sync. Need to find out if it is necessary to
85 * wait for 1 vsync before modifying the timing enable bit.
86 * */
87 ulDisplayCtrlReg =
88 ulDisplayCtrlReg &
92 ulDisplayCtrlReg =
93 ulDisplayCtrlReg &
96 }
99 /* Set the secondary display control */
103 /* Timing should be enabled first before enabling the plane because changing at the
104 same time does not guarantee that the plane will also enabled or disabled.
105 */
106 ulDisplayCtrlReg =
108 CRT_DISPLAY_CTRL_TIMING_LSB);
111 ulDisplayCtrlReg =
113 CRT_DISPLAY_CTRL_PLANE_LSB);
115 /* Added some masks to mask out the reserved bits.
116 * Sometimes, the reserved bits are set/reset randomly when
117 * writing to the PRIMARY_DISPLAY_CTRL, therefore, the register
118 * reserved bits are needed to be masked out.
119 */
121 ulReservedBits =
127 cnt++;
132 printk
134 cnt);
136 /* When turning off, there is no rule on the programming
137 * sequence since whenever the clock is off, then it does not
138 * matter whether the plane is enabled or disabled.
139 * Note: Modifying the plane bit will take effect on the next
140 * vertical sync. Need to find out if it is necessary to
141 * wait for 1 vsync before modifying the timing enable bit.
142 */
143 ulDisplayCtrlReg =
144 ulDisplayCtrlReg &
148 ulDisplayCtrlReg =
149 ulDisplayCtrlReg &
152 }
153 }
154 }
158 {
161 /* primary controller */
163 /* Do not wait when the Primary PLL is off or display control is already off.
164 This will prevent the software to wait forever. */
168 ||
171 PANEL_DISPLAY_CTRL_TIMING_LSB)) ==
172 PANEL_DISPLAY_CTRL_TIMING_DISABLE)) {
174 }
176 /* Wait for end of vsync. */
178 status =
180 SYSTEM_CTRL_PANEL_VSYNC_LSB);
183 /* Wait for start of vsync. */
185 status =
187 SYSTEM_CTRL_PANEL_VSYNC_LSB);
189 SYSTEM_CTRL_PANEL_VSYNC_INACTIVE);
190 }
194 /* Do not wait when the Primary PLL is off or display control is already off.
195 This will prevent the software to wait forever. */
199 CRT_DISPLAY_CTRL_TIMING_LSB)) ==
200 CRT_DISPLAY_CTRL_TIMING_DISABLE)) {
202 }
205 /* Wait for end of vsync. */
207 status =
209 SYSTEM_CTRL_CRT_VSYNC_LSB);
212 /* Wait for start of vsync. */
214 status =
216 SYSTEM_CTRL_CRT_VSYNC_LSB);
218 }
219 }
220 }
223 {
228 else
231 }
234 {
237 /* disp should be 1 to open sequence */
262 }
265 {
268 /* set panel path controller select */
271 reg =
273 PANEL_DISPLAY_CTRL_SELECT_LSB;
275 }
278 /* set crt path controller select */
281 reg =
283 CRT_DISPLAY_CTRL_SELECT_LSB;
284 /*se blank off */
287 }
289 /* set primary timing and plane en_bit */
292 }
295 /* set secondary timing and plane en_bit */
298 }
301 /* set panel sequence */
304 }
311 }
314 {
315 /* Initialize DVI. If the dviInit fail and the VendorID or the DeviceID are
316 not zeroed, then set the failure flag. If it is zeroe, it might mean
317 that the system is in Dual CRT Monitor configuration. */
319 /* De-skew enabled with default 111b value.
320 This will fix some artifacts problem in some mode on board 2.2.
321 Somehow this fix does not affect board 2.1.
322 */
333 domain
337 }
339 /* TODO: Initialize other display component */
341 /* Success */
344 }
347 #define primaryWaitVerticalSync(delay) waitNextVerticalSync(0, delay)
350 {
351 /* state != 0 means turn on both timing & plane en_bit */
357 /* Set the primary display control */
360 /* Turn on/off the Panel display control */
362 /* Timing should be enabled first before enabling the plane
363 * because changing at the same time does not guarantee that
364 * the plane will also enabled or disabled.
365 */
366 ulDisplayCtrlReg =
368 PANEL_DISPLAY_CTRL_TIMING_LSB);
371 ulDisplayCtrlReg =
373 PANEL_DISPLAY_CTRL_PLANE_LSB);
374 /* Added some masks to mask out the reserved bits.
375 * Sometimes, the reserved bits are set/reset randomly when
376 * writing to the PRIMARY_DISPLAY_CTRL, therefore, the register
377 * reserved bits are needed to be masked out.
378 */
379 ulReservedBits =
383 PANEL_DISPLAY_CTRL_RESERVED_3_MASK_LSB);
385 /* Somehow the register value on the plane is not set
386 * until a few delay. Need to write
387 * and read it a couple times
388 */
390 cnt++;
392 ulDisplayCtrlReg);
396 printk
398 cnt);
400 /* When turning off, there is no rule on the programming
401 * sequence since whenever the clock is off, then it does not
402 * matter whether the plane is enabled or disabled.
403 * Note: Modifying the plane bit will take effect on the
404 * next vertical sync. Need to find out if it is necessary to
405 * wait for 1 vsync before modifying the timing enable bit.
406 * */
407 ulDisplayCtrlReg =
408 ulDisplayCtrlReg &
412 ulDisplayCtrlReg =
413 ulDisplayCtrlReg &
416 }
419 /* Set the secondary display control */
423 /* Timing should be enabled first before enabling the plane because changing at the
424 same time does not guarantee that the plane will also enabled or disabled.
425 */
426 ulDisplayCtrlReg =
428 CRT_DISPLAY_CTRL_TIMING_LSB);
431 ulDisplayCtrlReg =
433 CRT_DISPLAY_CTRL_PLANE_LSB);
435 /* Added some masks to mask out the reserved bits.
436 * Sometimes, the reserved bits are set/reset randomly when
437 * writing to the PRIMARY_DISPLAY_CTRL, therefore, the register
438 * reserved bits are needed to be masked out.
439 */
441 ulReservedBits =
447 cnt++;
452 printk
454 cnt);
456 /* When turning off, there is no rule on the programming
457 * sequence since whenever the clock is off, then it does not
458 * matter whether the plane is enabled or disabled.
459 * Note: Modifying the plane bit will take effect on the next
460 * vertical sync. Need to find out if it is necessary to
461 * wait for 1 vsync before modifying the timing enable bit.
462 */
463 ulDisplayCtrlReg =
464 ulDisplayCtrlReg &
468 ulDisplayCtrlReg =
469 ulDisplayCtrlReg &
472 }
473 }
474 }
478 {
481 /* primary controller */
483 /* Do not wait when the Primary PLL is off or display control is already off.
484 This will prevent the software to wait forever. */
488 ||
491 PANEL_DISPLAY_CTRL_TIMING_LSB)) ==
492 PANEL_DISPLAY_CTRL_TIMING_DISABLE)) {
494 }
496 /* Wait for end of vsync. */
498 status =
500 SYSTEM_CTRL_PANEL_VSYNC_LSB);
503 /* Wait for start of vsync. */
505 status =
507 SYSTEM_CTRL_PANEL_VSYNC_LSB);
509 SYSTEM_CTRL_PANEL_VSYNC_INACTIVE);
510 }
514 /* Do not wait when the Primary PLL is off or display control is already off.
515 This will prevent the software to wait forever. */
519 CRT_DISPLAY_CTRL_TIMING_LSB)) ==
520 CRT_DISPLAY_CTRL_TIMING_DISABLE)) {
522 }
525 /* Wait for end of vsync. */
527 status =
529 SYSTEM_CTRL_CRT_VSYNC_LSB);
532 /* Wait for start of vsync. */
534 status =
536 SYSTEM_CTRL_CRT_VSYNC_LSB);
538 }
539 }
540 }
543 {
548 else
551 }
554 {
557 /* disp should be 1 to open sequence */
582 }
585 {
588 /* set panel path controller select */
591 reg =
593 PANEL_DISPLAY_CTRL_SELECT_LSB;
595 }
598 /* set crt path controller select */
601 reg =
603 CRT_DISPLAY_CTRL_SELECT_LSB;
604 /*se blank off */
607 }
609 /* set primary timing and plane en_bit */
612 }
615 /* set secondary timing and plane en_bit */
618 }
621 /* set panel sequence */
624 }
631 }
634 {
635 /* Initialize DVI. If the dviInit fail and the VendorID or the DeviceID are
636 not zeroed, then set the failure flag. If it is zeroe, it might mean
637 that the system is in Dual CRT Monitor configuration. */
639 /* De-skew enabled with default 111b value.
640 This will fix some artifacts problem in some mode on board 2.2.
641 Somehow this fix does not affect board 2.1.
642 */
656 }
658 /* TODO: Initialize other display component */
660 /* Success */
663 }