drivers/video/lynxfb/ddk750_display.h

   1 /*******************************************************************
   2 *Copyright (c) 2012 by Silicon Motion, Inc. (SMI)
   3 *Permission is hereby granted, free of charge, to any person obtaining a copy
   4 *of this software and associated documentation files (the "Software"), to deal
   5 *in the Software without restriction, including without limitation the rights to
   6 *use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
   7 *of the Software, and to permit persons to whom the Software is furnished to
   8 *do so, subject to the following conditions:
   9 *
  10 *THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11 *EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  12 *OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13 *NONINFRINGEMENT.  IN NO EVENT SHALL Mill.Chen and Monk.Liu OR COPYRIGHT
  14 *HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  15 *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  16 *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  17 *OTHER DEALINGS IN THE SOFTWARE.
  18 *******************************************************************/
  19 #ifndef DDK750_DISPLAY_H__
  20 #define DDK750_DISPLAY_H__
  21
  22 /* panel path select
  23    80000[29:28]
  24    */
  25
  26 #define PNL_2_OFFSET 0
  27 #define PNL_2_MASK (3 << PNL_2_OFFSET)
  28 #define PNL_2_USAGE     (PNL_2_MASK << 16)
  29 #define PNL_2_PRI       ((0 << PNL_2_OFFSET)|PNL_2_USAGE)
  30 #define PNL_2_SEC       ((2 << PNL_2_OFFSET)|PNL_2_USAGE)
  31
  32
  33 /* primary timing & plane enable bit
  34 1: 80000[8] & 80000[2] on
  35 0: both off
  36 */
  37 #define PRI_TP_OFFSET 4
  38 #define PRI_TP_MASK (1 << PRI_TP_OFFSET)
  39 #define PRI_TP_USAGE (PRI_TP_MASK << 16)
  40 #define PRI_TP_ON ((0x1 << PRI_TP_OFFSET)|PRI_TP_USAGE)
  41 #define PRI_TP_OFF ((0x0 << PRI_TP_OFFSET)|PRI_TP_USAGE)
  42
  43
  44 /* panel sequency status
  45    80000[27:24]
  46    */
  47 #define PNL_SEQ_OFFSET 6
  48 #define PNL_SEQ_MASK (1 << PNL_SEQ_OFFSET)
  49 #define PNL_SEQ_USAGE (PNL_SEQ_MASK << 16)
  50 #define PNL_SEQ_ON ((1 << PNL_SEQ_OFFSET)|PNL_SEQ_USAGE)
  51 #define PNL_SEQ_OFF ((0 << PNL_SEQ_OFFSET)|PNL_SEQ_USAGE)
  52
  53 /* dual digital output
  54    80000[19]
  55    */
  56 #define DUAL_TFT_OFFSET 8
  57 #define DUAL_TFT_MASK (1 << DUAL_TFT_OFFSET)
  58 #define DUAL_TFT_USAGE (DUAL_TFT_MASK << 16)
  59 #define DUAL_TFT_ON ((1 << DUAL_TFT_OFFSET)|DUAL_TFT_USAGE)
  60 #define DUAL_TFT_OFF ((0 << DUAL_TFT_OFFSET)|DUAL_TFT_USAGE)
  61
  62 /* secondary timing & plane enable bit
  63 1:80200[8] & 80200[2] on
  64 0: both off
  65 */
  66 #define SEC_TP_OFFSET 5
  67 #define SEC_TP_MASK (1 << SEC_TP_OFFSET)
  68 #define SEC_TP_USAGE (SEC_TP_MASK << 16)
  69 #define SEC_TP_ON  ((0x1 << SEC_TP_OFFSET)|SEC_TP_USAGE)
  70 #define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET)|SEC_TP_USAGE)
  71
  72 /* crt path select
  73    80200[19:18]
  74    */
  75 #define CRT_2_OFFSET 2
  76 #define CRT_2_MASK (3 << CRT_2_OFFSET)
  77 #define CRT_2_USAGE (CRT_2_MASK << 16)
  78 #define CRT_2_PRI ((0x0 << CRT_2_OFFSET)|CRT_2_USAGE)
  79 #define CRT_2_SEC ((0x2 << CRT_2_OFFSET)|CRT_2_USAGE)
  80
  81
  82 /* DAC affect both DVI and DSUB
  83    4[20]
  84    */
  85 #define DAC_OFFSET 7
  86 #define DAC_MASK (1 << DAC_OFFSET)
  87 #define DAC_USAGE (DAC_MASK << 16)
  88 #define DAC_ON ((0x0 << DAC_OFFSET)|DAC_USAGE)
  89 #define DAC_OFF ((0x1 << DAC_OFFSET)|DAC_USAGE)
  90
  91 /* DPMS only affect D-SUB head
  92    0[31:30]
  93    */
  94 #define DPMS_OFFSET 9
  95 #define DPMS_MASK (3 << DPMS_OFFSET)
  96 #define DPMS_USAGE (DPMS_MASK << 16)
  97 #define DPMS_OFF ((3 << DPMS_OFFSET)|DPMS_USAGE)
  98 #define DPMS_ON ((0 << DPMS_OFFSET)|DPMS_USAGE)
  99
 100
 101
 102 /*
 103    LCD1 means panel path TFT1  & panel path DVI (so enable DAC)
 104    CRT means crt path DSUB
 105    */
 106
 107 typedef enum _disp_output_t {
 108         do_LCD1_PRI = PNL_2_PRI | PRI_TP_ON | PNL_SEQ_ON | DAC_ON,
 109         do_LCD1_SEC = PNL_2_SEC | SEC_TP_ON | PNL_SEQ_ON | DAC_ON,
 110         do_LCD2_PRI = CRT_2_PRI | PRI_TP_ON | DUAL_TFT_ON,
 111         do_LCD2_SEC = CRT_2_SEC | SEC_TP_ON | DUAL_TFT_ON,
 112         /*
 113            do_DSUB_PRI = CRT_2_PRI|PRI_TP_ON|DPMS_ON|DAC_ON,
 114            do_DSUB_SEC = CRT_2_SEC|SEC_TP_ON|DPMS_ON|DAC_ON,
 115          */
 116         do_CRT_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON | DAC_ON,
 117         do_CRT_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON | DAC_ON,
 118 } disp_output_t;
 119
 120 #ifdef CONFIG_FB_LYNXFB_DOMAINS
 121 void ddk750_setLogicalDispOut(disp_output_t, int);
 122 int ddk750_initDVIDisp(int);
 123 #else
 124 void ddk750_setLogicalDispOut(disp_output_t);
 125 int ddk750_initDVIDisp(void);
 126 #endif /* CONFIG_FB_LYNXFB_DOMAINS  */
 127
 128 #endif