| blob | 98adc390c5375a3d355bdb5118fc73b67dd56d9d |
1 /*******************************************************************
2 *Copyright (c) 2012 by Silicon Motion, Inc. (SMI)
3 *Permission is hereby granted, free of charge, to any person obtaining a copy
4 *of this software and associated documentation files (the "Software"), to deal
5 *in the Software without restriction, including without limitation the rights to
6 *use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
7 *of the Software, and to permit persons to whom the Software is furnished to
8 *do so, subject to the following conditions:
9 *
10 *THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 *EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
12 *OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 *NONINFRINGEMENT. IN NO EVENT SHALL Mill.Chen and Monk.Liu OR COPYRIGHT
14 *HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
15 *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
16 *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
17 *OTHER DEALINGS IN THE SOFTWARE.
18 *******************************************************************/
24 #ifdef CONFIG_FB_LYNXFB_DOMAINS
25 /*
26 SM750LE only:
27 This function takes care extra registers and bit fields required to set
28 up a mode in SM750LE
30 Explanation about Display Control register:
31 HW only supports 7 predefined pixel clocks, and clock select is
32 in bit 29:27 of Display Control register.
33 */
35 pModeParam,
36 unsigned long
37 dispControl,
39 {
45 /* SM750LE has to set up the top-left and bottom-right
46 registers as well.
47 Note that normal SM750/SM718 only use those two register for
48 auto-centering mode.
49 */
54 /*clear */
61 /* Clear bit 29:27 of display control register */
63 /* Assume common fields in dispControl have been properly set before
64 calling this function.
65 This function only sets the extra fields in dispControl.
66 */
69 /* Set bit 29:27 of display control register for the right clock */
70 /* Note that SM750LE only need to supported 7 resoluitons. */
89 /* Set bit 25:24 of display controller */
93 /* Set bit 14 of display controller */
99 }
101 /* only timing related registers will be programed */
104 {
109 /* programe secondary pixel clock */
119 horizontal_sync_width <<
120 CRT_HORIZONTAL_SYNC_WIDTH_LSB)
131 vertical_sync_height <<
132 CRT_VERTICAL_SYNC_HEIGHT_LSB)
137 ulTmpValue =
139 vertical_sync_polarity <<
141 horizontal_sync_polarity
142 <<
143 CRT_DISPLAY_CTRL_HSYNC_PHASE_LSB)
145 CRT_DISPLAY_CTRL_PLANE_LSB);
157 }
170 horizontal_sync_width <<
171 PANEL_HORIZONTAL_SYNC_WIDTH_LSB)
183 PANEL_VERTICAL_SYNC_HEIGHT_LSB)
186 ulTmpValue =
188 PANEL_DISPLAY_CTRL_VSYNC_PHASE_LSB)
190 PANEL_DISPLAY_CTRL_HSYNC_PHASE_LSB)
192 PANEL_DISPLAY_CTRL_CLOCK_PHASE_LSB)
195 ulReservedBits =
197 PANEL_DISPLAY_CTRL_RESERVED_2_MASK_LSB)
199 PANEL_DISPLAY_CTRL_VSYNC_LSB);
207 /* May a hardware bug or just my test chip (not confirmed).
208 * PANEL_DISPLAY_CTRL register seems requiring few writes
209 * before a value can be succesfully written in.
210 * Added some masks to mask out the reserved bits.
211 * Note: This problem happens by design. The hardware will wait for the
212 * next vertical sync to turn on/off the plane.
213 */
219 cnt++;
223 }
227 }
229 }
232 {
233 pll_value_t pll;
240 /* set graphic mode via IO method */
243 }
246 }
249 /*
250 SM750LE only:
251 This function takes care extra registers and bit fields required to set
252 up a mode in SM750LE
254 Explanation about Display Control register:
255 HW only supports 7 predefined pixel clocks, and clock select is
256 in bit 29:27 of Display Control register.
257 */
259 pModeParam,
260 unsigned long
261 dispControl)
262 {
268 /* SM750LE has to set up the top-left and bottom-right
269 registers as well.
270 Note that normal SM750/SM718 only use those two register for
271 auto-centering mode.
272 */
277 /*clear */
284 /* Clear bit 29:27 of display control register */
286 /* Assume common fields in dispControl have been properly set before
287 calling this function.
288 This function only sets the extra fields in dispControl.
289 */
292 /* Set bit 29:27 of display control register for the right clock */
293 /* Note that SM750LE only need to supported 7 resoluitons. */
312 /* Set bit 25:24 of display controller */
316 /* Set bit 14 of display controller */
322 }
326 /* only timing related registers will be programed */
329 {
334 /* programe secondary pixel clock */
340 CRT_HORIZONTAL_TOTAL_DISPLAY_END_LSB));
344 horizontal_sync_width <<
345 CRT_HORIZONTAL_SYNC_WIDTH_LSB)
347 CRT_HORIZONTAL_SYNC_START_LSB));
353 CRT_VERTICAL_TOTAL_DISPLAY_END_LSB));
356 vertical_sync_height <<
357 CRT_VERTICAL_SYNC_HEIGHT_LSB)
359 CRT_VERTICAL_SYNC_START_LSB));
362 ulTmpValue =
364 vertical_sync_polarity <<
366 horizontal_sync_polarity
367 <<
368 CRT_DISPLAY_CTRL_HSYNC_PHASE_LSB)
370 CRT_DISPLAY_CTRL_PLANE_LSB);
374 ulTmpValue);
382 }
391 PANEL_HORIZONTAL_TOTAL_DISPLAY_END_LSB));
395 horizontal_sync_width <<
396 PANEL_HORIZONTAL_SYNC_WIDTH_LSB)
398 PANEL_HORIZONTAL_SYNC_START_LSB));
404 PANEL_VERTICAL_TOTAL_DISPLAY_END_LSB));
408 PANEL_VERTICAL_SYNC_HEIGHT_LSB)
410 PANEL_VERTICAL_SYNC_START_LSB));
411 ulTmpValue =
413 PANEL_DISPLAY_CTRL_VSYNC_PHASE_LSB)
415 PANEL_DISPLAY_CTRL_HSYNC_PHASE_LSB)
417 PANEL_DISPLAY_CTRL_CLOCK_PHASE_LSB)
420 ulReservedBits =
422 PANEL_DISPLAY_CTRL_RESERVED_2_MASK_LSB)
424 PANEL_DISPLAY_CTRL_VSYNC_LSB);
432 /* May a hardware bug or just my test chip (not confirmed).
433 * PANEL_DISPLAY_CTRL register seems requiring few writes
434 * before a value can be succesfully written in.
435 * Added some masks to mask out the reserved bits.
436 * Note: This problem happens by design. The hardware will wait for the
437 * next vertical sync to turn on/off the plane.
438 */
444 cnt++;
448 }
452 }
454 }
457 {
458 pll_value_t pll;
465 /* set graphic mode via IO method */
468 }
471 }