drivers/video/mgam83/sbus_mgam83fb.h

   1 /* linux/drivers/video/mgam83/mgam83fb.h
   2  *
   3  * Copyright (C) 2005, Alexander Shmelev <ashmelev@task.sun.mcst.ru>
   4  *
   5  */
   6
   7 #ifndef __MGAM83FB_H
   8 #define __MGAM83FB_H
   9
  10 /*******************************************************************************
  11  * Debug
  12  *******************************************************************************
  13  */
  14
  15 #ifdef CONFIG_FB_MGAM83_DEBUG
  16 #define MGA_DEBUG
  17 #endif
  18 //#define MGA_TRACE
  19 //#define MGA_CHECKPOINT
  20
  21 /*******************************************************************************
  22  * Model specific defines
  23  *******************************************************************************
  24  */
  25
  26 #define BUS_TYPE_SBUS   2
  27
  28
  29 //
  30 // SBUS
  31 //
  32 #if defined (CONFIG_SBUS)
  33 // device identificatoors
  34 #define MGA_PROM_NAME   "mga"
  35
  36 #elif defined(CONFIG_PCI2SBUS_MODULE)
  37 // device identificatoors
  38 #define MGA_PROM_NAME   "MCST, MGA/M"
  39
  40 #endif
  41
  42 #if defined (CONFIG_SBUS) || defined (CONFIG_PCI2SBUS_MODULE)
  43
  44 // sbus_dev.resource[]
  45 #define SBUS_FCODE_BAR          0
  46 #define SBUS_MMIO_BAR           1
  47 #define SBUS_I2C_BAR            2
  48 #define SBUS_MEM_BAR            3
  49
  50 #define SBUS_MEM_PIXCLOCK       7518
  51
  52 #endif  /* CONFIG_SBUS */
  53
  54
  55 #define MGA_MEM_SIZE            0x800000
  56
  57
  58
  59 /*******************************************************************************
  60  * Device Description
  61  *******************************************************************************
  62  */
  63
  64
  65 /*******************************************************************************
  66  * MMIO Registers
  67  *******************************************************************************
  68  */
  69 #define REG_CTRL        0x000   // Control Register
  70 #define REG_STAT        0x004   // Status Register
  71 #define REG_HTIM        0x008   // Horizontal Timing Register
  72 #define REG_VTIM        0x00c   // Vertical Timing Register
  73 #define REG_HVLEN       0x010   // Horizontal and Vertical Length Register
  74 #define REG_VBARa       0x014   // Video Memory Base Address Register A
  75 #define REG_VBARb       0x018   // Video Memory Base Address Register B
  76 #define REG_C0XY        0x030   // Cursor 0 X,Y Register
  77 #define REG_C0BAR       0x034   // Cursor0 Base Address register
  78 #define REG_C0CR        0x040   // Cursor0 Color Registers
  79 #define REG_C1XY        0x070   // Cursor 0 X,Y Register
  80 #define REG_C1BAR       0x074   // Cursor0 Base Address register
  81 #define REG_C1CR        0x080   // Cursor0 Color Registers
  82 #define REG_PCLT        0x800   // 8bpp Pseudo Color Lockup Table
  83 #define REG_TST_D       0x01C   // Test Mode
  84 #define REG_BUGFIX      0x0F8   // Bugfix register
  85
  86 // BitBlt module registers
  87 #define BBR0            0x1000          // CTRL_REG if writing
  88                                         // STAT_REG if reading
  89 #define BBR1            0x1004          // WINDOW_REG (size of the window to copy)
  90 #define BBR2            0x1008          // SADDR_REG (Source address reg - byte offset
  91                                         // inside framebuffer) invisible framebuffer part
  92 #define BBR3            0x100c          // DADDR_REG (Destination address reg - byte offset
  93                                         // inside framebuffer) visible framebuffer part
  94 #define BBR4            0x1010          // PITCH_REG (value to increment both SADDR_REG and
  95                                         // DADDR_REG to have them pointing to the next
  96                                         // lines of WINDOWS (source and destination windows
  97                                         // respecteviely)). PITCH_REG has 2 parts. The highest 16
  98                                         // little-endian bits are for the destination and the lowest
  99                                         // ones are for the source. Determined in bytes
 100 #define BBR5            0x1014          // BG_REG - Background color (color extenshion mode for
 101                                         // originally monochromed color only)
 102 #define BBR6            0x1018          // FG_REG - Foreground color (color extenshion mode for
 103                                         // originally monochromed color only)
 104 #define BBR7            0x101c          // RESERVED
 105         /* Bit feilds for CTRL_REG (little-endian mode) */
 106 #define CE_EN           (1 << 0)        // Enable color extenshion (for
 107                                         // originally monochromed color only)
 108 #define PAT_EN          (1 << 1)        // Enable 8x8 pattern multiplication
 109                                         // (Pattern Copy). Doesn't work if
 110                                         // continuous address generation for source
 111                                         // is enabled.
 112 #define SFILL_EN        (1 << 2)        // Enable continuous color pouring mode
 113                                         // Works only in color extenshion mode
 114 #define INV_EN          (1 << 3)        // monochromed image invertion mode
 115                                         // Works only in color extenshion mode
 116 #define TR_EN           (1 << 4)        // Transparency mode
 117                                         // Works only in color extenshion mode
 118 #define HDIR            (1 << 5)        // Horizontal (when drawing a line of WINDOW)
 119                                         // incrementation sign (0 --->; 1 <---;)
 120 #define VDIR            (1 << 6)        // Vertical incrementation sign (0 --->; 1 <---;)
 121                                         // The same as PITCH_REG parts sign
 122 #define SRC_MODE        (1 << 7)        // Enable address generation for source
 123                                         // If enabled makes module to increment source
 124                                         // address continuously inspite of lowest part of
 125                                         // PITCH_REG. (This mode has to be enabled if you
 126                                         // want to have your image object continuous in
 127                                         // invisible part of framebuffer memory due to economy
 128                                         // reason i think)
 129 /*#define TERM_MODE*///FIXME            // 32 bits word alignment when reached end of a line
 130                                         // Address generation for source mode only
 131 #define BPP_08          (0x00 << 10)
 132 #define BPP_16          (0x01 << 10)
 133 #define BPP_24          (0x02 << 10)
 134 #define BPP_32          (0x03 << 10)
 135
 136 #define ROP_02          (0x02 << 12)    // DST = DST &~ SRC
 137 #define ROP_03          (0x03 << 12)    // DST = DST
 138 #define ROP_04          (0x04 << 12)    // DST = ~DST & SRC
 139 #define ROP_05          (0x05 << 12)    // DST = SRC
 140 #define ROP_06          (0x06 << 12)    // DST = DST != SRC
 141 #define ROP_07          (0x07 << 12)    // DST = DST | SRC
 142 #define ROP_08          (0x08 << 12)    // DST = ~DST &~ SRC
 143 #define ROP_09          (0x09 << 12)    // DST = DST == SRC
 144 #define ROP_0A          (0x0a << 12)    // DST = ~SRC
 145 #define ROP_0B          (0x0b << 12)    // DST = DST | ~SRC
 146 #define ROP_0C          (0x0c << 12)    // DST = ~DST
 147 #define ROP_0D          (0x0d << 12)    // DST = ~DST | SRC
 148 #define ROP_0E          (0x0e << 12)    // DST = ~DST | ~SRC
 149 #define ROP_0F          (0x0f << 12)    // DST = {1}
 150
 151 #define SOFFS_MASK      (0x7 << 16)
 152
 153 #define SDMA_EN         (1 << 20)       // Enable DMA for Source
 154 #define DDMA_EN         (1 << 21)       // Enable DMA for Destination
 155
 156 #define PAUSE           (1 << 27)       // BitBlt operation delay
 157                                         // Used for the executive control only
 158 #define NFIE            (1 << 28)       // Enable interrupt in the case of unfilling
 159                                         // task buffer
 160                                         // Used for the executive control only
 161 #define NPIE            (1 << 29)       // Enable interrupt in the case of unexecuting
 162                                         // of BitBlt operation
 163                                         // Used for the executive control only
 164 #define ABORT           (1 << 30)       // BitBlt operation abortion
 165 #define START           (1 << 31)       // BitBlt operation starting
 166         /* Bit feilds for STAT_REG (little-endian mode) */
 167 #define FULL            (1 << 30)       // Double buffering state
 168                                         // 0 - Buffer isn't filled up, so another
 169                                         // operation may be initiated
 170                                         // 1 - Buffer is filled up
 171 #define PROCESS         (1 << 31)       // BitBlt operation carring out state
 172                                         // 0 - The module isn't carring out BitBlt operation
 173                                         // 1 - BitBlt operation is running
 174
 175         /* for BitBlt operation */
 176 #define BITS_IN_BYTE_TWISTER            (1 << 22)
 177 #define BYTES_IN_WORDS16_TWISTER        (1 << 23)
 178 #define WORDS16_IN_WORDS32_TWISTER      (1 << 24)
 179
 180 // Control Register REG_CTRL
 181         /* for Processor operation */
 182 #define CTRL_WORDS16_IN_WORDS32_TWISTER (0x1<<31)
 183 #define CTRL_IN_WORDS16_TWISTER         (0x1<<30)
 184
 185 #define CTRL_SAP
 186 #define CTRL_HC1R_32    0               // Hardware Cursor1 Resolution 32x32
 187 #define CTRL_HC1R_64    (0x1<<25)       //                             64x64
 188 #define CTRL_HC1E       (0x1<<24)       // Hardware Cursor1 Enabled
 189 #define CTRL_HC0R_32    0               // Hardware Cursor0 Resolution 32x32
 190 #define CTRL_HC0R_64    (0x1<<21)       //                             64x64
 191 #define CTRL_HC0E       (0x1<<20)       // Hardware Cursor0 Enabled
 192 #define CTRL_TST        (0x1<<17)       // TODO: ?????
 193 #define CTRL_BL_POS     0               // Blanking Polarization Level Positive
 194 #define CTRL_BL_NEG     (0x1<<15)       //                             Negative
 195 #define CTRL_CSYNC_HIGH 0               // Composite Synchronization Pulse Polarization Level Positive
 196 #define CTRL_CSYNC_LOW  (0x1<<14)       //                                                    Negative
 197 #define CTRL_VSYNC_HIGH 0               // Vertical Synchronization Pulse Polarization Level Positive
 198 #define CTRL_VSYNC_LOW  (0x1<<13)       //                                                   Negative
 199 #define CTRL_HSYNC_HIGH 0               // Horizontal Synchronization Pulse polarization Level Positive
 200 #define CTRL_HSYNC_LOW  (0x1<<12)       //                                                     Negative
 201
 202 #define CTRL_PC_GRAY    0               // 8-bit Pseudo Color Grayscale
 203 #define CTRL_PC_PSEUDO  (0x1<<11)       //                    Pseudo Color
 204
 205 #define CTRL_CD_8BPP    0               // Color Depth  8bpp
 206 #define CTRL_CD_16BPP   (0x1<<9)        //             16bpp
 207 #define CTRL_CD_24BPP   (0x2<<9)        //             24bpp
 208 #define CTRL_CD_32BPP   (0x3<<9)        //             32bpp
 209
 210 #define CTRL_VBL_1      0               // Video Memory Burst Length 1 cycle
 211 #define CTRL_VBL_2      (0x1<<7)        //                           2 cycles
 212 #define CTRL_VBL_4      (0x2<<7)        //                           4 cycles
 213 #define CTRL_VBL_8      (0x3<<7)        //                           8 cycles
 214 #define CTRL_VBL1024    (0x203<<7)      //                          16 cycles (extension)
 215
 216 #define CTRL_CBSWE      (0x1<<6)        // CLUT Bank Switching Enable
 217 #define CTRL_VBSWE      (0x1<<5)        // Video Bank Switching Enable
 218 #define CTRL_CBSIE      (0x1<<4)        // CLUT Bank Switch Interrupt Enable
 219 #define CTRL_VBSIE      (0x1<<3)        // VideoBank Switch Interrupt Enable
 220 #define CTRL_HIE        (0x1<<2)        // HSync Interrupt Enable
 221 #define CTRL_VIE        (0x1<<1)        // VSync Interrupt Enable
 222 #define CTRL_VEN        (0x1<<0)                // Video Enable
 223
 224 // Status Register REG_STAT
 225 #define STAT_HC1A       (0x1<<24)       // Hardware cursor1 available
 226 #define STAT_HC0A       (0x1<<20)       // Hardware cursor0 available
 227 #define STAT_ACMP       (0x1<<17)       // Active CLUT Memory Page
 228 #define STAT_AVMP       (0x1<<16)       // Active Video Memory Page
 229 #define STAT_CBSINT     (0x1<<7)        // CLUT Bank Switch Interrupt Pending
 230 #define STAT_VBSINT     (0x1<<6)        // Bank Switch Interrupt Pending
 231 #define STAT_HINT       (0x1<<5)        // Horizontal Interrupt Pending
 232 #define STAT_VINT       (0x1<<4)        // Vertical Interrupt Pending
 233 #define STAT_LUINT      (0x1<<1)        // Line FIFO Under-Run Interrupt Pending
 234 #define STAT_SINT       (0x1<<0)        // System Error Interrupt Pending
 235
 236 /*******************************************************************************
 237  * Helper macros
 238  *******************************************************************************
 239  */
 240
 241 #define MGA_PFX         "mgam83fb: "
 242
 243 #ifdef MGA_DEBUG
 244 #define DEBUG_MSG(x...) printk( KERN_DEBUG MGA_PFX x )
 245 #else
 246 #define DEBUG_MSG(x...)
 247 #endif
 248
 249 #ifdef MGA_TRACE
 250 #define TRACE_MSG(x...) printk( KERN_DEBUG MGA_PFX x )
 251 #else
 252 #define TRACE_MSG(x...)
 253 #endif
 254
 255 #ifdef MGA_CHECKPOINT
 256 #define CHECKPOINT printk( KERN_DEBUG MGA_PFX "Checkpoint: %s %s %d\n", __FILE__, __FUNCTION__, __LINE__ )
 257 #define CHECKPOINT_ENTER printk( KERN_DEBUG MGA_PFX "ENTER: %s %s %d\n", __FILE__, __FUNCTION__, __LINE__ )
 258 #define CHECKPOINT_LEAVE printk( KERN_DEBUG MGA_PFX "LEAVE: %s %s %d\n", __FILE__, __FUNCTION__, __LINE__ )
 259 #define CHECKPOINT_STR(x) printk( KERN_DEBUG MGA_PFX "CHECKPOINT: %s %s %s %d\n", x, __FILE__, __FUNCTION__, __LINE__ )
 260 #else
 261 #define CHECKPOINT
 262 #define CHECKPOINT_ENTER
 263 #define CHECKPOINT_LEAVE
 264 #define CHECKPOINT_STR(x)
 265 #endif
 266
 267 #define INFO_MSG(x...) printk( KERN_INFO MGA_PFX x )
 268 #define WARN_MSG(x...) printk( KERN_WARN MGA_PFX x )
 269 #define ERROR_MSG(x...) printk( KERN_ERR MGA_PFX x )
 270
 271 /*******************************************************************************
 272  * Prototypes
 273  *******************************************************************************
 274  */
 275
 276 void __sbus_init_pixclock( int model, unsigned long i2c_vbase );
 277 void __sbus_set_pixclock( int model, unsigned long i2c_vbase, uint32_t pixclock );
 278
 279 typedef struct {
 280         int div;        // [6:0] Linear output divider
 281
 282         int q;  // [7:0] PPL*_Q
 283         int p;  // [9:0] PPL*_P
 284         int po; // [0:0] PPL_PO
 285
 286         int pixclock;
 287 } sbus_clk_t;
 288
 289 sbus_clk_t __sbus_calc( int pixclock );
 290
 291 #endif  /* __MGAM83FB_H */