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drm/radeon/kms: set DMA mask properly on newer PCI asics
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / r100.c
blob574f2c7c6dd96c9ff0a9399bcb9add3bb7c08a48
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "r100d.h"
37 #include "rs100d.h"
38 #include "rv200d.h"
39 #include "rv250d.h"
40 #include "atom.h"
41
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
44
45 #include "r100_reg_safe.h"
46 #include "rn50_reg_safe.h"
47
48 /* Firmware Names */
49 #define FIRMWARE_R100 "radeon/R100_cp.bin"
50 #define FIRMWARE_R200 "radeon/R200_cp.bin"
51 #define FIRMWARE_R300 "radeon/R300_cp.bin"
52 #define FIRMWARE_R420 "radeon/R420_cp.bin"
53 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
54 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
55 #define FIRMWARE_R520 "radeon/R520_cp.bin"
56
57 MODULE_FIRMWARE(FIRMWARE_R100);
58 MODULE_FIRMWARE(FIRMWARE_R200);
59 MODULE_FIRMWARE(FIRMWARE_R300);
60 MODULE_FIRMWARE(FIRMWARE_R420);
61 MODULE_FIRMWARE(FIRMWARE_RS690);
62 MODULE_FIRMWARE(FIRMWARE_RS600);
63 MODULE_FIRMWARE(FIRMWARE_R520);
64
65 #include "r100_track.h"
66
67 /* This files gather functions specifics to:
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
69 */
70
71 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
72 {
73 /* enable the pflip int */
74 radeon_irq_kms_pflip_irq_get(rdev, crtc);
75 }
76
77 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
78 {
79 /* disable the pflip int */
80 radeon_irq_kms_pflip_irq_put(rdev, crtc);
81 }
82
83 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
84 {
85 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
86 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
87
88 /* Lock the graphics update lock */
89 /* update the scanout addresses */
90 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
91
92 /* Wait for update_pending to go high. */
93 while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));
94 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
95
96 /* Unlock the lock, so double-buffering can take place inside vblank */
97 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
98 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
99
100 /* Return current update_pending status: */
101 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
102 }
103
104 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
105 {
106 int i;
107 rdev->pm.dynpm_can_upclock = true;
108 rdev->pm.dynpm_can_downclock = true;
109
110 switch (rdev->pm.dynpm_planned_action) {
111 case DYNPM_ACTION_MINIMUM:
112 rdev->pm.requested_power_state_index = 0;
113 rdev->pm.dynpm_can_downclock = false;
114 break;
115 case DYNPM_ACTION_DOWNCLOCK:
116 if (rdev->pm.current_power_state_index == 0) {
117 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
118 rdev->pm.dynpm_can_downclock = false;
119 } else {
120 if (rdev->pm.active_crtc_count > 1) {
121 for (i = 0; i < rdev->pm.num_power_states; i++) {
122 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
123 continue;
124 else if (i >= rdev->pm.current_power_state_index) {
125 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
126 break;
127 } else {
128 rdev->pm.requested_power_state_index = i;
129 break;
130 }
131 }
132 } else
133 rdev->pm.requested_power_state_index =
134 rdev->pm.current_power_state_index - 1;
135 }
136 /* don't use the power state if crtcs are active and no display flag is set */
137 if ((rdev->pm.active_crtc_count > 0) &&
138 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
139 RADEON_PM_MODE_NO_DISPLAY)) {
140 rdev->pm.requested_power_state_index++;
141 }
142 break;
143 case DYNPM_ACTION_UPCLOCK:
144 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
145 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
146 rdev->pm.dynpm_can_upclock = false;
147 } else {
148 if (rdev->pm.active_crtc_count > 1) {
149 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
150 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
151 continue;
152 else if (i <= rdev->pm.current_power_state_index) {
153 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
154 break;
155 } else {
156 rdev->pm.requested_power_state_index = i;
157 break;
158 }
159 }
160 } else
161 rdev->pm.requested_power_state_index =
162 rdev->pm.current_power_state_index + 1;
163 }
164 break;
165 case DYNPM_ACTION_DEFAULT:
166 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
167 rdev->pm.dynpm_can_upclock = false;
168 break;
169 case DYNPM_ACTION_NONE:
170 default:
171 DRM_ERROR("Requested mode for not defined action\n");
172 return;
173 }
174 /* only one clock mode per power state */
175 rdev->pm.requested_clock_mode_index = 0;
176
177 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
178 rdev->pm.power_state[rdev->pm.requested_power_state_index].
179 clock_info[rdev->pm.requested_clock_mode_index].sclk,
180 rdev->pm.power_state[rdev->pm.requested_power_state_index].
181 clock_info[rdev->pm.requested_clock_mode_index].mclk,
182 rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 pcie_lanes);
184 }
185
186 void r100_pm_init_profile(struct radeon_device *rdev)
187 {
188 /* default */
189 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
190 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
191 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
192 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
193 /* low sh */
194 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
195 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
196 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
197 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
198 /* mid sh */
199 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
200 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
201 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
202 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
203 /* high sh */
204 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
205 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
206 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
207 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
208 /* low mh */
209 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
210 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
211 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
212 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
213 /* mid mh */
214 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
215 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
216 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
217 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
218 /* high mh */
219 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
220 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
221 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
222 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
223 }
224
225 void r100_pm_misc(struct radeon_device *rdev)
226 {
227 int requested_index = rdev->pm.requested_power_state_index;
228 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
229 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
230 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
231
232 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
233 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
234 tmp = RREG32(voltage->gpio.reg);
235 if (voltage->active_high)
236 tmp |= voltage->gpio.mask;
237 else
238 tmp &= ~(voltage->gpio.mask);
239 WREG32(voltage->gpio.reg, tmp);
240 if (voltage->delay)
241 udelay(voltage->delay);
242 } else {
243 tmp = RREG32(voltage->gpio.reg);
244 if (voltage->active_high)
245 tmp &= ~voltage->gpio.mask;
246 else
247 tmp |= voltage->gpio.mask;
248 WREG32(voltage->gpio.reg, tmp);
249 if (voltage->delay)
250 udelay(voltage->delay);
251 }
252 }
253
254 sclk_cntl = RREG32_PLL(SCLK_CNTL);
255 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
256 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
257 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
258 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
259 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
260 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
261 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
262 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
263 else
264 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
265 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
266 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
267 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
268 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
269 } else
270 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
271
272 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
273 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
274 if (voltage->delay) {
275 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
276 switch (voltage->delay) {
277 case 33:
278 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
279 break;
280 case 66:
281 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
282 break;
283 case 99:
284 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
285 break;
286 case 132:
287 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
288 break;
289 }
290 } else
291 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
292 } else
293 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
294
295 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
296 sclk_cntl &= ~FORCE_HDP;
297 else
298 sclk_cntl |= FORCE_HDP;
299
300 WREG32_PLL(SCLK_CNTL, sclk_cntl);
301 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
302 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
303
304 /* set pcie lanes */
305 if ((rdev->flags & RADEON_IS_PCIE) &&
306 !(rdev->flags & RADEON_IS_IGP) &&
307 rdev->asic->set_pcie_lanes &&
308 (ps->pcie_lanes !=
309 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
310 radeon_set_pcie_lanes(rdev,
311 ps->pcie_lanes);
312 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
313 }
314 }
315
316 void r100_pm_prepare(struct radeon_device *rdev)
317 {
318 struct drm_device *ddev = rdev->ddev;
319 struct drm_crtc *crtc;
320 struct radeon_crtc *radeon_crtc;
321 u32 tmp;
322
323 /* disable any active CRTCs */
324 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
325 radeon_crtc = to_radeon_crtc(crtc);
326 if (radeon_crtc->enabled) {
327 if (radeon_crtc->crtc_id) {
328 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
329 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
330 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
331 } else {
332 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
333 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
334 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
335 }
336 }
337 }
338 }
339
340 void r100_pm_finish(struct radeon_device *rdev)
341 {
342 struct drm_device *ddev = rdev->ddev;
343 struct drm_crtc *crtc;
344 struct radeon_crtc *radeon_crtc;
345 u32 tmp;
346
347 /* enable any active CRTCs */
348 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
349 radeon_crtc = to_radeon_crtc(crtc);
350 if (radeon_crtc->enabled) {
351 if (radeon_crtc->crtc_id) {
352 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
353 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
354 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
355 } else {
356 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
357 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
358 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
359 }
360 }
361 }
362 }
363
364 bool r100_gui_idle(struct radeon_device *rdev)
365 {
366 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
367 return false;
368 else
369 return true;
370 }
371
372 /* hpd for digital panel detect/disconnect */
373 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
374 {
375 bool connected = false;
376
377 switch (hpd) {
378 case RADEON_HPD_1:
379 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
380 connected = true;
381 break;
382 case RADEON_HPD_2:
383 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
384 connected = true;
385 break;
386 default:
387 break;
388 }
389 return connected;
390 }
391
392 void r100_hpd_set_polarity(struct radeon_device *rdev,
393 enum radeon_hpd_id hpd)
394 {
395 u32 tmp;
396 bool connected = r100_hpd_sense(rdev, hpd);
397
398 switch (hpd) {
399 case RADEON_HPD_1:
400 tmp = RREG32(RADEON_FP_GEN_CNTL);
401 if (connected)
402 tmp &= ~RADEON_FP_DETECT_INT_POL;
403 else
404 tmp |= RADEON_FP_DETECT_INT_POL;
405 WREG32(RADEON_FP_GEN_CNTL, tmp);
406 break;
407 case RADEON_HPD_2:
408 tmp = RREG32(RADEON_FP2_GEN_CNTL);
409 if (connected)
410 tmp &= ~RADEON_FP2_DETECT_INT_POL;
411 else
412 tmp |= RADEON_FP2_DETECT_INT_POL;
413 WREG32(RADEON_FP2_GEN_CNTL, tmp);
414 break;
415 default:
416 break;
417 }
418 }
419
420 void r100_hpd_init(struct radeon_device *rdev)
421 {
422 struct drm_device *dev = rdev->ddev;
423 struct drm_connector *connector;
424
425 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
426 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
427 switch (radeon_connector->hpd.hpd) {
428 case RADEON_HPD_1:
429 rdev->irq.hpd[0] = true;
430 break;
431 case RADEON_HPD_2:
432 rdev->irq.hpd[1] = true;
433 break;
434 default:
435 break;
436 }
437 }
438 if (rdev->irq.installed)
439 r100_irq_set(rdev);
440 }
441
442 void r100_hpd_fini(struct radeon_device *rdev)
443 {
444 struct drm_device *dev = rdev->ddev;
445 struct drm_connector *connector;
446
447 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
448 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
449 switch (radeon_connector->hpd.hpd) {
450 case RADEON_HPD_1:
451 rdev->irq.hpd[0] = false;
452 break;
453 case RADEON_HPD_2:
454 rdev->irq.hpd[1] = false;
455 break;
456 default:
457 break;
458 }
459 }
460 }
461
462 /*
463 * PCI GART
464 */
465 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
466 {
467 /* TODO: can we do somethings here ? */
468 /* It seems hw only cache one entry so we should discard this
469 * entry otherwise if first GPU GART read hit this entry it
470 * could end up in wrong address. */
471 }
472
473 int r100_pci_gart_init(struct radeon_device *rdev)
474 {
475 int r;
476
477 if (rdev->gart.table.ram.ptr) {
478 WARN(1, "R100 PCI GART already initialized\n");
479 return 0;
480 }
481 /* Initialize common gart structure */
482 r = radeon_gart_init(rdev);
483 if (r)
484 return r;
485 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
486 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
487 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
488 return radeon_gart_table_ram_alloc(rdev);
489 }
490
491 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
492 void r100_enable_bm(struct radeon_device *rdev)
493 {
494 uint32_t tmp;
495 /* Enable bus mastering */
496 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
497 WREG32(RADEON_BUS_CNTL, tmp);
498 }
499
500 int r100_pci_gart_enable(struct radeon_device *rdev)
501 {
502 uint32_t tmp;
503
504 radeon_gart_restore(rdev);
505 /* discard memory request outside of configured range */
506 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
507 WREG32(RADEON_AIC_CNTL, tmp);
508 /* set address range for PCI address translate */
509 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
510 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
511 /* set PCI GART page-table base address */
512 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
513 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
514 WREG32(RADEON_AIC_CNTL, tmp);
515 r100_pci_gart_tlb_flush(rdev);
516 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
517 (unsigned)(rdev->mc.gtt_size >> 20),
518 (unsigned long long)rdev->gart.table_addr);
519 rdev->gart.ready = true;
520 return 0;
521 }
522
523 void r100_pci_gart_disable(struct radeon_device *rdev)
524 {
525 uint32_t tmp;
526
527 /* discard memory request outside of configured range */
528 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
529 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
530 WREG32(RADEON_AIC_LO_ADDR, 0);
531 WREG32(RADEON_AIC_HI_ADDR, 0);
532 }
533
534 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
535 {
536 if (i < 0 || i > rdev->gart.num_gpu_pages) {
537 return -EINVAL;
538 }
539 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
540 return 0;
541 }
542
543 void r100_pci_gart_fini(struct radeon_device *rdev)
544 {
545 radeon_gart_fini(rdev);
546 r100_pci_gart_disable(rdev);
547 radeon_gart_table_ram_free(rdev);
548 }
549
550 int r100_irq_set(struct radeon_device *rdev)
551 {
552 uint32_t tmp = 0;
553
554 if (!rdev->irq.installed) {
555 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
556 WREG32(R_000040_GEN_INT_CNTL, 0);
557 return -EINVAL;
558 }
559 if (rdev->irq.sw_int) {
560 tmp |= RADEON_SW_INT_ENABLE;
561 }
562 if (rdev->irq.gui_idle) {
563 tmp |= RADEON_GUI_IDLE_MASK;
564 }
565 if (rdev->irq.crtc_vblank_int[0] ||
566 rdev->irq.pflip[0]) {
567 tmp |= RADEON_CRTC_VBLANK_MASK;
568 }
569 if (rdev->irq.crtc_vblank_int[1] ||
570 rdev->irq.pflip[1]) {
571 tmp |= RADEON_CRTC2_VBLANK_MASK;
572 }
573 if (rdev->irq.hpd[0]) {
574 tmp |= RADEON_FP_DETECT_MASK;
575 }
576 if (rdev->irq.hpd[1]) {
577 tmp |= RADEON_FP2_DETECT_MASK;
578 }
579 WREG32(RADEON_GEN_INT_CNTL, tmp);
580 return 0;
581 }
582
583 void r100_irq_disable(struct radeon_device *rdev)
584 {
585 u32 tmp;
586
587 WREG32(R_000040_GEN_INT_CNTL, 0);
588 /* Wait and acknowledge irq */
589 mdelay(1);
590 tmp = RREG32(R_000044_GEN_INT_STATUS);
591 WREG32(R_000044_GEN_INT_STATUS, tmp);
592 }
593
594 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
595 {
596 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
597 uint32_t irq_mask = RADEON_SW_INT_TEST |
598 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
599 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
600
601 /* the interrupt works, but the status bit is permanently asserted */
602 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
603 if (!rdev->irq.gui_idle_acked)
604 irq_mask |= RADEON_GUI_IDLE_STAT;
605 }
606
607 if (irqs) {
608 WREG32(RADEON_GEN_INT_STATUS, irqs);
609 }
610 return irqs & irq_mask;
611 }
612
613 int r100_irq_process(struct radeon_device *rdev)
614 {
615 uint32_t status, msi_rearm;
616 bool queue_hotplug = false;
617
618 /* reset gui idle ack. the status bit is broken */
619 rdev->irq.gui_idle_acked = false;
620
621 status = r100_irq_ack(rdev);
622 if (!status) {
623 return IRQ_NONE;
624 }
625 if (rdev->shutdown) {
626 return IRQ_NONE;
627 }
628 while (status) {
629 /* SW interrupt */
630 if (status & RADEON_SW_INT_TEST) {
631 radeon_fence_process(rdev);
632 }
633 /* gui idle interrupt */
634 if (status & RADEON_GUI_IDLE_STAT) {
635 rdev->irq.gui_idle_acked = true;
636 rdev->pm.gui_idle = true;
637 wake_up(&rdev->irq.idle_queue);
638 }
639 /* Vertical blank interrupts */
640 if (status & RADEON_CRTC_VBLANK_STAT) {
641 if (rdev->irq.crtc_vblank_int[0]) {
642 drm_handle_vblank(rdev->ddev, 0);
643 rdev->pm.vblank_sync = true;
644 wake_up(&rdev->irq.vblank_queue);
645 }
646 if (rdev->irq.pflip[0])
647 radeon_crtc_handle_flip(rdev, 0);
648 }
649 if (status & RADEON_CRTC2_VBLANK_STAT) {
650 if (rdev->irq.crtc_vblank_int[1]) {
651 drm_handle_vblank(rdev->ddev, 1);
652 rdev->pm.vblank_sync = true;
653 wake_up(&rdev->irq.vblank_queue);
654 }
655 if (rdev->irq.pflip[1])
656 radeon_crtc_handle_flip(rdev, 1);
657 }
658 if (status & RADEON_FP_DETECT_STAT) {
659 queue_hotplug = true;
660 DRM_DEBUG("HPD1\n");
661 }
662 if (status & RADEON_FP2_DETECT_STAT) {
663 queue_hotplug = true;
664 DRM_DEBUG("HPD2\n");
665 }
666 status = r100_irq_ack(rdev);
667 }
668 /* reset gui idle ack. the status bit is broken */
669 rdev->irq.gui_idle_acked = false;
670 if (queue_hotplug)
671 schedule_work(&rdev->hotplug_work);
672 if (rdev->msi_enabled) {
673 switch (rdev->family) {
674 case CHIP_RS400:
675 case CHIP_RS480:
676 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
677 WREG32(RADEON_AIC_CNTL, msi_rearm);
678 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
679 break;
680 default:
681 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
682 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
683 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
684 break;
685 }
686 }
687 return IRQ_HANDLED;
688 }
689
690 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
691 {
692 if (crtc == 0)
693 return RREG32(RADEON_CRTC_CRNT_FRAME);
694 else
695 return RREG32(RADEON_CRTC2_CRNT_FRAME);
696 }
697
698 /* Who ever call radeon_fence_emit should call ring_lock and ask
699 * for enough space (today caller are ib schedule and buffer move) */
700 void r100_fence_ring_emit(struct radeon_device *rdev,
701 struct radeon_fence *fence)
702 {
703 /* We have to make sure that caches are flushed before
704 * CPU might read something from VRAM. */
705 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
706 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
707 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
708 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
709 /* Wait until IDLE & CLEAN */
710 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
711 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
712 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
713 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
714 RADEON_HDP_READ_BUFFER_INVALIDATE);
715 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
716 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
717 /* Emit fence sequence & fire IRQ */
718 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
719 radeon_ring_write(rdev, fence->seq);
720 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
721 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
722 }
723
724 int r100_copy_blit(struct radeon_device *rdev,
725 uint64_t src_offset,
726 uint64_t dst_offset,
727 unsigned num_pages,
728 struct radeon_fence *fence)
729 {
730 uint32_t cur_pages;
731 uint32_t stride_bytes = PAGE_SIZE;
732 uint32_t pitch;
733 uint32_t stride_pixels;
734 unsigned ndw;
735 int num_loops;
736 int r = 0;
737
738 /* radeon limited to 16k stride */
739 stride_bytes &= 0x3fff;
740 /* radeon pitch is /64 */
741 pitch = stride_bytes / 64;
742 stride_pixels = stride_bytes / 4;
743 num_loops = DIV_ROUND_UP(num_pages, 8191);
744
745 /* Ask for enough room for blit + flush + fence */
746 ndw = 64 + (10 * num_loops);
747 r = radeon_ring_lock(rdev, ndw);
748 if (r) {
749 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
750 return -EINVAL;
751 }
752 while (num_pages > 0) {
753 cur_pages = num_pages;
754 if (cur_pages > 8191) {
755 cur_pages = 8191;
756 }
757 num_pages -= cur_pages;
758
759 /* pages are in Y direction - height
760 page width in X direction - width */
761 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
762 radeon_ring_write(rdev,
763 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
764 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
765 RADEON_GMC_SRC_CLIPPING |
766 RADEON_GMC_DST_CLIPPING |
767 RADEON_GMC_BRUSH_NONE |
768 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
769 RADEON_GMC_SRC_DATATYPE_COLOR |
770 RADEON_ROP3_S |
771 RADEON_DP_SRC_SOURCE_MEMORY |
772 RADEON_GMC_CLR_CMP_CNTL_DIS |
773 RADEON_GMC_WR_MSK_DIS);
774 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
775 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
776 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
777 radeon_ring_write(rdev, 0);
778 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
779 radeon_ring_write(rdev, num_pages);
780 radeon_ring_write(rdev, num_pages);
781 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
782 }
783 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
784 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
785 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
786 radeon_ring_write(rdev,
787 RADEON_WAIT_2D_IDLECLEAN |
788 RADEON_WAIT_HOST_IDLECLEAN |
789 RADEON_WAIT_DMA_GUI_IDLE);
790 if (fence) {
791 r = radeon_fence_emit(rdev, fence);
792 }
793 radeon_ring_unlock_commit(rdev);
794 return r;
795 }
796
797 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
798 {
799 unsigned i;
800 u32 tmp;
801
802 for (i = 0; i < rdev->usec_timeout; i++) {
803 tmp = RREG32(R_000E40_RBBM_STATUS);
804 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
805 return 0;
806 }
807 udelay(1);
808 }
809 return -1;
810 }
811
812 void r100_ring_start(struct radeon_device *rdev)
813 {
814 int r;
815
816 r = radeon_ring_lock(rdev, 2);
817 if (r) {
818 return;
819 }
820 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
821 radeon_ring_write(rdev,
822 RADEON_ISYNC_ANY2D_IDLE3D |
823 RADEON_ISYNC_ANY3D_IDLE2D |
824 RADEON_ISYNC_WAIT_IDLEGUI |
825 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
826 radeon_ring_unlock_commit(rdev);
827 }
828
829
830 /* Load the microcode for the CP */
831 static int r100_cp_init_microcode(struct radeon_device *rdev)
832 {
833 struct platform_device *pdev;
834 const char *fw_name = NULL;
835 int err;
836
837 DRM_DEBUG_KMS("\n");
838
839 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
840 err = IS_ERR(pdev);
841 if (err) {
842 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
843 return -EINVAL;
844 }
845 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
846 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
847 (rdev->family == CHIP_RS200)) {
848 DRM_INFO("Loading R100 Microcode\n");
849 fw_name = FIRMWARE_R100;
850 } else if ((rdev->family == CHIP_R200) ||
851 (rdev->family == CHIP_RV250) ||
852 (rdev->family == CHIP_RV280) ||
853 (rdev->family == CHIP_RS300)) {
854 DRM_INFO("Loading R200 Microcode\n");
855 fw_name = FIRMWARE_R200;
856 } else if ((rdev->family == CHIP_R300) ||
857 (rdev->family == CHIP_R350) ||
858 (rdev->family == CHIP_RV350) ||
859 (rdev->family == CHIP_RV380) ||
860 (rdev->family == CHIP_RS400) ||
861 (rdev->family == CHIP_RS480)) {
862 DRM_INFO("Loading R300 Microcode\n");
863 fw_name = FIRMWARE_R300;
864 } else if ((rdev->family == CHIP_R420) ||
865 (rdev->family == CHIP_R423) ||
866 (rdev->family == CHIP_RV410)) {
867 DRM_INFO("Loading R400 Microcode\n");
868 fw_name = FIRMWARE_R420;
869 } else if ((rdev->family == CHIP_RS690) ||
870 (rdev->family == CHIP_RS740)) {
871 DRM_INFO("Loading RS690/RS740 Microcode\n");
872 fw_name = FIRMWARE_RS690;
873 } else if (rdev->family == CHIP_RS600) {
874 DRM_INFO("Loading RS600 Microcode\n");
875 fw_name = FIRMWARE_RS600;
876 } else if ((rdev->family == CHIP_RV515) ||
877 (rdev->family == CHIP_R520) ||
878 (rdev->family == CHIP_RV530) ||
879 (rdev->family == CHIP_R580) ||
880 (rdev->family == CHIP_RV560) ||
881 (rdev->family == CHIP_RV570)) {
882 DRM_INFO("Loading R500 Microcode\n");
883 fw_name = FIRMWARE_R520;
884 }
885
886 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
887 platform_device_unregister(pdev);
888 if (err) {
889 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
890 fw_name);
891 } else if (rdev->me_fw->size % 8) {
892 printk(KERN_ERR
893 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
894 rdev->me_fw->size, fw_name);
895 err = -EINVAL;
896 release_firmware(rdev->me_fw);
897 rdev->me_fw = NULL;
898 }
899 return err;
900 }
901
902 static void r100_cp_load_microcode(struct radeon_device *rdev)
903 {
904 const __be32 *fw_data;
905 int i, size;
906
907 if (r100_gui_wait_for_idle(rdev)) {
908 printk(KERN_WARNING "Failed to wait GUI idle while "
909 "programming pipes. Bad things might happen.\n");
910 }
911
912 if (rdev->me_fw) {
913 size = rdev->me_fw->size / 4;
914 fw_data = (const __be32 *)&rdev->me_fw->data[0];
915 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
916 for (i = 0; i < size; i += 2) {
917 WREG32(RADEON_CP_ME_RAM_DATAH,
918 be32_to_cpup(&fw_data[i]));
919 WREG32(RADEON_CP_ME_RAM_DATAL,
920 be32_to_cpup(&fw_data[i + 1]));
921 }
922 }
923 }
924
925 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
926 {
927 unsigned rb_bufsz;
928 unsigned rb_blksz;
929 unsigned max_fetch;
930 unsigned pre_write_timer;
931 unsigned pre_write_limit;
932 unsigned indirect2_start;
933 unsigned indirect1_start;
934 uint32_t tmp;
935 int r;
936
937 if (r100_debugfs_cp_init(rdev)) {
938 DRM_ERROR("Failed to register debugfs file for CP !\n");
939 }
940 if (!rdev->me_fw) {
941 r = r100_cp_init_microcode(rdev);
942 if (r) {
943 DRM_ERROR("Failed to load firmware!\n");
944 return r;
945 }
946 }
947
948 /* Align ring size */
949 rb_bufsz = drm_order(ring_size / 8);
950 ring_size = (1 << (rb_bufsz + 1)) * 4;
951 r100_cp_load_microcode(rdev);
952 r = radeon_ring_init(rdev, ring_size);
953 if (r) {
954 return r;
955 }
956 /* Each time the cp read 1024 bytes (16 dword/quadword) update
957 * the rptr copy in system ram */
958 rb_blksz = 9;
959 /* cp will read 128bytes at a time (4 dwords) */
960 max_fetch = 1;
961 rdev->cp.align_mask = 16 - 1;
962 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
963 pre_write_timer = 64;
964 /* Force CP_RB_WPTR write if written more than one time before the
965 * delay expire
966 */
967 pre_write_limit = 0;
968 /* Setup the cp cache like this (cache size is 96 dwords) :
969 * RING 0 to 15
970 * INDIRECT1 16 to 79
971 * INDIRECT2 80 to 95
972 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
973 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
974 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
975 * Idea being that most of the gpu cmd will be through indirect1 buffer
976 * so it gets the bigger cache.
977 */
978 indirect2_start = 80;
979 indirect1_start = 16;
980 /* cp setup */
981 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
982 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
983 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
984 REG_SET(RADEON_MAX_FETCH, max_fetch));
985 #ifdef __BIG_ENDIAN
986 tmp |= RADEON_BUF_SWAP_32BIT;
987 #endif
988 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
989
990 /* Set ring address */
991 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
992 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
993 /* Force read & write ptr to 0 */
994 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
995 WREG32(RADEON_CP_RB_RPTR_WR, 0);
996 WREG32(RADEON_CP_RB_WPTR, 0);
997
998 /* set the wb address whether it's enabled or not */
999 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1000 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1001 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1002
1003 if (rdev->wb.enabled)
1004 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1005 else {
1006 tmp |= RADEON_RB_NO_UPDATE;
1007 WREG32(R_000770_SCRATCH_UMSK, 0);
1008 }
1009
1010 WREG32(RADEON_CP_RB_CNTL, tmp);
1011 udelay(10);
1012 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1013 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
1014 /* protect against crazy HW on resume */
1015 rdev->cp.wptr &= rdev->cp.ptr_mask;
1016 /* Set cp mode to bus mastering & enable cp*/
1017 WREG32(RADEON_CP_CSQ_MODE,
1018 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1019 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1020 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1021 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1022 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1023 radeon_ring_start(rdev);
1024 r = radeon_ring_test(rdev);
1025 if (r) {
1026 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1027 return r;
1028 }
1029 rdev->cp.ready = true;
1030 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1031 return 0;
1032 }
1033
1034 void r100_cp_fini(struct radeon_device *rdev)
1035 {
1036 if (r100_cp_wait_for_idle(rdev)) {
1037 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1038 }
1039 /* Disable ring */
1040 r100_cp_disable(rdev);
1041 radeon_ring_fini(rdev);
1042 DRM_INFO("radeon: cp finalized\n");
1043 }
1044
1045 void r100_cp_disable(struct radeon_device *rdev)
1046 {
1047 /* Disable ring */
1048 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1049 rdev->cp.ready = false;
1050 WREG32(RADEON_CP_CSQ_MODE, 0);
1051 WREG32(RADEON_CP_CSQ_CNTL, 0);
1052 WREG32(R_000770_SCRATCH_UMSK, 0);
1053 if (r100_gui_wait_for_idle(rdev)) {
1054 printk(KERN_WARNING "Failed to wait GUI idle while "
1055 "programming pipes. Bad things might happen.\n");
1056 }
1057 }
1058
1059 void r100_cp_commit(struct radeon_device *rdev)
1060 {
1061 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1062 (void)RREG32(RADEON_CP_RB_WPTR);
1063 }
1064
1065
1066 /*
1067 * CS functions
1068 */
1069 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1070 struct radeon_cs_packet *pkt,
1071 const unsigned *auth, unsigned n,
1072 radeon_packet0_check_t check)
1073 {
1074 unsigned reg;
1075 unsigned i, j, m;
1076 unsigned idx;
1077 int r;
1078
1079 idx = pkt->idx + 1;
1080 reg = pkt->reg;
1081 /* Check that register fall into register range
1082 * determined by the number of entry (n) in the
1083 * safe register bitmap.
1084 */
1085 if (pkt->one_reg_wr) {
1086 if ((reg >> 7) > n) {
1087 return -EINVAL;
1088 }
1089 } else {
1090 if (((reg + (pkt->count << 2)) >> 7) > n) {
1091 return -EINVAL;
1092 }
1093 }
1094 for (i = 0; i <= pkt->count; i++, idx++) {
1095 j = (reg >> 7);
1096 m = 1 << ((reg >> 2) & 31);
1097 if (auth[j] & m) {
1098 r = check(p, pkt, idx, reg);
1099 if (r) {
1100 return r;
1101 }
1102 }
1103 if (pkt->one_reg_wr) {
1104 if (!(auth[j] & m)) {
1105 break;
1106 }
1107 } else {
1108 reg += 4;
1109 }
1110 }
1111 return 0;
1112 }
1113
1114 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1115 struct radeon_cs_packet *pkt)
1116 {
1117 volatile uint32_t *ib;
1118 unsigned i;
1119 unsigned idx;
1120
1121 ib = p->ib->ptr;
1122 idx = pkt->idx;
1123 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1124 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1125 }
1126 }
1127
1128 /**
1129 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1130 * @parser: parser structure holding parsing context.
1131 * @pkt: where to store packet informations
1132 *
1133 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1134 * if packet is bigger than remaining ib size. or if packets is unknown.
1135 **/
1136 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1137 struct radeon_cs_packet *pkt,
1138 unsigned idx)
1139 {
1140 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1141 uint32_t header;
1142
1143 if (idx >= ib_chunk->length_dw) {
1144 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1145 idx, ib_chunk->length_dw);
1146 return -EINVAL;
1147 }
1148 header = radeon_get_ib_value(p, idx);
1149 pkt->idx = idx;
1150 pkt->type = CP_PACKET_GET_TYPE(header);
1151 pkt->count = CP_PACKET_GET_COUNT(header);
1152 switch (pkt->type) {
1153 case PACKET_TYPE0:
1154 pkt->reg = CP_PACKET0_GET_REG(header);
1155 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1156 break;
1157 case PACKET_TYPE3:
1158 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1159 break;
1160 case PACKET_TYPE2:
1161 pkt->count = -1;
1162 break;
1163 default:
1164 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1165 return -EINVAL;
1166 }
1167 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1168 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1169 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1170 return -EINVAL;
1171 }
1172 return 0;
1173 }
1174
1175 /**
1176 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1177 * @parser: parser structure holding parsing context.
1178 *
1179 * Userspace sends a special sequence for VLINE waits.
1180 * PACKET0 - VLINE_START_END + value
1181 * PACKET0 - WAIT_UNTIL +_value
1182 * RELOC (P3) - crtc_id in reloc.
1183 *
1184 * This function parses this and relocates the VLINE START END
1185 * and WAIT UNTIL packets to the correct crtc.
1186 * It also detects a switched off crtc and nulls out the
1187 * wait in that case.
1188 */
1189 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1190 {
1191 struct drm_mode_object *obj;
1192 struct drm_crtc *crtc;
1193 struct radeon_crtc *radeon_crtc;
1194 struct radeon_cs_packet p3reloc, waitreloc;
1195 int crtc_id;
1196 int r;
1197 uint32_t header, h_idx, reg;
1198 volatile uint32_t *ib;
1199
1200 ib = p->ib->ptr;
1201
1202 /* parse the wait until */
1203 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1204 if (r)
1205 return r;
1206
1207 /* check its a wait until and only 1 count */
1208 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1209 waitreloc.count != 0) {
1210 DRM_ERROR("vline wait had illegal wait until segment\n");
1211 return -EINVAL;
1212 }
1213
1214 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1215 DRM_ERROR("vline wait had illegal wait until\n");
1216 return -EINVAL;
1217 }
1218
1219 /* jump over the NOP */
1220 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1221 if (r)
1222 return r;
1223
1224 h_idx = p->idx - 2;
1225 p->idx += waitreloc.count + 2;
1226 p->idx += p3reloc.count + 2;
1227
1228 header = radeon_get_ib_value(p, h_idx);
1229 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1230 reg = CP_PACKET0_GET_REG(header);
1231 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1232 if (!obj) {
1233 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1234 return -EINVAL;
1235 }
1236 crtc = obj_to_crtc(obj);
1237 radeon_crtc = to_radeon_crtc(crtc);
1238 crtc_id = radeon_crtc->crtc_id;
1239
1240 if (!crtc->enabled) {
1241 /* if the CRTC isn't enabled - we need to nop out the wait until */
1242 ib[h_idx + 2] = PACKET2(0);
1243 ib[h_idx + 3] = PACKET2(0);
1244 } else if (crtc_id == 1) {
1245 switch (reg) {
1246 case AVIVO_D1MODE_VLINE_START_END:
1247 header &= ~R300_CP_PACKET0_REG_MASK;
1248 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1249 break;
1250 case RADEON_CRTC_GUI_TRIG_VLINE:
1251 header &= ~R300_CP_PACKET0_REG_MASK;
1252 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1253 break;
1254 default:
1255 DRM_ERROR("unknown crtc reloc\n");
1256 return -EINVAL;
1257 }
1258 ib[h_idx] = header;
1259 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1260 }
1261
1262 return 0;
1263 }
1264
1265 /**
1266 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1267 * @parser: parser structure holding parsing context.
1268 * @data: pointer to relocation data
1269 * @offset_start: starting offset
1270 * @offset_mask: offset mask (to align start offset on)
1271 * @reloc: reloc informations
1272 *
1273 * Check next packet is relocation packet3, do bo validation and compute
1274 * GPU offset using the provided start.
1275 **/
1276 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1277 struct radeon_cs_reloc **cs_reloc)
1278 {
1279 struct radeon_cs_chunk *relocs_chunk;
1280 struct radeon_cs_packet p3reloc;
1281 unsigned idx;
1282 int r;
1283
1284 if (p->chunk_relocs_idx == -1) {
1285 DRM_ERROR("No relocation chunk !\n");
1286 return -EINVAL;
1287 }
1288 *cs_reloc = NULL;
1289 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1290 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1291 if (r) {
1292 return r;
1293 }
1294 p->idx += p3reloc.count + 2;
1295 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1296 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1297 p3reloc.idx);
1298 r100_cs_dump_packet(p, &p3reloc);
1299 return -EINVAL;
1300 }
1301 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1302 if (idx >= relocs_chunk->length_dw) {
1303 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1304 idx, relocs_chunk->length_dw);
1305 r100_cs_dump_packet(p, &p3reloc);
1306 return -EINVAL;
1307 }
1308 /* FIXME: we assume reloc size is 4 dwords */
1309 *cs_reloc = p->relocs_ptr[(idx / 4)];
1310 return 0;
1311 }
1312
1313 static int r100_get_vtx_size(uint32_t vtx_fmt)
1314 {
1315 int vtx_size;
1316 vtx_size = 2;
1317 /* ordered according to bits in spec */
1318 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1319 vtx_size++;
1320 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1321 vtx_size += 3;
1322 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1323 vtx_size++;
1324 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1325 vtx_size++;
1326 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1327 vtx_size += 3;
1328 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1329 vtx_size++;
1330 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1331 vtx_size++;
1332 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1333 vtx_size += 2;
1334 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1335 vtx_size += 2;
1336 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1337 vtx_size++;
1338 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1339 vtx_size += 2;
1340 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1341 vtx_size++;
1342 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1343 vtx_size += 2;
1344 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1345 vtx_size++;
1346 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1347 vtx_size++;
1348 /* blend weight */
1349 if (vtx_fmt & (0x7 << 15))
1350 vtx_size += (vtx_fmt >> 15) & 0x7;
1351 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1352 vtx_size += 3;
1353 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1354 vtx_size += 2;
1355 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1356 vtx_size++;
1357 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1358 vtx_size++;
1359 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1360 vtx_size++;
1361 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1362 vtx_size++;
1363 return vtx_size;
1364 }
1365
1366 static int r100_packet0_check(struct radeon_cs_parser *p,
1367 struct radeon_cs_packet *pkt,
1368 unsigned idx, unsigned reg)
1369 {
1370 struct radeon_cs_reloc *reloc;
1371 struct r100_cs_track *track;
1372 volatile uint32_t *ib;
1373 uint32_t tmp;
1374 int r;
1375 int i, face;
1376 u32 tile_flags = 0;
1377 u32 idx_value;
1378
1379 ib = p->ib->ptr;
1380 track = (struct r100_cs_track *)p->track;
1381
1382 idx_value = radeon_get_ib_value(p, idx);
1383
1384 switch (reg) {
1385 case RADEON_CRTC_GUI_TRIG_VLINE:
1386 r = r100_cs_packet_parse_vline(p);
1387 if (r) {
1388 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1389 idx, reg);
1390 r100_cs_dump_packet(p, pkt);
1391 return r;
1392 }
1393 break;
1394 /* FIXME: only allow PACKET3 blit? easier to check for out of
1395 * range access */
1396 case RADEON_DST_PITCH_OFFSET:
1397 case RADEON_SRC_PITCH_OFFSET:
1398 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1399 if (r)
1400 return r;
1401 break;
1402 case RADEON_RB3D_DEPTHOFFSET:
1403 r = r100_cs_packet_next_reloc(p, &reloc);
1404 if (r) {
1405 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1406 idx, reg);
1407 r100_cs_dump_packet(p, pkt);
1408 return r;
1409 }
1410 track->zb.robj = reloc->robj;
1411 track->zb.offset = idx_value;
1412 track->zb_dirty = true;
1413 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1414 break;
1415 case RADEON_RB3D_COLOROFFSET:
1416 r = r100_cs_packet_next_reloc(p, &reloc);
1417 if (r) {
1418 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1419 idx, reg);
1420 r100_cs_dump_packet(p, pkt);
1421 return r;
1422 }
1423 track->cb[0].robj = reloc->robj;
1424 track->cb[0].offset = idx_value;
1425 track->cb_dirty = true;
1426 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1427 break;
1428 case RADEON_PP_TXOFFSET_0:
1429 case RADEON_PP_TXOFFSET_1:
1430 case RADEON_PP_TXOFFSET_2:
1431 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1432 r = r100_cs_packet_next_reloc(p, &reloc);
1433 if (r) {
1434 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1435 idx, reg);
1436 r100_cs_dump_packet(p, pkt);
1437 return r;
1438 }
1439 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1440 track->textures[i].robj = reloc->robj;
1441 track->tex_dirty = true;
1442 break;
1443 case RADEON_PP_CUBIC_OFFSET_T0_0:
1444 case RADEON_PP_CUBIC_OFFSET_T0_1:
1445 case RADEON_PP_CUBIC_OFFSET_T0_2:
1446 case RADEON_PP_CUBIC_OFFSET_T0_3:
1447 case RADEON_PP_CUBIC_OFFSET_T0_4:
1448 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1449 r = r100_cs_packet_next_reloc(p, &reloc);
1450 if (r) {
1451 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1452 idx, reg);
1453 r100_cs_dump_packet(p, pkt);
1454 return r;
1455 }
1456 track->textures[0].cube_info[i].offset = idx_value;
1457 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1458 track->textures[0].cube_info[i].robj = reloc->robj;
1459 track->tex_dirty = true;
1460 break;
1461 case RADEON_PP_CUBIC_OFFSET_T1_0:
1462 case RADEON_PP_CUBIC_OFFSET_T1_1:
1463 case RADEON_PP_CUBIC_OFFSET_T1_2:
1464 case RADEON_PP_CUBIC_OFFSET_T1_3:
1465 case RADEON_PP_CUBIC_OFFSET_T1_4:
1466 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1467 r = r100_cs_packet_next_reloc(p, &reloc);
1468 if (r) {
1469 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1470 idx, reg);
1471 r100_cs_dump_packet(p, pkt);
1472 return r;
1473 }
1474 track->textures[1].cube_info[i].offset = idx_value;
1475 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1476 track->textures[1].cube_info[i].robj = reloc->robj;
1477 track->tex_dirty = true;
1478 break;
1479 case RADEON_PP_CUBIC_OFFSET_T2_0:
1480 case RADEON_PP_CUBIC_OFFSET_T2_1:
1481 case RADEON_PP_CUBIC_OFFSET_T2_2:
1482 case RADEON_PP_CUBIC_OFFSET_T2_3:
1483 case RADEON_PP_CUBIC_OFFSET_T2_4:
1484 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1485 r = r100_cs_packet_next_reloc(p, &reloc);
1486 if (r) {
1487 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1488 idx, reg);
1489 r100_cs_dump_packet(p, pkt);
1490 return r;
1491 }
1492 track->textures[2].cube_info[i].offset = idx_value;
1493 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1494 track->textures[2].cube_info[i].robj = reloc->robj;
1495 track->tex_dirty = true;
1496 break;
1497 case RADEON_RE_WIDTH_HEIGHT:
1498 track->maxy = ((idx_value >> 16) & 0x7FF);
1499 track->cb_dirty = true;
1500 track->zb_dirty = true;
1501 break;
1502 case RADEON_RB3D_COLORPITCH:
1503 r = r100_cs_packet_next_reloc(p, &reloc);
1504 if (r) {
1505 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1506 idx, reg);
1507 r100_cs_dump_packet(p, pkt);
1508 return r;
1509 }
1510
1511 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1512 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1513 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1514 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1515
1516 tmp = idx_value & ~(0x7 << 16);
1517 tmp |= tile_flags;
1518 ib[idx] = tmp;
1519
1520 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1521 track->cb_dirty = true;
1522 break;
1523 case RADEON_RB3D_DEPTHPITCH:
1524 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1525 track->zb_dirty = true;
1526 break;
1527 case RADEON_RB3D_CNTL:
1528 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1529 case 7:
1530 case 8:
1531 case 9:
1532 case 11:
1533 case 12:
1534 track->cb[0].cpp = 1;
1535 break;
1536 case 3:
1537 case 4:
1538 case 15:
1539 track->cb[0].cpp = 2;
1540 break;
1541 case 6:
1542 track->cb[0].cpp = 4;
1543 break;
1544 default:
1545 DRM_ERROR("Invalid color buffer format (%d) !\n",
1546 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1547 return -EINVAL;
1548 }
1549 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1550 track->cb_dirty = true;
1551 track->zb_dirty = true;
1552 break;
1553 case RADEON_RB3D_ZSTENCILCNTL:
1554 switch (idx_value & 0xf) {
1555 case 0:
1556 track->zb.cpp = 2;
1557 break;
1558 case 2:
1559 case 3:
1560 case 4:
1561 case 5:
1562 case 9:
1563 case 11:
1564 track->zb.cpp = 4;
1565 break;
1566 default:
1567 break;
1568 }
1569 track->zb_dirty = true;
1570 break;
1571 case RADEON_RB3D_ZPASS_ADDR:
1572 r = r100_cs_packet_next_reloc(p, &reloc);
1573 if (r) {
1574 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1575 idx, reg);
1576 r100_cs_dump_packet(p, pkt);
1577 return r;
1578 }
1579 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1580 break;
1581 case RADEON_PP_CNTL:
1582 {
1583 uint32_t temp = idx_value >> 4;
1584 for (i = 0; i < track->num_texture; i++)
1585 track->textures[i].enabled = !!(temp & (1 << i));
1586 track->tex_dirty = true;
1587 }
1588 break;
1589 case RADEON_SE_VF_CNTL:
1590 track->vap_vf_cntl = idx_value;
1591 break;
1592 case RADEON_SE_VTX_FMT:
1593 track->vtx_size = r100_get_vtx_size(idx_value);
1594 break;
1595 case RADEON_PP_TEX_SIZE_0:
1596 case RADEON_PP_TEX_SIZE_1:
1597 case RADEON_PP_TEX_SIZE_2:
1598 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1599 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1600 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1601 track->tex_dirty = true;
1602 break;
1603 case RADEON_PP_TEX_PITCH_0:
1604 case RADEON_PP_TEX_PITCH_1:
1605 case RADEON_PP_TEX_PITCH_2:
1606 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1607 track->textures[i].pitch = idx_value + 32;
1608 track->tex_dirty = true;
1609 break;
1610 case RADEON_PP_TXFILTER_0:
1611 case RADEON_PP_TXFILTER_1:
1612 case RADEON_PP_TXFILTER_2:
1613 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1614 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1615 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1616 tmp = (idx_value >> 23) & 0x7;
1617 if (tmp == 2 || tmp == 6)
1618 track->textures[i].roundup_w = false;
1619 tmp = (idx_value >> 27) & 0x7;
1620 if (tmp == 2 || tmp == 6)
1621 track->textures[i].roundup_h = false;
1622 track->tex_dirty = true;
1623 break;
1624 case RADEON_PP_TXFORMAT_0:
1625 case RADEON_PP_TXFORMAT_1:
1626 case RADEON_PP_TXFORMAT_2:
1627 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1628 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1629 track->textures[i].use_pitch = 1;
1630 } else {
1631 track->textures[i].use_pitch = 0;
1632 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1633 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1634 }
1635 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1636 track->textures[i].tex_coord_type = 2;
1637 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1638 case RADEON_TXFORMAT_I8:
1639 case RADEON_TXFORMAT_RGB332:
1640 case RADEON_TXFORMAT_Y8:
1641 track->textures[i].cpp = 1;
1642 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1643 break;
1644 case RADEON_TXFORMAT_AI88:
1645 case RADEON_TXFORMAT_ARGB1555:
1646 case RADEON_TXFORMAT_RGB565:
1647 case RADEON_TXFORMAT_ARGB4444:
1648 case RADEON_TXFORMAT_VYUY422:
1649 case RADEON_TXFORMAT_YVYU422:
1650 case RADEON_TXFORMAT_SHADOW16:
1651 case RADEON_TXFORMAT_LDUDV655:
1652 case RADEON_TXFORMAT_DUDV88:
1653 track->textures[i].cpp = 2;
1654 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1655 break;
1656 case RADEON_TXFORMAT_ARGB8888:
1657 case RADEON_TXFORMAT_RGBA8888:
1658 case RADEON_TXFORMAT_SHADOW32:
1659 case RADEON_TXFORMAT_LDUDUV8888:
1660 track->textures[i].cpp = 4;
1661 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1662 break;
1663 case RADEON_TXFORMAT_DXT1:
1664 track->textures[i].cpp = 1;
1665 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1666 break;
1667 case RADEON_TXFORMAT_DXT23:
1668 case RADEON_TXFORMAT_DXT45:
1669 track->textures[i].cpp = 1;
1670 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1671 break;
1672 }
1673 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1674 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1675 track->tex_dirty = true;
1676 break;
1677 case RADEON_PP_CUBIC_FACES_0:
1678 case RADEON_PP_CUBIC_FACES_1:
1679 case RADEON_PP_CUBIC_FACES_2:
1680 tmp = idx_value;
1681 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1682 for (face = 0; face < 4; face++) {
1683 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1684 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1685 }
1686 track->tex_dirty = true;
1687 break;
1688 default:
1689 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1690 reg, idx);
1691 return -EINVAL;
1692 }
1693 return 0;
1694 }
1695
1696 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1697 struct radeon_cs_packet *pkt,
1698 struct radeon_bo *robj)
1699 {
1700 unsigned idx;
1701 u32 value;
1702 idx = pkt->idx + 1;
1703 value = radeon_get_ib_value(p, idx + 2);
1704 if ((value + 1) > radeon_bo_size(robj)) {
1705 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1706 "(need %u have %lu) !\n",
1707 value + 1,
1708 radeon_bo_size(robj));
1709 return -EINVAL;
1710 }
1711 return 0;
1712 }
1713
1714 static int r100_packet3_check(struct radeon_cs_parser *p,
1715 struct radeon_cs_packet *pkt)
1716 {
1717 struct radeon_cs_reloc *reloc;
1718 struct r100_cs_track *track;
1719 unsigned idx;
1720 volatile uint32_t *ib;
1721 int r;
1722
1723 ib = p->ib->ptr;
1724 idx = pkt->idx + 1;
1725 track = (struct r100_cs_track *)p->track;
1726 switch (pkt->opcode) {
1727 case PACKET3_3D_LOAD_VBPNTR:
1728 r = r100_packet3_load_vbpntr(p, pkt, idx);
1729 if (r)
1730 return r;
1731 break;
1732 case PACKET3_INDX_BUFFER:
1733 r = r100_cs_packet_next_reloc(p, &reloc);
1734 if (r) {
1735 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1736 r100_cs_dump_packet(p, pkt);
1737 return r;
1738 }
1739 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1740 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1741 if (r) {
1742 return r;
1743 }
1744 break;
1745 case 0x23:
1746 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1747 r = r100_cs_packet_next_reloc(p, &reloc);
1748 if (r) {
1749 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1750 r100_cs_dump_packet(p, pkt);
1751 return r;
1752 }
1753 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1754 track->num_arrays = 1;
1755 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1756
1757 track->arrays[0].robj = reloc->robj;
1758 track->arrays[0].esize = track->vtx_size;
1759
1760 track->max_indx = radeon_get_ib_value(p, idx+1);
1761
1762 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1763 track->immd_dwords = pkt->count - 1;
1764 r = r100_cs_track_check(p->rdev, track);
1765 if (r)
1766 return r;
1767 break;
1768 case PACKET3_3D_DRAW_IMMD:
1769 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1770 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1771 return -EINVAL;
1772 }
1773 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1774 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1775 track->immd_dwords = pkt->count - 1;
1776 r = r100_cs_track_check(p->rdev, track);
1777 if (r)
1778 return r;
1779 break;
1780 /* triggers drawing using in-packet vertex data */
1781 case PACKET3_3D_DRAW_IMMD_2:
1782 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1783 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1784 return -EINVAL;
1785 }
1786 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1787 track->immd_dwords = pkt->count;
1788 r = r100_cs_track_check(p->rdev, track);
1789 if (r)
1790 return r;
1791 break;
1792 /* triggers drawing using in-packet vertex data */
1793 case PACKET3_3D_DRAW_VBUF_2:
1794 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1795 r = r100_cs_track_check(p->rdev, track);
1796 if (r)
1797 return r;
1798 break;
1799 /* triggers drawing of vertex buffers setup elsewhere */
1800 case PACKET3_3D_DRAW_INDX_2:
1801 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1802 r = r100_cs_track_check(p->rdev, track);
1803 if (r)
1804 return r;
1805 break;
1806 /* triggers drawing using indices to vertex buffer */
1807 case PACKET3_3D_DRAW_VBUF:
1808 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1809 r = r100_cs_track_check(p->rdev, track);
1810 if (r)
1811 return r;
1812 break;
1813 /* triggers drawing of vertex buffers setup elsewhere */
1814 case PACKET3_3D_DRAW_INDX:
1815 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1816 r = r100_cs_track_check(p->rdev, track);
1817 if (r)
1818 return r;
1819 break;
1820 /* triggers drawing using indices to vertex buffer */
1821 case PACKET3_3D_CLEAR_HIZ:
1822 case PACKET3_3D_CLEAR_ZMASK:
1823 if (p->rdev->hyperz_filp != p->filp)
1824 return -EINVAL;
1825 break;
1826 case PACKET3_NOP:
1827 break;
1828 default:
1829 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1830 return -EINVAL;
1831 }
1832 return 0;
1833 }
1834
1835 int r100_cs_parse(struct radeon_cs_parser *p)
1836 {
1837 struct radeon_cs_packet pkt;
1838 struct r100_cs_track *track;
1839 int r;
1840
1841 track = kzalloc(sizeof(*track), GFP_KERNEL);
1842 r100_cs_track_clear(p->rdev, track);
1843 p->track = track;
1844 do {
1845 r = r100_cs_packet_parse(p, &pkt, p->idx);
1846 if (r) {
1847 return r;
1848 }
1849 p->idx += pkt.count + 2;
1850 switch (pkt.type) {
1851 case PACKET_TYPE0:
1852 if (p->rdev->family >= CHIP_R200)
1853 r = r100_cs_parse_packet0(p, &pkt,
1854 p->rdev->config.r100.reg_safe_bm,
1855 p->rdev->config.r100.reg_safe_bm_size,
1856 &r200_packet0_check);
1857 else
1858 r = r100_cs_parse_packet0(p, &pkt,
1859 p->rdev->config.r100.reg_safe_bm,
1860 p->rdev->config.r100.reg_safe_bm_size,
1861 &r100_packet0_check);
1862 break;
1863 case PACKET_TYPE2:
1864 break;
1865 case PACKET_TYPE3:
1866 r = r100_packet3_check(p, &pkt);
1867 break;
1868 default:
1869 DRM_ERROR("Unknown packet type %d !\n",
1870 pkt.type);
1871 return -EINVAL;
1872 }
1873 if (r) {
1874 return r;
1875 }
1876 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1877 return 0;
1878 }
1879
1880
1881 /*
1882 * Global GPU functions
1883 */
1884 void r100_errata(struct radeon_device *rdev)
1885 {
1886 rdev->pll_errata = 0;
1887
1888 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1889 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1890 }
1891
1892 if (rdev->family == CHIP_RV100 ||
1893 rdev->family == CHIP_RS100 ||
1894 rdev->family == CHIP_RS200) {
1895 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1896 }
1897 }
1898
1899 /* Wait for vertical sync on primary CRTC */
1900 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1901 {
1902 uint32_t crtc_gen_cntl, tmp;
1903 int i;
1904
1905 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1906 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1907 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1908 return;
1909 }
1910 /* Clear the CRTC_VBLANK_SAVE bit */
1911 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1912 for (i = 0; i < rdev->usec_timeout; i++) {
1913 tmp = RREG32(RADEON_CRTC_STATUS);
1914 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1915 return;
1916 }
1917 DRM_UDELAY(1);
1918 }
1919 }
1920
1921 /* Wait for vertical sync on secondary CRTC */
1922 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1923 {
1924 uint32_t crtc2_gen_cntl, tmp;
1925 int i;
1926
1927 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1928 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1929 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1930 return;
1931
1932 /* Clear the CRTC_VBLANK_SAVE bit */
1933 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1934 for (i = 0; i < rdev->usec_timeout; i++) {
1935 tmp = RREG32(RADEON_CRTC2_STATUS);
1936 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1937 return;
1938 }
1939 DRM_UDELAY(1);
1940 }
1941 }
1942
1943 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1944 {
1945 unsigned i;
1946 uint32_t tmp;
1947
1948 for (i = 0; i < rdev->usec_timeout; i++) {
1949 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1950 if (tmp >= n) {
1951 return 0;
1952 }
1953 DRM_UDELAY(1);
1954 }
1955 return -1;
1956 }
1957
1958 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1959 {
1960 unsigned i;
1961 uint32_t tmp;
1962
1963 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1964 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1965 " Bad things might happen.\n");
1966 }
1967 for (i = 0; i < rdev->usec_timeout; i++) {
1968 tmp = RREG32(RADEON_RBBM_STATUS);
1969 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1970 return 0;
1971 }
1972 DRM_UDELAY(1);
1973 }
1974 return -1;
1975 }
1976
1977 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1978 {
1979 unsigned i;
1980 uint32_t tmp;
1981
1982 for (i = 0; i < rdev->usec_timeout; i++) {
1983 /* read MC_STATUS */
1984 tmp = RREG32(RADEON_MC_STATUS);
1985 if (tmp & RADEON_MC_IDLE) {
1986 return 0;
1987 }
1988 DRM_UDELAY(1);
1989 }
1990 return -1;
1991 }
1992
1993 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1994 {
1995 lockup->last_cp_rptr = cp->rptr;
1996 lockup->last_jiffies = jiffies;
1997 }
1998
1999 /**
2000 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2001 * @rdev: radeon device structure
2002 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
2003 * @cp: radeon_cp structure holding CP information
2004 *
2005 * We don't need to initialize the lockup tracking information as we will either
2006 * have CP rptr to a different value of jiffies wrap around which will force
2007 * initialization of the lockup tracking informations.
2008 *
2009 * A possible false positivie is if we get call after while and last_cp_rptr ==
2010 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2011 * if the elapsed time since last call is bigger than 2 second than we return
2012 * false and update the tracking information. Due to this the caller must call
2013 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2014 * the fencing code should be cautious about that.
2015 *
2016 * Caller should write to the ring to force CP to do something so we don't get
2017 * false positive when CP is just gived nothing to do.
2018 *
2019 **/
2020 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2021 {
2022 unsigned long cjiffies, elapsed;
2023
2024 cjiffies = jiffies;
2025 if (!time_after(cjiffies, lockup->last_jiffies)) {
2026 /* likely a wrap around */
2027 lockup->last_cp_rptr = cp->rptr;
2028 lockup->last_jiffies = jiffies;
2029 return false;
2030 }
2031 if (cp->rptr != lockup->last_cp_rptr) {
2032 /* CP is still working no lockup */
2033 lockup->last_cp_rptr = cp->rptr;
2034 lockup->last_jiffies = jiffies;
2035 return false;
2036 }
2037 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2038 if (elapsed >= 10000) {
2039 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2040 return true;
2041 }
2042 /* give a chance to the GPU ... */
2043 return false;
2044 }
2045
2046 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2047 {
2048 u32 rbbm_status;
2049 int r;
2050
2051 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2052 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2053 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2054 return false;
2055 }
2056 /* force CP activities */
2057 r = radeon_ring_lock(rdev, 2);
2058 if (!r) {
2059 /* PACKET2 NOP */
2060 radeon_ring_write(rdev, 0x80000000);
2061 radeon_ring_write(rdev, 0x80000000);
2062 radeon_ring_unlock_commit(rdev);
2063 }
2064 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2065 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2066 }
2067
2068 void r100_bm_disable(struct radeon_device *rdev)
2069 {
2070 u32 tmp;
2071
2072 /* disable bus mastering */
2073 tmp = RREG32(R_000030_BUS_CNTL);
2074 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2075 mdelay(1);
2076 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2077 mdelay(1);
2078 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2079 tmp = RREG32(RADEON_BUS_CNTL);
2080 mdelay(1);
2081 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2082 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2083 mdelay(1);
2084 }
2085
2086 int r100_asic_reset(struct radeon_device *rdev)
2087 {
2088 struct r100_mc_save save;
2089 u32 status, tmp;
2090 int ret = 0;
2091
2092 status = RREG32(R_000E40_RBBM_STATUS);
2093 if (!G_000E40_GUI_ACTIVE(status)) {
2094 return 0;
2095 }
2096 r100_mc_stop(rdev, &save);
2097 status = RREG32(R_000E40_RBBM_STATUS);
2098 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2099 /* stop CP */
2100 WREG32(RADEON_CP_CSQ_CNTL, 0);
2101 tmp = RREG32(RADEON_CP_RB_CNTL);
2102 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2103 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2104 WREG32(RADEON_CP_RB_WPTR, 0);
2105 WREG32(RADEON_CP_RB_CNTL, tmp);
2106 /* save PCI state */
2107 pci_save_state(rdev->pdev);
2108 /* disable bus mastering */
2109 r100_bm_disable(rdev);
2110 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2111 S_0000F0_SOFT_RESET_RE(1) |
2112 S_0000F0_SOFT_RESET_PP(1) |
2113 S_0000F0_SOFT_RESET_RB(1));
2114 RREG32(R_0000F0_RBBM_SOFT_RESET);
2115 mdelay(500);
2116 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2117 mdelay(1);
2118 status = RREG32(R_000E40_RBBM_STATUS);
2119 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2120 /* reset CP */
2121 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2122 RREG32(R_0000F0_RBBM_SOFT_RESET);
2123 mdelay(500);
2124 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2125 mdelay(1);
2126 status = RREG32(R_000E40_RBBM_STATUS);
2127 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2128 /* restore PCI & busmastering */
2129 pci_restore_state(rdev->pdev);
2130 r100_enable_bm(rdev);
2131 /* Check if GPU is idle */
2132 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2133 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2134 dev_err(rdev->dev, "failed to reset GPU\n");
2135 rdev->gpu_lockup = true;
2136 ret = -1;
2137 } else
2138 dev_info(rdev->dev, "GPU reset succeed\n");
2139 r100_mc_resume(rdev, &save);
2140 return ret;
2141 }
2142
2143 void r100_set_common_regs(struct radeon_device *rdev)
2144 {
2145 struct drm_device *dev = rdev->ddev;
2146 bool force_dac2 = false;
2147 u32 tmp;
2148
2149 /* set these so they don't interfere with anything */
2150 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2151 WREG32(RADEON_SUBPIC_CNTL, 0);
2152 WREG32(RADEON_VIPH_CONTROL, 0);
2153 WREG32(RADEON_I2C_CNTL_1, 0);
2154 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2155 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2156 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2157
2158 /* always set up dac2 on rn50 and some rv100 as lots
2159 * of servers seem to wire it up to a VGA port but
2160 * don't report it in the bios connector
2161 * table.
2162 */
2163 switch (dev->pdev->device) {
2164 /* RN50 */
2165 case 0x515e:
2166 case 0x5969:
2167 force_dac2 = true;
2168 break;
2169 /* RV100*/
2170 case 0x5159:
2171 case 0x515a:
2172 /* DELL triple head servers */
2173 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2174 ((dev->pdev->subsystem_device == 0x016c) ||
2175 (dev->pdev->subsystem_device == 0x016d) ||
2176 (dev->pdev->subsystem_device == 0x016e) ||
2177 (dev->pdev->subsystem_device == 0x016f) ||
2178 (dev->pdev->subsystem_device == 0x0170) ||
2179 (dev->pdev->subsystem_device == 0x017d) ||
2180 (dev->pdev->subsystem_device == 0x017e) ||
2181 (dev->pdev->subsystem_device == 0x0183) ||
2182 (dev->pdev->subsystem_device == 0x018a) ||
2183 (dev->pdev->subsystem_device == 0x019a)))
2184 force_dac2 = true;
2185 break;
2186 }
2187
2188 if (force_dac2) {
2189 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2190 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2191 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2192
2193 /* For CRT on DAC2, don't turn it on if BIOS didn't
2194 enable it, even it's detected.
2195 */
2196
2197 /* force it to crtc0 */
2198 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2199 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2200 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2201
2202 /* set up the TV DAC */
2203 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2204 RADEON_TV_DAC_STD_MASK |
2205 RADEON_TV_DAC_RDACPD |
2206 RADEON_TV_DAC_GDACPD |
2207 RADEON_TV_DAC_BDACPD |
2208 RADEON_TV_DAC_BGADJ_MASK |
2209 RADEON_TV_DAC_DACADJ_MASK);
2210 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2211 RADEON_TV_DAC_NHOLD |
2212 RADEON_TV_DAC_STD_PS2 |
2213 (0x58 << 16));
2214
2215 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2216 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2217 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2218 }
2219
2220 /* switch PM block to ACPI mode */
2221 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2222 tmp &= ~RADEON_PM_MODE_SEL;
2223 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2224
2225 }
2226
2227 /*
2228 * VRAM info
2229 */
2230 static void r100_vram_get_type(struct radeon_device *rdev)
2231 {
2232 uint32_t tmp;
2233
2234 rdev->mc.vram_is_ddr = false;
2235 if (rdev->flags & RADEON_IS_IGP)
2236 rdev->mc.vram_is_ddr = true;
2237 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2238 rdev->mc.vram_is_ddr = true;
2239 if ((rdev->family == CHIP_RV100) ||
2240 (rdev->family == CHIP_RS100) ||
2241 (rdev->family == CHIP_RS200)) {
2242 tmp = RREG32(RADEON_MEM_CNTL);
2243 if (tmp & RV100_HALF_MODE) {
2244 rdev->mc.vram_width = 32;
2245 } else {
2246 rdev->mc.vram_width = 64;
2247 }
2248 if (rdev->flags & RADEON_SINGLE_CRTC) {
2249 rdev->mc.vram_width /= 4;
2250 rdev->mc.vram_is_ddr = true;
2251 }
2252 } else if (rdev->family <= CHIP_RV280) {
2253 tmp = RREG32(RADEON_MEM_CNTL);
2254 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2255 rdev->mc.vram_width = 128;
2256 } else {
2257 rdev->mc.vram_width = 64;
2258 }
2259 } else {
2260 /* newer IGPs */
2261 rdev->mc.vram_width = 128;
2262 }
2263 }
2264
2265 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2266 {
2267 u32 aper_size;
2268 u8 byte;
2269
2270 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2271
2272 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2273 * that is has the 2nd generation multifunction PCI interface
2274 */
2275 if (rdev->family == CHIP_RV280 ||
2276 rdev->family >= CHIP_RV350) {
2277 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2278 ~RADEON_HDP_APER_CNTL);
2279 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2280 return aper_size * 2;
2281 }
2282
2283 /* Older cards have all sorts of funny issues to deal with. First
2284 * check if it's a multifunction card by reading the PCI config
2285 * header type... Limit those to one aperture size
2286 */
2287 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2288 if (byte & 0x80) {
2289 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2290 DRM_INFO("Limiting VRAM to one aperture\n");
2291 return aper_size;
2292 }
2293
2294 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2295 * have set it up. We don't write this as it's broken on some ASICs but
2296 * we expect the BIOS to have done the right thing (might be too optimistic...)
2297 */
2298 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2299 return aper_size * 2;
2300 return aper_size;
2301 }
2302
2303 void r100_vram_init_sizes(struct radeon_device *rdev)
2304 {
2305 u64 config_aper_size;
2306
2307 /* work out accessible VRAM */
2308 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2309 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2310 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2311 /* FIXME we don't use the second aperture yet when we could use it */
2312 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2313 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2314 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2315 if (rdev->flags & RADEON_IS_IGP) {
2316 uint32_t tom;
2317 /* read NB_TOM to get the amount of ram stolen for the GPU */
2318 tom = RREG32(RADEON_NB_TOM);
2319 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2320 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2321 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2322 } else {
2323 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2324 /* Some production boards of m6 will report 0
2325 * if it's 8 MB
2326 */
2327 if (rdev->mc.real_vram_size == 0) {
2328 rdev->mc.real_vram_size = 8192 * 1024;
2329 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2330 }
2331 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2332 * Novell bug 204882 + along with lots of ubuntu ones
2333 */
2334 if (rdev->mc.aper_size > config_aper_size)
2335 config_aper_size = rdev->mc.aper_size;
2336
2337 if (config_aper_size > rdev->mc.real_vram_size)
2338 rdev->mc.mc_vram_size = config_aper_size;
2339 else
2340 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2341 }
2342 }
2343
2344 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2345 {
2346 uint32_t temp;
2347
2348 temp = RREG32(RADEON_CONFIG_CNTL);
2349 if (state == false) {
2350 temp &= ~RADEON_CFG_VGA_RAM_EN;
2351 temp |= RADEON_CFG_VGA_IO_DIS;
2352 } else {
2353 temp &= ~RADEON_CFG_VGA_IO_DIS;
2354 }
2355 WREG32(RADEON_CONFIG_CNTL, temp);
2356 }
2357
2358 void r100_mc_init(struct radeon_device *rdev)
2359 {
2360 u64 base;
2361
2362 r100_vram_get_type(rdev);
2363 r100_vram_init_sizes(rdev);
2364 base = rdev->mc.aper_base;
2365 if (rdev->flags & RADEON_IS_IGP)
2366 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2367 radeon_vram_location(rdev, &rdev->mc, base);
2368 rdev->mc.gtt_base_align = 0;
2369 if (!(rdev->flags & RADEON_IS_AGP))
2370 radeon_gtt_location(rdev, &rdev->mc);
2371 radeon_update_bandwidth_info(rdev);
2372 }
2373
2374
2375 /*
2376 * Indirect registers accessor
2377 */
2378 void r100_pll_errata_after_index(struct radeon_device *rdev)
2379 {
2380 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2381 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2382 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2383 }
2384 }
2385
2386 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2387 {
2388 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2389 * or the chip could hang on a subsequent access
2390 */
2391 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2392 udelay(5000);
2393 }
2394
2395 /* This function is required to workaround a hardware bug in some (all?)
2396 * revisions of the R300. This workaround should be called after every
2397 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2398 * may not be correct.
2399 */
2400 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2401 uint32_t save, tmp;
2402
2403 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2404 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2405 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2406 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2407 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2408 }
2409 }
2410
2411 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2412 {
2413 uint32_t data;
2414
2415 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2416 r100_pll_errata_after_index(rdev);
2417 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2418 r100_pll_errata_after_data(rdev);
2419 return data;
2420 }
2421
2422 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2423 {
2424 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2425 r100_pll_errata_after_index(rdev);
2426 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2427 r100_pll_errata_after_data(rdev);
2428 }
2429
2430 void r100_set_safe_registers(struct radeon_device *rdev)
2431 {
2432 if (ASIC_IS_RN50(rdev)) {
2433 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2434 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2435 } else if (rdev->family < CHIP_R200) {
2436 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2437 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2438 } else {
2439 r200_set_safe_registers(rdev);
2440 }
2441 }
2442
2443 /*
2444 * Debugfs info
2445 */
2446 #if defined(CONFIG_DEBUG_FS)
2447 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2448 {
2449 struct drm_info_node *node = (struct drm_info_node *) m->private;
2450 struct drm_device *dev = node->minor->dev;
2451 struct radeon_device *rdev = dev->dev_private;
2452 uint32_t reg, value;
2453 unsigned i;
2454
2455 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2456 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2457 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2458 for (i = 0; i < 64; i++) {
2459 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2460 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2461 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2462 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2463 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2464 }
2465 return 0;
2466 }
2467
2468 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2469 {
2470 struct drm_info_node *node = (struct drm_info_node *) m->private;
2471 struct drm_device *dev = node->minor->dev;
2472 struct radeon_device *rdev = dev->dev_private;
2473 uint32_t rdp, wdp;
2474 unsigned count, i, j;
2475
2476 radeon_ring_free_size(rdev);
2477 rdp = RREG32(RADEON_CP_RB_RPTR);
2478 wdp = RREG32(RADEON_CP_RB_WPTR);
2479 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2480 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2481 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2482 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2483 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2484 seq_printf(m, "%u dwords in ring\n", count);
2485 for (j = 0; j <= count; j++) {
2486 i = (rdp + j) & rdev->cp.ptr_mask;
2487 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2488 }
2489 return 0;
2490 }
2491
2492
2493 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2494 {
2495 struct drm_info_node *node = (struct drm_info_node *) m->private;
2496 struct drm_device *dev = node->minor->dev;
2497 struct radeon_device *rdev = dev->dev_private;
2498 uint32_t csq_stat, csq2_stat, tmp;
2499 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2500 unsigned i;
2501
2502 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2503 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2504 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2505 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2506 r_rptr = (csq_stat >> 0) & 0x3ff;
2507 r_wptr = (csq_stat >> 10) & 0x3ff;
2508 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2509 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2510 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2511 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2512 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2513 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2514 seq_printf(m, "Ring rptr %u\n", r_rptr);
2515 seq_printf(m, "Ring wptr %u\n", r_wptr);
2516 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2517 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2518 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2519 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2520 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2521 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2522 seq_printf(m, "Ring fifo:\n");
2523 for (i = 0; i < 256; i++) {
2524 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2525 tmp = RREG32(RADEON_CP_CSQ_DATA);
2526 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2527 }
2528 seq_printf(m, "Indirect1 fifo:\n");
2529 for (i = 256; i <= 512; i++) {
2530 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2531 tmp = RREG32(RADEON_CP_CSQ_DATA);
2532 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2533 }
2534 seq_printf(m, "Indirect2 fifo:\n");
2535 for (i = 640; i < ib1_wptr; i++) {
2536 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2537 tmp = RREG32(RADEON_CP_CSQ_DATA);
2538 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2539 }
2540 return 0;
2541 }
2542
2543 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2544 {
2545 struct drm_info_node *node = (struct drm_info_node *) m->private;
2546 struct drm_device *dev = node->minor->dev;
2547 struct radeon_device *rdev = dev->dev_private;
2548 uint32_t tmp;
2549
2550 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2551 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2552 tmp = RREG32(RADEON_MC_FB_LOCATION);
2553 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2554 tmp = RREG32(RADEON_BUS_CNTL);
2555 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2556 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2557 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2558 tmp = RREG32(RADEON_AGP_BASE);
2559 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2560 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2561 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2562 tmp = RREG32(0x01D0);
2563 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2564 tmp = RREG32(RADEON_AIC_LO_ADDR);
2565 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2566 tmp = RREG32(RADEON_AIC_HI_ADDR);
2567 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2568 tmp = RREG32(0x01E4);
2569 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2570 return 0;
2571 }
2572
2573 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2574 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2575 };
2576
2577 static struct drm_info_list r100_debugfs_cp_list[] = {
2578 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2579 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2580 };
2581
2582 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2583 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2584 };
2585 #endif
2586
2587 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2588 {
2589 #if defined(CONFIG_DEBUG_FS)
2590 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2591 #else
2592 return 0;
2593 #endif
2594 }
2595
2596 int r100_debugfs_cp_init(struct radeon_device *rdev)
2597 {
2598 #if defined(CONFIG_DEBUG_FS)
2599 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2600 #else
2601 return 0;
2602 #endif
2603 }
2604
2605 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2606 {
2607 #if defined(CONFIG_DEBUG_FS)
2608 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2609 #else
2610 return 0;
2611 #endif
2612 }
2613
2614 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2615 uint32_t tiling_flags, uint32_t pitch,
2616 uint32_t offset, uint32_t obj_size)
2617 {
2618 int surf_index = reg * 16;
2619 int flags = 0;
2620
2621 if (rdev->family <= CHIP_RS200) {
2622 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2623 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2624 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2625 if (tiling_flags & RADEON_TILING_MACRO)
2626 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2627 } else if (rdev->family <= CHIP_RV280) {
2628 if (tiling_flags & (RADEON_TILING_MACRO))
2629 flags |= R200_SURF_TILE_COLOR_MACRO;
2630 if (tiling_flags & RADEON_TILING_MICRO)
2631 flags |= R200_SURF_TILE_COLOR_MICRO;
2632 } else {
2633 if (tiling_flags & RADEON_TILING_MACRO)
2634 flags |= R300_SURF_TILE_MACRO;
2635 if (tiling_flags & RADEON_TILING_MICRO)
2636 flags |= R300_SURF_TILE_MICRO;
2637 }
2638
2639 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2640 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2641 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2642 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2643
2644 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2645 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2646 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2647 if (ASIC_IS_RN50(rdev))
2648 pitch /= 16;
2649 }
2650
2651 /* r100/r200 divide by 16 */
2652 if (rdev->family < CHIP_R300)
2653 flags |= pitch / 16;
2654 else
2655 flags |= pitch / 8;
2656
2657
2658 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2659 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2660 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2661 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2662 return 0;
2663 }
2664
2665 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2666 {
2667 int surf_index = reg * 16;
2668 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2669 }
2670
2671 void r100_bandwidth_update(struct radeon_device *rdev)
2672 {
2673 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2674 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2675 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2676 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2677 fixed20_12 memtcas_ff[8] = {
2678 dfixed_init(1),
2679 dfixed_init(2),
2680 dfixed_init(3),
2681 dfixed_init(0),
2682 dfixed_init_half(1),
2683 dfixed_init_half(2),
2684 dfixed_init(0),
2685 };
2686 fixed20_12 memtcas_rs480_ff[8] = {
2687 dfixed_init(0),
2688 dfixed_init(1),
2689 dfixed_init(2),
2690 dfixed_init(3),
2691 dfixed_init(0),
2692 dfixed_init_half(1),
2693 dfixed_init_half(2),
2694 dfixed_init_half(3),
2695 };
2696 fixed20_12 memtcas2_ff[8] = {
2697 dfixed_init(0),
2698 dfixed_init(1),
2699 dfixed_init(2),
2700 dfixed_init(3),
2701 dfixed_init(4),
2702 dfixed_init(5),
2703 dfixed_init(6),
2704 dfixed_init(7),
2705 };
2706 fixed20_12 memtrbs[8] = {
2707 dfixed_init(1),
2708 dfixed_init_half(1),
2709 dfixed_init(2),
2710 dfixed_init_half(2),
2711 dfixed_init(3),
2712 dfixed_init_half(3),
2713 dfixed_init(4),
2714 dfixed_init_half(4)
2715 };
2716 fixed20_12 memtrbs_r4xx[8] = {
2717 dfixed_init(4),
2718 dfixed_init(5),
2719 dfixed_init(6),
2720 dfixed_init(7),
2721 dfixed_init(8),
2722 dfixed_init(9),
2723 dfixed_init(10),
2724 dfixed_init(11)
2725 };
2726 fixed20_12 min_mem_eff;
2727 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2728 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2729 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2730 disp_drain_rate2, read_return_rate;
2731 fixed20_12 time_disp1_drop_priority;
2732 int c;
2733 int cur_size = 16; /* in octawords */
2734 int critical_point = 0, critical_point2;
2735 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2736 int stop_req, max_stop_req;
2737 struct drm_display_mode *mode1 = NULL;
2738 struct drm_display_mode *mode2 = NULL;
2739 uint32_t pixel_bytes1 = 0;
2740 uint32_t pixel_bytes2 = 0;
2741
2742 radeon_update_display_priority(rdev);
2743
2744 if (rdev->mode_info.crtcs[0]->base.enabled) {
2745 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2746 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2747 }
2748 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2749 if (rdev->mode_info.crtcs[1]->base.enabled) {
2750 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2751 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2752 }
2753 }
2754
2755 min_mem_eff.full = dfixed_const_8(0);
2756 /* get modes */
2757 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2758 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2759 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2760 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2761 /* check crtc enables */
2762 if (mode2)
2763 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2764 if (mode1)
2765 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2766 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2767 }
2768
2769 /*
2770 * determine is there is enough bw for current mode
2771 */
2772 sclk_ff = rdev->pm.sclk;
2773 mclk_ff = rdev->pm.mclk;
2774
2775 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2776 temp_ff.full = dfixed_const(temp);
2777 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2778
2779 pix_clk.full = 0;
2780 pix_clk2.full = 0;
2781 peak_disp_bw.full = 0;
2782 if (mode1) {
2783 temp_ff.full = dfixed_const(1000);
2784 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2785 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2786 temp_ff.full = dfixed_const(pixel_bytes1);
2787 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2788 }
2789 if (mode2) {
2790 temp_ff.full = dfixed_const(1000);
2791 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2792 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2793 temp_ff.full = dfixed_const(pixel_bytes2);
2794 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2795 }
2796
2797 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2798 if (peak_disp_bw.full >= mem_bw.full) {
2799 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2800 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2801 }
2802
2803 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2804 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2805 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2806 mem_trcd = ((temp >> 2) & 0x3) + 1;
2807 mem_trp = ((temp & 0x3)) + 1;
2808 mem_tras = ((temp & 0x70) >> 4) + 1;
2809 } else if (rdev->family == CHIP_R300 ||
2810 rdev->family == CHIP_R350) { /* r300, r350 */
2811 mem_trcd = (temp & 0x7) + 1;
2812 mem_trp = ((temp >> 8) & 0x7) + 1;
2813 mem_tras = ((temp >> 11) & 0xf) + 4;
2814 } else if (rdev->family == CHIP_RV350 ||
2815 rdev->family <= CHIP_RV380) {
2816 /* rv3x0 */
2817 mem_trcd = (temp & 0x7) + 3;
2818 mem_trp = ((temp >> 8) & 0x7) + 3;
2819 mem_tras = ((temp >> 11) & 0xf) + 6;
2820 } else if (rdev->family == CHIP_R420 ||
2821 rdev->family == CHIP_R423 ||
2822 rdev->family == CHIP_RV410) {
2823 /* r4xx */
2824 mem_trcd = (temp & 0xf) + 3;
2825 if (mem_trcd > 15)
2826 mem_trcd = 15;
2827 mem_trp = ((temp >> 8) & 0xf) + 3;
2828 if (mem_trp > 15)
2829 mem_trp = 15;
2830 mem_tras = ((temp >> 12) & 0x1f) + 6;
2831 if (mem_tras > 31)
2832 mem_tras = 31;
2833 } else { /* RV200, R200 */
2834 mem_trcd = (temp & 0x7) + 1;
2835 mem_trp = ((temp >> 8) & 0x7) + 1;
2836 mem_tras = ((temp >> 12) & 0xf) + 4;
2837 }
2838 /* convert to FF */
2839 trcd_ff.full = dfixed_const(mem_trcd);
2840 trp_ff.full = dfixed_const(mem_trp);
2841 tras_ff.full = dfixed_const(mem_tras);
2842
2843 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2844 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2845 data = (temp & (7 << 20)) >> 20;
2846 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2847 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2848 tcas_ff = memtcas_rs480_ff[data];
2849 else
2850 tcas_ff = memtcas_ff[data];
2851 } else
2852 tcas_ff = memtcas2_ff[data];
2853
2854 if (rdev->family == CHIP_RS400 ||
2855 rdev->family == CHIP_RS480) {
2856 /* extra cas latency stored in bits 23-25 0-4 clocks */
2857 data = (temp >> 23) & 0x7;
2858 if (data < 5)
2859 tcas_ff.full += dfixed_const(data);
2860 }
2861
2862 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2863 /* on the R300, Tcas is included in Trbs.
2864 */
2865 temp = RREG32(RADEON_MEM_CNTL);
2866 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2867 if (data == 1) {
2868 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2869 temp = RREG32(R300_MC_IND_INDEX);
2870 temp &= ~R300_MC_IND_ADDR_MASK;
2871 temp |= R300_MC_READ_CNTL_CD_mcind;
2872 WREG32(R300_MC_IND_INDEX, temp);
2873 temp = RREG32(R300_MC_IND_DATA);
2874 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2875 } else {
2876 temp = RREG32(R300_MC_READ_CNTL_AB);
2877 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2878 }
2879 } else {
2880 temp = RREG32(R300_MC_READ_CNTL_AB);
2881 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2882 }
2883 if (rdev->family == CHIP_RV410 ||
2884 rdev->family == CHIP_R420 ||
2885 rdev->family == CHIP_R423)
2886 trbs_ff = memtrbs_r4xx[data];
2887 else
2888 trbs_ff = memtrbs[data];
2889 tcas_ff.full += trbs_ff.full;
2890 }
2891
2892 sclk_eff_ff.full = sclk_ff.full;
2893
2894 if (rdev->flags & RADEON_IS_AGP) {
2895 fixed20_12 agpmode_ff;
2896 agpmode_ff.full = dfixed_const(radeon_agpmode);
2897 temp_ff.full = dfixed_const_666(16);
2898 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2899 }
2900 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2901
2902 if (ASIC_IS_R300(rdev)) {
2903 sclk_delay_ff.full = dfixed_const(250);
2904 } else {
2905 if ((rdev->family == CHIP_RV100) ||
2906 rdev->flags & RADEON_IS_IGP) {
2907 if (rdev->mc.vram_is_ddr)
2908 sclk_delay_ff.full = dfixed_const(41);
2909 else
2910 sclk_delay_ff.full = dfixed_const(33);
2911 } else {
2912 if (rdev->mc.vram_width == 128)
2913 sclk_delay_ff.full = dfixed_const(57);
2914 else
2915 sclk_delay_ff.full = dfixed_const(41);
2916 }
2917 }
2918
2919 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
2920
2921 if (rdev->mc.vram_is_ddr) {
2922 if (rdev->mc.vram_width == 32) {
2923 k1.full = dfixed_const(40);
2924 c = 3;
2925 } else {
2926 k1.full = dfixed_const(20);
2927 c = 1;
2928 }
2929 } else {
2930 k1.full = dfixed_const(40);
2931 c = 3;
2932 }
2933
2934 temp_ff.full = dfixed_const(2);
2935 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2936 temp_ff.full = dfixed_const(c);
2937 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2938 temp_ff.full = dfixed_const(4);
2939 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2940 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
2941 mc_latency_mclk.full += k1.full;
2942
2943 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2944 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
2945
2946 /*
2947 HW cursor time assuming worst case of full size colour cursor.
2948 */
2949 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2950 temp_ff.full += trcd_ff.full;
2951 if (temp_ff.full < tras_ff.full)
2952 temp_ff.full = tras_ff.full;
2953 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
2954
2955 temp_ff.full = dfixed_const(cur_size);
2956 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
2957 /*
2958 Find the total latency for the display data.
2959 */
2960 disp_latency_overhead.full = dfixed_const(8);
2961 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
2962 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2963 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2964
2965 if (mc_latency_mclk.full > mc_latency_sclk.full)
2966 disp_latency.full = mc_latency_mclk.full;
2967 else
2968 disp_latency.full = mc_latency_sclk.full;
2969
2970 /* setup Max GRPH_STOP_REQ default value */
2971 if (ASIC_IS_RV100(rdev))
2972 max_stop_req = 0x5c;
2973 else
2974 max_stop_req = 0x7c;
2975
2976 if (mode1) {
2977 /* CRTC1
2978 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2979 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2980 */
2981 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2982
2983 if (stop_req > max_stop_req)
2984 stop_req = max_stop_req;
2985
2986 /*
2987 Find the drain rate of the display buffer.
2988 */
2989 temp_ff.full = dfixed_const((16/pixel_bytes1));
2990 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
2991
2992 /*
2993 Find the critical point of the display buffer.
2994 */
2995 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
2996 crit_point_ff.full += dfixed_const_half(0);
2997
2998 critical_point = dfixed_trunc(crit_point_ff);
2999
3000 if (rdev->disp_priority == 2) {
3001 critical_point = 0;
3002 }
3003
3004 /*
3005 The critical point should never be above max_stop_req-4. Setting
3006 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3007 */
3008 if (max_stop_req - critical_point < 4)
3009 critical_point = 0;
3010
3011 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3012 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3013 critical_point = 0x10;
3014 }
3015
3016 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3017 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3018 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3019 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3020 if ((rdev->family == CHIP_R350) &&
3021 (stop_req > 0x15)) {
3022 stop_req -= 0x10;
3023 }
3024 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3025 temp |= RADEON_GRPH_BUFFER_SIZE;
3026 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3027 RADEON_GRPH_CRITICAL_AT_SOF |
3028 RADEON_GRPH_STOP_CNTL);
3029 /*
3030 Write the result into the register.
3031 */
3032 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3033 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3034
3035 #if 0
3036 if ((rdev->family == CHIP_RS400) ||
3037 (rdev->family == CHIP_RS480)) {
3038 /* attempt to program RS400 disp regs correctly ??? */
3039 temp = RREG32(RS400_DISP1_REG_CNTL);
3040 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3041 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3042 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3043 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3044 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3045 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3046 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3047 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3048 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3049 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3050 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3051 }
3052 #endif
3053
3054 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3055 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3056 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3057 }
3058
3059 if (mode2) {
3060 u32 grph2_cntl;
3061 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3062
3063 if (stop_req > max_stop_req)
3064 stop_req = max_stop_req;
3065
3066 /*
3067 Find the drain rate of the display buffer.
3068 */
3069 temp_ff.full = dfixed_const((16/pixel_bytes2));
3070 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3071
3072 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3073 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3074 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3075 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3076 if ((rdev->family == CHIP_R350) &&
3077 (stop_req > 0x15)) {
3078 stop_req -= 0x10;
3079 }
3080 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3081 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3082 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3083 RADEON_GRPH_CRITICAL_AT_SOF |
3084 RADEON_GRPH_STOP_CNTL);
3085
3086 if ((rdev->family == CHIP_RS100) ||
3087 (rdev->family == CHIP_RS200))
3088 critical_point2 = 0;
3089 else {
3090 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3091 temp_ff.full = dfixed_const(temp);
3092 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3093 if (sclk_ff.full < temp_ff.full)
3094 temp_ff.full = sclk_ff.full;
3095
3096 read_return_rate.full = temp_ff.full;
3097
3098 if (mode1) {
3099 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3100 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3101 } else {
3102 time_disp1_drop_priority.full = 0;
3103 }
3104 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3105 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3106 crit_point_ff.full += dfixed_const_half(0);
3107
3108 critical_point2 = dfixed_trunc(crit_point_ff);
3109
3110 if (rdev->disp_priority == 2) {
3111 critical_point2 = 0;
3112 }
3113
3114 if (max_stop_req - critical_point2 < 4)
3115 critical_point2 = 0;
3116
3117 }
3118
3119 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3120 /* some R300 cards have problem with this set to 0 */
3121 critical_point2 = 0x10;
3122 }
3123
3124 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3125 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3126
3127 if ((rdev->family == CHIP_RS400) ||
3128 (rdev->family == CHIP_RS480)) {
3129 #if 0
3130 /* attempt to program RS400 disp2 regs correctly ??? */
3131 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3132 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3133 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3134 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3135 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3136 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3137 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3138 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3139 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3140 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3141 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3142 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3143 #endif
3144 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3145 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3146 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3147 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3148 }
3149
3150 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3151 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3152 }
3153 }
3154
3155 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3156 {
3157 DRM_ERROR("pitch %d\n", t->pitch);
3158 DRM_ERROR("use_pitch %d\n", t->use_pitch);
3159 DRM_ERROR("width %d\n", t->width);
3160 DRM_ERROR("width_11 %d\n", t->width_11);
3161 DRM_ERROR("height %d\n", t->height);
3162 DRM_ERROR("height_11 %d\n", t->height_11);
3163 DRM_ERROR("num levels %d\n", t->num_levels);
3164 DRM_ERROR("depth %d\n", t->txdepth);
3165 DRM_ERROR("bpp %d\n", t->cpp);
3166 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3167 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3168 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3169 DRM_ERROR("compress format %d\n", t->compress_format);
3170 }
3171
3172 static int r100_track_compress_size(int compress_format, int w, int h)
3173 {
3174 int block_width, block_height, block_bytes;
3175 int wblocks, hblocks;
3176 int min_wblocks;
3177 int sz;
3178
3179 block_width = 4;
3180 block_height = 4;
3181
3182 switch (compress_format) {
3183 case R100_TRACK_COMP_DXT1:
3184 block_bytes = 8;
3185 min_wblocks = 4;
3186 break;
3187 default:
3188 case R100_TRACK_COMP_DXT35:
3189 block_bytes = 16;
3190 min_wblocks = 2;
3191 break;
3192 }
3193
3194 hblocks = (h + block_height - 1) / block_height;
3195 wblocks = (w + block_width - 1) / block_width;
3196 if (wblocks < min_wblocks)
3197 wblocks = min_wblocks;
3198 sz = wblocks * hblocks * block_bytes;
3199 return sz;
3200 }
3201
3202 static int r100_cs_track_cube(struct radeon_device *rdev,
3203 struct r100_cs_track *track, unsigned idx)
3204 {
3205 unsigned face, w, h;
3206 struct radeon_bo *cube_robj;
3207 unsigned long size;
3208 unsigned compress_format = track->textures[idx].compress_format;
3209
3210 for (face = 0; face < 5; face++) {
3211 cube_robj = track->textures[idx].cube_info[face].robj;
3212 w = track->textures[idx].cube_info[face].width;
3213 h = track->textures[idx].cube_info[face].height;
3214
3215 if (compress_format) {
3216 size = r100_track_compress_size(compress_format, w, h);
3217 } else
3218 size = w * h;
3219 size *= track->textures[idx].cpp;
3220
3221 size += track->textures[idx].cube_info[face].offset;
3222
3223 if (size > radeon_bo_size(cube_robj)) {
3224 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3225 size, radeon_bo_size(cube_robj));
3226 r100_cs_track_texture_print(&track->textures[idx]);
3227 return -1;
3228 }
3229 }
3230 return 0;
3231 }
3232
3233 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3234 struct r100_cs_track *track)
3235 {
3236 struct radeon_bo *robj;
3237 unsigned long size;
3238 unsigned u, i, w, h, d;
3239 int ret;
3240
3241 for (u = 0; u < track->num_texture; u++) {
3242 if (!track->textures[u].enabled)
3243 continue;
3244 if (track->textures[u].lookup_disable)
3245 continue;
3246 robj = track->textures[u].robj;
3247 if (robj == NULL) {
3248 DRM_ERROR("No texture bound to unit %u\n", u);
3249 return -EINVAL;
3250 }
3251 size = 0;
3252 for (i = 0; i <= track->textures[u].num_levels; i++) {
3253 if (track->textures[u].use_pitch) {
3254 if (rdev->family < CHIP_R300)
3255 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3256 else
3257 w = track->textures[u].pitch / (1 << i);
3258 } else {
3259 w = track->textures[u].width;
3260 if (rdev->family >= CHIP_RV515)
3261 w |= track->textures[u].width_11;
3262 w = w / (1 << i);
3263 if (track->textures[u].roundup_w)
3264 w = roundup_pow_of_two(w);
3265 }
3266 h = track->textures[u].height;
3267 if (rdev->family >= CHIP_RV515)
3268 h |= track->textures[u].height_11;
3269 h = h / (1 << i);
3270 if (track->textures[u].roundup_h)
3271 h = roundup_pow_of_two(h);
3272 if (track->textures[u].tex_coord_type == 1) {
3273 d = (1 << track->textures[u].txdepth) / (1 << i);
3274 if (!d)
3275 d = 1;
3276 } else {
3277 d = 1;
3278 }
3279 if (track->textures[u].compress_format) {
3280
3281 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3282 /* compressed textures are block based */
3283 } else
3284 size += w * h * d;
3285 }
3286 size *= track->textures[u].cpp;
3287
3288 switch (track->textures[u].tex_coord_type) {
3289 case 0:
3290 case 1:
3291 break;
3292 case 2:
3293 if (track->separate_cube) {
3294 ret = r100_cs_track_cube(rdev, track, u);
3295 if (ret)
3296 return ret;
3297 } else
3298 size *= 6;
3299 break;
3300 default:
3301 DRM_ERROR("Invalid texture coordinate type %u for unit "
3302 "%u\n", track->textures[u].tex_coord_type, u);
3303 return -EINVAL;
3304 }
3305 if (size > radeon_bo_size(robj)) {
3306 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3307 "%lu\n", u, size, radeon_bo_size(robj));
3308 r100_cs_track_texture_print(&track->textures[u]);
3309 return -EINVAL;
3310 }
3311 }
3312 return 0;
3313 }
3314
3315 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3316 {
3317 unsigned i;
3318 unsigned long size;
3319 unsigned prim_walk;
3320 unsigned nverts;
3321 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3322
3323 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3324 !track->blend_read_enable)
3325 num_cb = 0;
3326
3327 for (i = 0; i < num_cb; i++) {
3328 if (track->cb[i].robj == NULL) {
3329 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3330 return -EINVAL;
3331 }
3332 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3333 size += track->cb[i].offset;
3334 if (size > radeon_bo_size(track->cb[i].robj)) {
3335 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3336 "(need %lu have %lu) !\n", i, size,
3337 radeon_bo_size(track->cb[i].robj));
3338 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3339 i, track->cb[i].pitch, track->cb[i].cpp,
3340 track->cb[i].offset, track->maxy);
3341 return -EINVAL;
3342 }
3343 }
3344 track->cb_dirty = false;
3345
3346 if (track->zb_dirty && track->z_enabled) {
3347 if (track->zb.robj == NULL) {
3348 DRM_ERROR("[drm] No buffer for z buffer !\n");
3349 return -EINVAL;
3350 }
3351 size = track->zb.pitch * track->zb.cpp * track->maxy;
3352 size += track->zb.offset;
3353 if (size > radeon_bo_size(track->zb.robj)) {
3354 DRM_ERROR("[drm] Buffer too small for z buffer "
3355 "(need %lu have %lu) !\n", size,
3356 radeon_bo_size(track->zb.robj));
3357 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3358 track->zb.pitch, track->zb.cpp,
3359 track->zb.offset, track->maxy);
3360 return -EINVAL;
3361 }
3362 }
3363 track->zb_dirty = false;
3364
3365 if (track->aa_dirty && track->aaresolve) {
3366 if (track->aa.robj == NULL) {
3367 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3368 return -EINVAL;
3369 }
3370 /* I believe the format comes from colorbuffer0. */
3371 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3372 size += track->aa.offset;
3373 if (size > radeon_bo_size(track->aa.robj)) {
3374 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3375 "(need %lu have %lu) !\n", i, size,
3376 radeon_bo_size(track->aa.robj));
3377 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3378 i, track->aa.pitch, track->cb[0].cpp,
3379 track->aa.offset, track->maxy);
3380 return -EINVAL;
3381 }
3382 }
3383 track->aa_dirty = false;
3384
3385 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3386 if (track->vap_vf_cntl & (1 << 14)) {
3387 nverts = track->vap_alt_nverts;
3388 } else {
3389 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3390 }
3391 switch (prim_walk) {
3392 case 1:
3393 for (i = 0; i < track->num_arrays; i++) {
3394 size = track->arrays[i].esize * track->max_indx * 4;
3395 if (track->arrays[i].robj == NULL) {
3396 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3397 "bound\n", prim_walk, i);
3398 return -EINVAL;
3399 }
3400 if (size > radeon_bo_size(track->arrays[i].robj)) {
3401 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3402 "need %lu dwords have %lu dwords\n",
3403 prim_walk, i, size >> 2,
3404 radeon_bo_size(track->arrays[i].robj)
3405 >> 2);
3406 DRM_ERROR("Max indices %u\n", track->max_indx);
3407 return -EINVAL;
3408 }
3409 }
3410 break;
3411 case 2:
3412 for (i = 0; i < track->num_arrays; i++) {
3413 size = track->arrays[i].esize * (nverts - 1) * 4;
3414 if (track->arrays[i].robj == NULL) {
3415 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3416 "bound\n", prim_walk, i);
3417 return -EINVAL;
3418 }
3419 if (size > radeon_bo_size(track->arrays[i].robj)) {
3420 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3421 "need %lu dwords have %lu dwords\n",
3422 prim_walk, i, size >> 2,
3423 radeon_bo_size(track->arrays[i].robj)
3424 >> 2);
3425 return -EINVAL;
3426 }
3427 }
3428 break;
3429 case 3:
3430 size = track->vtx_size * nverts;
3431 if (size != track->immd_dwords) {
3432 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3433 track->immd_dwords, size);
3434 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3435 nverts, track->vtx_size);
3436 return -EINVAL;
3437 }
3438 break;
3439 default:
3440 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3441 prim_walk);
3442 return -EINVAL;
3443 }
3444
3445 if (track->tex_dirty) {
3446 track->tex_dirty = false;
3447 return r100_cs_track_texture_check(rdev, track);
3448 }
3449 return 0;
3450 }
3451
3452 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3453 {
3454 unsigned i, face;
3455
3456 track->cb_dirty = true;
3457 track->zb_dirty = true;
3458 track->tex_dirty = true;
3459 track->aa_dirty = true;
3460
3461 if (rdev->family < CHIP_R300) {
3462 track->num_cb = 1;
3463 if (rdev->family <= CHIP_RS200)
3464 track->num_texture = 3;
3465 else
3466 track->num_texture = 6;
3467 track->maxy = 2048;
3468 track->separate_cube = 1;
3469 } else {
3470 track->num_cb = 4;
3471 track->num_texture = 16;
3472 track->maxy = 4096;
3473 track->separate_cube = 0;
3474 track->aaresolve = false;
3475 track->aa.robj = NULL;
3476 }
3477
3478 for (i = 0; i < track->num_cb; i++) {
3479 track->cb[i].robj = NULL;
3480 track->cb[i].pitch = 8192;
3481 track->cb[i].cpp = 16;
3482 track->cb[i].offset = 0;
3483 }
3484 track->z_enabled = true;
3485 track->zb.robj = NULL;
3486 track->zb.pitch = 8192;
3487 track->zb.cpp = 4;
3488 track->zb.offset = 0;
3489 track->vtx_size = 0x7F;
3490 track->immd_dwords = 0xFFFFFFFFUL;
3491 track->num_arrays = 11;
3492 track->max_indx = 0x00FFFFFFUL;
3493 for (i = 0; i < track->num_arrays; i++) {
3494 track->arrays[i].robj = NULL;
3495 track->arrays[i].esize = 0x7F;
3496 }
3497 for (i = 0; i < track->num_texture; i++) {
3498 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3499 track->textures[i].pitch = 16536;
3500 track->textures[i].width = 16536;
3501 track->textures[i].height = 16536;
3502 track->textures[i].width_11 = 1 << 11;
3503 track->textures[i].height_11 = 1 << 11;
3504 track->textures[i].num_levels = 12;
3505 if (rdev->family <= CHIP_RS200) {
3506 track->textures[i].tex_coord_type = 0;
3507 track->textures[i].txdepth = 0;
3508 } else {
3509 track->textures[i].txdepth = 16;
3510 track->textures[i].tex_coord_type = 1;
3511 }
3512 track->textures[i].cpp = 64;
3513 track->textures[i].robj = NULL;
3514 /* CS IB emission code makes sure texture unit are disabled */
3515 track->textures[i].enabled = false;
3516 track->textures[i].lookup_disable = false;
3517 track->textures[i].roundup_w = true;
3518 track->textures[i].roundup_h = true;
3519 if (track->separate_cube)
3520 for (face = 0; face < 5; face++) {
3521 track->textures[i].cube_info[face].robj = NULL;
3522 track->textures[i].cube_info[face].width = 16536;
3523 track->textures[i].cube_info[face].height = 16536;
3524 track->textures[i].cube_info[face].offset = 0;
3525 }
3526 }
3527 }
3528
3529 int r100_ring_test(struct radeon_device *rdev)
3530 {
3531 uint32_t scratch;
3532 uint32_t tmp = 0;
3533 unsigned i;
3534 int r;
3535
3536 r = radeon_scratch_get(rdev, &scratch);
3537 if (r) {
3538 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3539 return r;
3540 }
3541 WREG32(scratch, 0xCAFEDEAD);
3542 r = radeon_ring_lock(rdev, 2);
3543 if (r) {
3544 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3545 radeon_scratch_free(rdev, scratch);
3546 return r;
3547 }
3548 radeon_ring_write(rdev, PACKET0(scratch, 0));
3549 radeon_ring_write(rdev, 0xDEADBEEF);
3550 radeon_ring_unlock_commit(rdev);
3551 for (i = 0; i < rdev->usec_timeout; i++) {
3552 tmp = RREG32(scratch);
3553 if (tmp == 0xDEADBEEF) {
3554 break;
3555 }
3556 DRM_UDELAY(1);
3557 }
3558 if (i < rdev->usec_timeout) {
3559 DRM_INFO("ring test succeeded in %d usecs\n", i);
3560 } else {
3561 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3562 scratch, tmp);
3563 r = -EINVAL;
3564 }
3565 radeon_scratch_free(rdev, scratch);
3566 return r;
3567 }
3568
3569 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3570 {
3571 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3572 radeon_ring_write(rdev, ib->gpu_addr);
3573 radeon_ring_write(rdev, ib->length_dw);
3574 }
3575
3576 int r100_ib_test(struct radeon_device *rdev)
3577 {
3578 struct radeon_ib *ib;
3579 uint32_t scratch;
3580 uint32_t tmp = 0;
3581 unsigned i;
3582 int r;
3583
3584 r = radeon_scratch_get(rdev, &scratch);
3585 if (r) {
3586 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3587 return r;
3588 }
3589 WREG32(scratch, 0xCAFEDEAD);
3590 r = radeon_ib_get(rdev, &ib);
3591 if (r) {
3592 return r;
3593 }
3594 ib->ptr[0] = PACKET0(scratch, 0);
3595 ib->ptr[1] = 0xDEADBEEF;
3596 ib->ptr[2] = PACKET2(0);
3597 ib->ptr[3] = PACKET2(0);
3598 ib->ptr[4] = PACKET2(0);
3599 ib->ptr[5] = PACKET2(0);
3600 ib->ptr[6] = PACKET2(0);
3601 ib->ptr[7] = PACKET2(0);
3602 ib->length_dw = 8;
3603 r = radeon_ib_schedule(rdev, ib);
3604 if (r) {
3605 radeon_scratch_free(rdev, scratch);
3606 radeon_ib_free(rdev, &ib);
3607 return r;
3608 }
3609 r = radeon_fence_wait(ib->fence, false);
3610 if (r) {
3611 return r;
3612 }
3613 for (i = 0; i < rdev->usec_timeout; i++) {
3614 tmp = RREG32(scratch);
3615 if (tmp == 0xDEADBEEF) {
3616 break;
3617 }
3618 DRM_UDELAY(1);
3619 }
3620 if (i < rdev->usec_timeout) {
3621 DRM_INFO("ib test succeeded in %u usecs\n", i);
3622 } else {
3623 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3624 scratch, tmp);
3625 r = -EINVAL;
3626 }
3627 radeon_scratch_free(rdev, scratch);
3628 radeon_ib_free(rdev, &ib);
3629 return r;
3630 }
3631
3632 void r100_ib_fini(struct radeon_device *rdev)
3633 {
3634 radeon_ib_pool_fini(rdev);
3635 }
3636
3637 int r100_ib_init(struct radeon_device *rdev)
3638 {
3639 int r;
3640
3641 r = radeon_ib_pool_init(rdev);
3642 if (r) {
3643 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
3644 r100_ib_fini(rdev);
3645 return r;
3646 }
3647 r = r100_ib_test(rdev);
3648 if (r) {
3649 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3650 r100_ib_fini(rdev);
3651 return r;
3652 }
3653 return 0;
3654 }
3655
3656 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3657 {
3658 /* Shutdown CP we shouldn't need to do that but better be safe than
3659 * sorry
3660 */
3661 rdev->cp.ready = false;
3662 WREG32(R_000740_CP_CSQ_CNTL, 0);
3663
3664 /* Save few CRTC registers */
3665 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3666 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3667 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3668 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3669 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3670 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3671 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3672 }
3673
3674 /* Disable VGA aperture access */
3675 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3676 /* Disable cursor, overlay, crtc */
3677 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3678 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3679 S_000054_CRTC_DISPLAY_DIS(1));
3680 WREG32(R_000050_CRTC_GEN_CNTL,
3681 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3682 S_000050_CRTC_DISP_REQ_EN_B(1));
3683 WREG32(R_000420_OV0_SCALE_CNTL,
3684 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3685 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3686 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3687 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3688 S_000360_CUR2_LOCK(1));
3689 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3690 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3691 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3692 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3693 WREG32(R_000360_CUR2_OFFSET,
3694 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3695 }
3696 }
3697
3698 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3699 {
3700 /* Update base address for crtc */
3701 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3702 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3703 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3704 }
3705 /* Restore CRTC registers */
3706 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3707 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3708 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3709 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3710 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3711 }
3712 }
3713
3714 void r100_vga_render_disable(struct radeon_device *rdev)
3715 {
3716 u32 tmp;
3717
3718 tmp = RREG8(R_0003C2_GENMO_WT);
3719 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3720 }
3721
3722 static void r100_debugfs(struct radeon_device *rdev)
3723 {
3724 int r;
3725
3726 r = r100_debugfs_mc_info_init(rdev);
3727 if (r)
3728 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3729 }
3730
3731 static void r100_mc_program(struct radeon_device *rdev)
3732 {
3733 struct r100_mc_save save;
3734
3735 /* Stops all mc clients */
3736 r100_mc_stop(rdev, &save);
3737 if (rdev->flags & RADEON_IS_AGP) {
3738 WREG32(R_00014C_MC_AGP_LOCATION,
3739 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3740 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3741 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3742 if (rdev->family > CHIP_RV200)
3743 WREG32(R_00015C_AGP_BASE_2,
3744 upper_32_bits(rdev->mc.agp_base) & 0xff);
3745 } else {
3746 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3747 WREG32(R_000170_AGP_BASE, 0);
3748 if (rdev->family > CHIP_RV200)
3749 WREG32(R_00015C_AGP_BASE_2, 0);
3750 }
3751 /* Wait for mc idle */
3752 if (r100_mc_wait_for_idle(rdev))
3753 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3754 /* Program MC, should be a 32bits limited address space */
3755 WREG32(R_000148_MC_FB_LOCATION,
3756 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3757 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3758 r100_mc_resume(rdev, &save);
3759 }
3760
3761 void r100_clock_startup(struct radeon_device *rdev)
3762 {
3763 u32 tmp;
3764
3765 if (radeon_dynclks != -1 && radeon_dynclks)
3766 radeon_legacy_set_clock_gating(rdev, 1);
3767 /* We need to force on some of the block */
3768 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3769 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3770 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3771 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3772 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3773 }
3774
3775 static int r100_startup(struct radeon_device *rdev)
3776 {
3777 int r;
3778
3779 /* set common regs */
3780 r100_set_common_regs(rdev);
3781 /* program mc */
3782 r100_mc_program(rdev);
3783 /* Resume clock */
3784 r100_clock_startup(rdev);
3785 /* Initialize GART (initialize after TTM so we can allocate
3786 * memory through TTM but finalize after TTM) */
3787 r100_enable_bm(rdev);
3788 if (rdev->flags & RADEON_IS_PCI) {
3789 r = r100_pci_gart_enable(rdev);
3790 if (r)
3791 return r;
3792 }
3793
3794 /* allocate wb buffer */
3795 r = radeon_wb_init(rdev);
3796 if (r)
3797 return r;
3798
3799 /* Enable IRQ */
3800 r100_irq_set(rdev);
3801 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3802 /* 1M ring buffer */
3803 r = r100_cp_init(rdev, 1024 * 1024);
3804 if (r) {
3805 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3806 return r;
3807 }
3808 r = r100_ib_init(rdev);
3809 if (r) {
3810 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
3811 return r;
3812 }
3813 return 0;
3814 }
3815
3816 int r100_resume(struct radeon_device *rdev)
3817 {
3818 /* Make sur GART are not working */
3819 if (rdev->flags & RADEON_IS_PCI)
3820 r100_pci_gart_disable(rdev);
3821 /* Resume clock before doing reset */
3822 r100_clock_startup(rdev);
3823 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3824 if (radeon_asic_reset(rdev)) {
3825 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3826 RREG32(R_000E40_RBBM_STATUS),
3827 RREG32(R_0007C0_CP_STAT));
3828 }
3829 /* post */
3830 radeon_combios_asic_init(rdev->ddev);
3831 /* Resume clock after posting */
3832 r100_clock_startup(rdev);
3833 /* Initialize surface registers */
3834 radeon_surface_init(rdev);
3835 return r100_startup(rdev);
3836 }
3837
3838 int r100_suspend(struct radeon_device *rdev)
3839 {
3840 r100_cp_disable(rdev);
3841 radeon_wb_disable(rdev);
3842 r100_irq_disable(rdev);
3843 if (rdev->flags & RADEON_IS_PCI)
3844 r100_pci_gart_disable(rdev);
3845 return 0;
3846 }
3847
3848 void r100_fini(struct radeon_device *rdev)
3849 {
3850 r100_cp_fini(rdev);
3851 radeon_wb_fini(rdev);
3852 r100_ib_fini(rdev);
3853 radeon_gem_fini(rdev);
3854 if (rdev->flags & RADEON_IS_PCI)
3855 r100_pci_gart_fini(rdev);
3856 radeon_agp_fini(rdev);
3857 radeon_irq_kms_fini(rdev);
3858 radeon_fence_driver_fini(rdev);
3859 radeon_bo_fini(rdev);
3860 radeon_atombios_fini(rdev);
3861 kfree(rdev->bios);
3862 rdev->bios = NULL;
3863 }
3864
3865 /*
3866 * Due to how kexec works, it can leave the hw fully initialised when it
3867 * boots the new kernel. However doing our init sequence with the CP and
3868 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3869 * do some quick sanity checks and restore sane values to avoid this
3870 * problem.
3871 */
3872 void r100_restore_sanity(struct radeon_device *rdev)
3873 {
3874 u32 tmp;
3875
3876 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3877 if (tmp) {
3878 WREG32(RADEON_CP_CSQ_CNTL, 0);
3879 }
3880 tmp = RREG32(RADEON_CP_RB_CNTL);
3881 if (tmp) {
3882 WREG32(RADEON_CP_RB_CNTL, 0);
3883 }
3884 tmp = RREG32(RADEON_SCRATCH_UMSK);
3885 if (tmp) {
3886 WREG32(RADEON_SCRATCH_UMSK, 0);
3887 }
3888 }
3889
3890 int r100_init(struct radeon_device *rdev)
3891 {
3892 int r;
3893
3894 /* Register debugfs file specific to this group of asics */
3895 r100_debugfs(rdev);
3896 /* Disable VGA */
3897 r100_vga_render_disable(rdev);
3898 /* Initialize scratch registers */
3899 radeon_scratch_init(rdev);
3900 /* Initialize surface registers */
3901 radeon_surface_init(rdev);
3902 /* sanity check some register to avoid hangs like after kexec */
3903 r100_restore_sanity(rdev);
3904 /* TODO: disable VGA need to use VGA request */
3905 /* BIOS*/
3906 if (!radeon_get_bios(rdev)) {
3907 if (ASIC_IS_AVIVO(rdev))
3908 return -EINVAL;
3909 }
3910 if (rdev->is_atom_bios) {
3911 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3912 return -EINVAL;
3913 } else {
3914 r = radeon_combios_init(rdev);
3915 if (r)
3916 return r;
3917 }
3918 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3919 if (radeon_asic_reset(rdev)) {
3920 dev_warn(rdev->dev,
3921 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3922 RREG32(R_000E40_RBBM_STATUS),
3923 RREG32(R_0007C0_CP_STAT));
3924 }
3925 /* check if cards are posted or not */
3926 if (radeon_boot_test_post_card(rdev) == false)
3927 return -EINVAL;
3928 /* Set asic errata */
3929 r100_errata(rdev);
3930 /* Initialize clocks */
3931 radeon_get_clock_info(rdev->ddev);
3932 /* initialize AGP */
3933 if (rdev->flags & RADEON_IS_AGP) {
3934 r = radeon_agp_init(rdev);
3935 if (r) {
3936 radeon_agp_disable(rdev);
3937 }
3938 }
3939 /* initialize VRAM */
3940 r100_mc_init(rdev);
3941 /* Fence driver */
3942 r = radeon_fence_driver_init(rdev);
3943 if (r)
3944 return r;
3945 r = radeon_irq_kms_init(rdev);
3946 if (r)
3947 return r;
3948 /* Memory manager */
3949 r = radeon_bo_init(rdev);
3950 if (r)
3951 return r;
3952 if (rdev->flags & RADEON_IS_PCI) {
3953 r = r100_pci_gart_init(rdev);
3954 if (r)
3955 return r;
3956 }
3957 r100_set_safe_registers(rdev);
3958 rdev->accel_working = true;
3959 r = r100_startup(rdev);
3960 if (r) {
3961 /* Somethings want wront with the accel init stop accel */
3962 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3963 r100_cp_fini(rdev);
3964 radeon_wb_fini(rdev);
3965 r100_ib_fini(rdev);
3966 radeon_irq_kms_fini(rdev);
3967 if (rdev->flags & RADEON_IS_PCI)
3968 r100_pci_gart_fini(rdev);
3969 rdev->accel_working = false;
3970 }
3971 return 0;
3972 }
Linux with added FPC-III support