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drm/radeon/kms: set DMA mask properly on newer PCI asics
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / r600.c
blob334aee6eab7ce03b4ed7cf9e151f4977755dce28
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
32 #include "drmP.h"
33 #include "radeon_drm.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "radeon_mode.h"
37 #include "r600d.h"
38 #include "atom.h"
39 #include "avivod.h"
40
41 #define PFP_UCODE_SIZE 576
42 #define PM4_UCODE_SIZE 1792
43 #define RLC_UCODE_SIZE 768
44 #define R700_PFP_UCODE_SIZE 848
45 #define R700_PM4_UCODE_SIZE 1360
46 #define R700_RLC_UCODE_SIZE 1024
47 #define EVERGREEN_PFP_UCODE_SIZE 1120
48 #define EVERGREEN_PM4_UCODE_SIZE 1376
49 #define EVERGREEN_RLC_UCODE_SIZE 768
50 #define CAYMAN_RLC_UCODE_SIZE 1024
51
52 /* Firmware Names */
53 MODULE_FIRMWARE("radeon/R600_pfp.bin");
54 MODULE_FIRMWARE("radeon/R600_me.bin");
55 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV610_me.bin");
57 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV630_me.bin");
59 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV620_me.bin");
61 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV635_me.bin");
63 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV670_me.bin");
65 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
66 MODULE_FIRMWARE("radeon/RS780_me.bin");
67 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
68 MODULE_FIRMWARE("radeon/RV770_me.bin");
69 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
70 MODULE_FIRMWARE("radeon/RV730_me.bin");
71 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
72 MODULE_FIRMWARE("radeon/RV710_me.bin");
73 MODULE_FIRMWARE("radeon/R600_rlc.bin");
74 MODULE_FIRMWARE("radeon/R700_rlc.bin");
75 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
76 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
77 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
78 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
79 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
80 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
81 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
82 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
83 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
84 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
85 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
86 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
87 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
88 MODULE_FIRMWARE("radeon/PALM_me.bin");
89 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
90 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
91 MODULE_FIRMWARE("radeon/SUMO_me.bin");
92 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
93 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
94
95 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
96
97 /* r600,rv610,rv630,rv620,rv635,rv670 */
98 int r600_mc_wait_for_idle(struct radeon_device *rdev);
99 void r600_gpu_init(struct radeon_device *rdev);
100 void r600_fini(struct radeon_device *rdev);
101 void r600_irq_disable(struct radeon_device *rdev);
102 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
103
104 /* get temperature in millidegrees */
105 int rv6xx_get_temp(struct radeon_device *rdev)
106 {
107 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
108 ASIC_T_SHIFT;
109 int actual_temp = temp & 0xff;
110
111 if (temp & 0x100)
112 actual_temp -= 256;
113
114 return actual_temp * 1000;
115 }
116
117 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
118 {
119 int i;
120
121 rdev->pm.dynpm_can_upclock = true;
122 rdev->pm.dynpm_can_downclock = true;
123
124 /* power state array is low to high, default is first */
125 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
126 int min_power_state_index = 0;
127
128 if (rdev->pm.num_power_states > 2)
129 min_power_state_index = 1;
130
131 switch (rdev->pm.dynpm_planned_action) {
132 case DYNPM_ACTION_MINIMUM:
133 rdev->pm.requested_power_state_index = min_power_state_index;
134 rdev->pm.requested_clock_mode_index = 0;
135 rdev->pm.dynpm_can_downclock = false;
136 break;
137 case DYNPM_ACTION_DOWNCLOCK:
138 if (rdev->pm.current_power_state_index == min_power_state_index) {
139 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
140 rdev->pm.dynpm_can_downclock = false;
141 } else {
142 if (rdev->pm.active_crtc_count > 1) {
143 for (i = 0; i < rdev->pm.num_power_states; i++) {
144 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
145 continue;
146 else if (i >= rdev->pm.current_power_state_index) {
147 rdev->pm.requested_power_state_index =
148 rdev->pm.current_power_state_index;
149 break;
150 } else {
151 rdev->pm.requested_power_state_index = i;
152 break;
153 }
154 }
155 } else {
156 if (rdev->pm.current_power_state_index == 0)
157 rdev->pm.requested_power_state_index =
158 rdev->pm.num_power_states - 1;
159 else
160 rdev->pm.requested_power_state_index =
161 rdev->pm.current_power_state_index - 1;
162 }
163 }
164 rdev->pm.requested_clock_mode_index = 0;
165 /* don't use the power state if crtcs are active and no display flag is set */
166 if ((rdev->pm.active_crtc_count > 0) &&
167 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
168 clock_info[rdev->pm.requested_clock_mode_index].flags &
169 RADEON_PM_MODE_NO_DISPLAY)) {
170 rdev->pm.requested_power_state_index++;
171 }
172 break;
173 case DYNPM_ACTION_UPCLOCK:
174 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
175 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
176 rdev->pm.dynpm_can_upclock = false;
177 } else {
178 if (rdev->pm.active_crtc_count > 1) {
179 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
180 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
181 continue;
182 else if (i <= rdev->pm.current_power_state_index) {
183 rdev->pm.requested_power_state_index =
184 rdev->pm.current_power_state_index;
185 break;
186 } else {
187 rdev->pm.requested_power_state_index = i;
188 break;
189 }
190 }
191 } else
192 rdev->pm.requested_power_state_index =
193 rdev->pm.current_power_state_index + 1;
194 }
195 rdev->pm.requested_clock_mode_index = 0;
196 break;
197 case DYNPM_ACTION_DEFAULT:
198 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
199 rdev->pm.requested_clock_mode_index = 0;
200 rdev->pm.dynpm_can_upclock = false;
201 break;
202 case DYNPM_ACTION_NONE:
203 default:
204 DRM_ERROR("Requested mode for not defined action\n");
205 return;
206 }
207 } else {
208 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
209 /* for now just select the first power state and switch between clock modes */
210 /* power state array is low to high, default is first (0) */
211 if (rdev->pm.active_crtc_count > 1) {
212 rdev->pm.requested_power_state_index = -1;
213 /* start at 1 as we don't want the default mode */
214 for (i = 1; i < rdev->pm.num_power_states; i++) {
215 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
216 continue;
217 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
218 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
219 rdev->pm.requested_power_state_index = i;
220 break;
221 }
222 }
223 /* if nothing selected, grab the default state. */
224 if (rdev->pm.requested_power_state_index == -1)
225 rdev->pm.requested_power_state_index = 0;
226 } else
227 rdev->pm.requested_power_state_index = 1;
228
229 switch (rdev->pm.dynpm_planned_action) {
230 case DYNPM_ACTION_MINIMUM:
231 rdev->pm.requested_clock_mode_index = 0;
232 rdev->pm.dynpm_can_downclock = false;
233 break;
234 case DYNPM_ACTION_DOWNCLOCK:
235 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
236 if (rdev->pm.current_clock_mode_index == 0) {
237 rdev->pm.requested_clock_mode_index = 0;
238 rdev->pm.dynpm_can_downclock = false;
239 } else
240 rdev->pm.requested_clock_mode_index =
241 rdev->pm.current_clock_mode_index - 1;
242 } else {
243 rdev->pm.requested_clock_mode_index = 0;
244 rdev->pm.dynpm_can_downclock = false;
245 }
246 /* don't use the power state if crtcs are active and no display flag is set */
247 if ((rdev->pm.active_crtc_count > 0) &&
248 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
249 clock_info[rdev->pm.requested_clock_mode_index].flags &
250 RADEON_PM_MODE_NO_DISPLAY)) {
251 rdev->pm.requested_clock_mode_index++;
252 }
253 break;
254 case DYNPM_ACTION_UPCLOCK:
255 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
256 if (rdev->pm.current_clock_mode_index ==
257 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
258 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
259 rdev->pm.dynpm_can_upclock = false;
260 } else
261 rdev->pm.requested_clock_mode_index =
262 rdev->pm.current_clock_mode_index + 1;
263 } else {
264 rdev->pm.requested_clock_mode_index =
265 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
266 rdev->pm.dynpm_can_upclock = false;
267 }
268 break;
269 case DYNPM_ACTION_DEFAULT:
270 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
271 rdev->pm.requested_clock_mode_index = 0;
272 rdev->pm.dynpm_can_upclock = false;
273 break;
274 case DYNPM_ACTION_NONE:
275 default:
276 DRM_ERROR("Requested mode for not defined action\n");
277 return;
278 }
279 }
280
281 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
282 rdev->pm.power_state[rdev->pm.requested_power_state_index].
283 clock_info[rdev->pm.requested_clock_mode_index].sclk,
284 rdev->pm.power_state[rdev->pm.requested_power_state_index].
285 clock_info[rdev->pm.requested_clock_mode_index].mclk,
286 rdev->pm.power_state[rdev->pm.requested_power_state_index].
287 pcie_lanes);
288 }
289
290 static int r600_pm_get_type_index(struct radeon_device *rdev,
291 enum radeon_pm_state_type ps_type,
292 int instance)
293 {
294 int i;
295 int found_instance = -1;
296
297 for (i = 0; i < rdev->pm.num_power_states; i++) {
298 if (rdev->pm.power_state[i].type == ps_type) {
299 found_instance++;
300 if (found_instance == instance)
301 return i;
302 }
303 }
304 /* return default if no match */
305 return rdev->pm.default_power_state_index;
306 }
307
308 void rs780_pm_init_profile(struct radeon_device *rdev)
309 {
310 if (rdev->pm.num_power_states == 2) {
311 /* default */
312 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
313 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
314 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
316 /* low sh */
317 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
321 /* mid sh */
322 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
326 /* high sh */
327 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
329 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
331 /* low mh */
332 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
336 /* mid mh */
337 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
341 /* high mh */
342 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
344 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
346 } else if (rdev->pm.num_power_states == 3) {
347 /* default */
348 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
349 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
350 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
351 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
352 /* low sh */
353 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
354 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
355 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
356 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
357 /* mid sh */
358 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
359 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
360 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
361 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
362 /* high sh */
363 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
364 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
365 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
366 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
367 /* low mh */
368 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
369 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
370 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
372 /* mid mh */
373 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
374 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
375 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
376 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
377 /* high mh */
378 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
379 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
380 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
381 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
382 } else {
383 /* default */
384 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
385 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
386 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
387 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
388 /* low sh */
389 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
390 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
391 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
392 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
393 /* mid sh */
394 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
395 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
396 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
397 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
398 /* high sh */
399 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
400 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
401 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
402 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
403 /* low mh */
404 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
405 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
406 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
407 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
408 /* mid mh */
409 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
410 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
411 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
412 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
413 /* high mh */
414 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
415 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
416 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
417 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
418 }
419 }
420
421 void r600_pm_init_profile(struct radeon_device *rdev)
422 {
423 if (rdev->family == CHIP_R600) {
424 /* XXX */
425 /* default */
426 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
427 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
429 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
430 /* low sh */
431 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
432 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
434 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
435 /* mid sh */
436 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
437 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
439 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
440 /* high sh */
441 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
442 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
444 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
445 /* low mh */
446 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
447 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
448 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
449 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
450 /* mid mh */
451 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
452 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
453 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
454 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
455 /* high mh */
456 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
457 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
458 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
459 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
460 } else {
461 if (rdev->pm.num_power_states < 4) {
462 /* default */
463 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
464 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
465 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
466 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
467 /* low sh */
468 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
469 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
470 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
471 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
472 /* mid sh */
473 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
474 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
475 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
476 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
477 /* high sh */
478 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
479 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
480 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
481 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
482 /* low mh */
483 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
484 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
485 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
486 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
487 /* low mh */
488 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
489 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
490 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
491 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
492 /* high mh */
493 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
494 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
495 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
496 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
497 } else {
498 /* default */
499 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
500 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
501 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
502 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
503 /* low sh */
504 if (rdev->flags & RADEON_IS_MOBILITY) {
505 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
506 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
507 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
508 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
509 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
510 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
511 } else {
512 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
513 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
514 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
515 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
516 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
517 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
518 }
519 /* mid sh */
520 if (rdev->flags & RADEON_IS_MOBILITY) {
521 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
522 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
523 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
524 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
525 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
526 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
527 } else {
528 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
529 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
530 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
531 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
532 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
533 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
534 }
535 /* high sh */
536 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
537 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
538 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
539 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
540 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
541 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
542 /* low mh */
543 if (rdev->flags & RADEON_IS_MOBILITY) {
544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
545 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
546 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
547 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
548 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
549 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
550 } else {
551 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
552 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
553 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
554 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
555 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
556 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
557 }
558 /* mid mh */
559 if (rdev->flags & RADEON_IS_MOBILITY) {
560 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
561 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
562 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
563 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
564 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
566 } else {
567 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
568 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
569 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
570 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
571 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
572 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
573 }
574 /* high mh */
575 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
576 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
577 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
578 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
579 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
580 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
581 }
582 }
583 }
584
585 void r600_pm_misc(struct radeon_device *rdev)
586 {
587 int req_ps_idx = rdev->pm.requested_power_state_index;
588 int req_cm_idx = rdev->pm.requested_clock_mode_index;
589 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
590 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
591
592 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
593 /* 0xff01 is a flag rather then an actual voltage */
594 if (voltage->voltage == 0xff01)
595 return;
596 if (voltage->voltage != rdev->pm.current_vddc) {
597 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
598 rdev->pm.current_vddc = voltage->voltage;
599 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
600 }
601 }
602 }
603
604 bool r600_gui_idle(struct radeon_device *rdev)
605 {
606 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
607 return false;
608 else
609 return true;
610 }
611
612 /* hpd for digital panel detect/disconnect */
613 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
614 {
615 bool connected = false;
616
617 if (ASIC_IS_DCE3(rdev)) {
618 switch (hpd) {
619 case RADEON_HPD_1:
620 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
621 connected = true;
622 break;
623 case RADEON_HPD_2:
624 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
625 connected = true;
626 break;
627 case RADEON_HPD_3:
628 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
629 connected = true;
630 break;
631 case RADEON_HPD_4:
632 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
633 connected = true;
634 break;
635 /* DCE 3.2 */
636 case RADEON_HPD_5:
637 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
638 connected = true;
639 break;
640 case RADEON_HPD_6:
641 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
642 connected = true;
643 break;
644 default:
645 break;
646 }
647 } else {
648 switch (hpd) {
649 case RADEON_HPD_1:
650 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
651 connected = true;
652 break;
653 case RADEON_HPD_2:
654 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
655 connected = true;
656 break;
657 case RADEON_HPD_3:
658 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
659 connected = true;
660 break;
661 default:
662 break;
663 }
664 }
665 return connected;
666 }
667
668 void r600_hpd_set_polarity(struct radeon_device *rdev,
669 enum radeon_hpd_id hpd)
670 {
671 u32 tmp;
672 bool connected = r600_hpd_sense(rdev, hpd);
673
674 if (ASIC_IS_DCE3(rdev)) {
675 switch (hpd) {
676 case RADEON_HPD_1:
677 tmp = RREG32(DC_HPD1_INT_CONTROL);
678 if (connected)
679 tmp &= ~DC_HPDx_INT_POLARITY;
680 else
681 tmp |= DC_HPDx_INT_POLARITY;
682 WREG32(DC_HPD1_INT_CONTROL, tmp);
683 break;
684 case RADEON_HPD_2:
685 tmp = RREG32(DC_HPD2_INT_CONTROL);
686 if (connected)
687 tmp &= ~DC_HPDx_INT_POLARITY;
688 else
689 tmp |= DC_HPDx_INT_POLARITY;
690 WREG32(DC_HPD2_INT_CONTROL, tmp);
691 break;
692 case RADEON_HPD_3:
693 tmp = RREG32(DC_HPD3_INT_CONTROL);
694 if (connected)
695 tmp &= ~DC_HPDx_INT_POLARITY;
696 else
697 tmp |= DC_HPDx_INT_POLARITY;
698 WREG32(DC_HPD3_INT_CONTROL, tmp);
699 break;
700 case RADEON_HPD_4:
701 tmp = RREG32(DC_HPD4_INT_CONTROL);
702 if (connected)
703 tmp &= ~DC_HPDx_INT_POLARITY;
704 else
705 tmp |= DC_HPDx_INT_POLARITY;
706 WREG32(DC_HPD4_INT_CONTROL, tmp);
707 break;
708 case RADEON_HPD_5:
709 tmp = RREG32(DC_HPD5_INT_CONTROL);
710 if (connected)
711 tmp &= ~DC_HPDx_INT_POLARITY;
712 else
713 tmp |= DC_HPDx_INT_POLARITY;
714 WREG32(DC_HPD5_INT_CONTROL, tmp);
715 break;
716 /* DCE 3.2 */
717 case RADEON_HPD_6:
718 tmp = RREG32(DC_HPD6_INT_CONTROL);
719 if (connected)
720 tmp &= ~DC_HPDx_INT_POLARITY;
721 else
722 tmp |= DC_HPDx_INT_POLARITY;
723 WREG32(DC_HPD6_INT_CONTROL, tmp);
724 break;
725 default:
726 break;
727 }
728 } else {
729 switch (hpd) {
730 case RADEON_HPD_1:
731 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
732 if (connected)
733 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
734 else
735 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
736 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
737 break;
738 case RADEON_HPD_2:
739 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
740 if (connected)
741 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
742 else
743 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
744 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
745 break;
746 case RADEON_HPD_3:
747 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
748 if (connected)
749 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
750 else
751 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
752 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
753 break;
754 default:
755 break;
756 }
757 }
758 }
759
760 void r600_hpd_init(struct radeon_device *rdev)
761 {
762 struct drm_device *dev = rdev->ddev;
763 struct drm_connector *connector;
764
765 if (ASIC_IS_DCE3(rdev)) {
766 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
767 if (ASIC_IS_DCE32(rdev))
768 tmp |= DC_HPDx_EN;
769
770 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
771 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
772 switch (radeon_connector->hpd.hpd) {
773 case RADEON_HPD_1:
774 WREG32(DC_HPD1_CONTROL, tmp);
775 rdev->irq.hpd[0] = true;
776 break;
777 case RADEON_HPD_2:
778 WREG32(DC_HPD2_CONTROL, tmp);
779 rdev->irq.hpd[1] = true;
780 break;
781 case RADEON_HPD_3:
782 WREG32(DC_HPD3_CONTROL, tmp);
783 rdev->irq.hpd[2] = true;
784 break;
785 case RADEON_HPD_4:
786 WREG32(DC_HPD4_CONTROL, tmp);
787 rdev->irq.hpd[3] = true;
788 break;
789 /* DCE 3.2 */
790 case RADEON_HPD_5:
791 WREG32(DC_HPD5_CONTROL, tmp);
792 rdev->irq.hpd[4] = true;
793 break;
794 case RADEON_HPD_6:
795 WREG32(DC_HPD6_CONTROL, tmp);
796 rdev->irq.hpd[5] = true;
797 break;
798 default:
799 break;
800 }
801 }
802 } else {
803 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
804 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
805 switch (radeon_connector->hpd.hpd) {
806 case RADEON_HPD_1:
807 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
808 rdev->irq.hpd[0] = true;
809 break;
810 case RADEON_HPD_2:
811 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
812 rdev->irq.hpd[1] = true;
813 break;
814 case RADEON_HPD_3:
815 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
816 rdev->irq.hpd[2] = true;
817 break;
818 default:
819 break;
820 }
821 }
822 }
823 if (rdev->irq.installed)
824 r600_irq_set(rdev);
825 }
826
827 void r600_hpd_fini(struct radeon_device *rdev)
828 {
829 struct drm_device *dev = rdev->ddev;
830 struct drm_connector *connector;
831
832 if (ASIC_IS_DCE3(rdev)) {
833 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
834 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
835 switch (radeon_connector->hpd.hpd) {
836 case RADEON_HPD_1:
837 WREG32(DC_HPD1_CONTROL, 0);
838 rdev->irq.hpd[0] = false;
839 break;
840 case RADEON_HPD_2:
841 WREG32(DC_HPD2_CONTROL, 0);
842 rdev->irq.hpd[1] = false;
843 break;
844 case RADEON_HPD_3:
845 WREG32(DC_HPD3_CONTROL, 0);
846 rdev->irq.hpd[2] = false;
847 break;
848 case RADEON_HPD_4:
849 WREG32(DC_HPD4_CONTROL, 0);
850 rdev->irq.hpd[3] = false;
851 break;
852 /* DCE 3.2 */
853 case RADEON_HPD_5:
854 WREG32(DC_HPD5_CONTROL, 0);
855 rdev->irq.hpd[4] = false;
856 break;
857 case RADEON_HPD_6:
858 WREG32(DC_HPD6_CONTROL, 0);
859 rdev->irq.hpd[5] = false;
860 break;
861 default:
862 break;
863 }
864 }
865 } else {
866 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
867 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
868 switch (radeon_connector->hpd.hpd) {
869 case RADEON_HPD_1:
870 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
871 rdev->irq.hpd[0] = false;
872 break;
873 case RADEON_HPD_2:
874 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
875 rdev->irq.hpd[1] = false;
876 break;
877 case RADEON_HPD_3:
878 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
879 rdev->irq.hpd[2] = false;
880 break;
881 default:
882 break;
883 }
884 }
885 }
886 }
887
888 /*
889 * R600 PCIE GART
890 */
891 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
892 {
893 unsigned i;
894 u32 tmp;
895
896 /* flush hdp cache so updates hit vram */
897 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
898 !(rdev->flags & RADEON_IS_AGP)) {
899 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
900 u32 tmp;
901
902 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
903 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
904 * This seems to cause problems on some AGP cards. Just use the old
905 * method for them.
906 */
907 WREG32(HDP_DEBUG1, 0);
908 tmp = readl((void __iomem *)ptr);
909 } else
910 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
911
912 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
913 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
914 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
915 for (i = 0; i < rdev->usec_timeout; i++) {
916 /* read MC_STATUS */
917 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
918 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
919 if (tmp == 2) {
920 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
921 return;
922 }
923 if (tmp) {
924 return;
925 }
926 udelay(1);
927 }
928 }
929
930 int r600_pcie_gart_init(struct radeon_device *rdev)
931 {
932 int r;
933
934 if (rdev->gart.table.vram.robj) {
935 WARN(1, "R600 PCIE GART already initialized\n");
936 return 0;
937 }
938 /* Initialize common gart structure */
939 r = radeon_gart_init(rdev);
940 if (r)
941 return r;
942 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
943 return radeon_gart_table_vram_alloc(rdev);
944 }
945
946 int r600_pcie_gart_enable(struct radeon_device *rdev)
947 {
948 u32 tmp;
949 int r, i;
950
951 if (rdev->gart.table.vram.robj == NULL) {
952 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
953 return -EINVAL;
954 }
955 r = radeon_gart_table_vram_pin(rdev);
956 if (r)
957 return r;
958 radeon_gart_restore(rdev);
959
960 /* Setup L2 cache */
961 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
962 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
963 EFFECTIVE_L2_QUEUE_SIZE(7));
964 WREG32(VM_L2_CNTL2, 0);
965 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
966 /* Setup TLB control */
967 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
968 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
969 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
970 ENABLE_WAIT_L2_QUERY;
971 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
972 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
973 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
974 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
975 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
976 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
977 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
978 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
979 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
980 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
981 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
982 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
983 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
984 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
985 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
986 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
987 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
988 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
989 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
990 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
991 (u32)(rdev->dummy_page.addr >> 12));
992 for (i = 1; i < 7; i++)
993 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
994
995 r600_pcie_gart_tlb_flush(rdev);
996 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
997 (unsigned)(rdev->mc.gtt_size >> 20),
998 (unsigned long long)rdev->gart.table_addr);
999 rdev->gart.ready = true;
1000 return 0;
1001 }
1002
1003 void r600_pcie_gart_disable(struct radeon_device *rdev)
1004 {
1005 u32 tmp;
1006 int i, r;
1007
1008 /* Disable all tables */
1009 for (i = 0; i < 7; i++)
1010 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1011
1012 /* Disable L2 cache */
1013 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1014 EFFECTIVE_L2_QUEUE_SIZE(7));
1015 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1016 /* Setup L1 TLB control */
1017 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1018 ENABLE_WAIT_L2_QUERY;
1019 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1020 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1021 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1022 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1023 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1024 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1025 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1026 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1027 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1028 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1029 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1030 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1031 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1032 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1033 if (rdev->gart.table.vram.robj) {
1034 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1035 if (likely(r == 0)) {
1036 radeon_bo_kunmap(rdev->gart.table.vram.robj);
1037 radeon_bo_unpin(rdev->gart.table.vram.robj);
1038 radeon_bo_unreserve(rdev->gart.table.vram.robj);
1039 }
1040 }
1041 }
1042
1043 void r600_pcie_gart_fini(struct radeon_device *rdev)
1044 {
1045 radeon_gart_fini(rdev);
1046 r600_pcie_gart_disable(rdev);
1047 radeon_gart_table_vram_free(rdev);
1048 }
1049
1050 void r600_agp_enable(struct radeon_device *rdev)
1051 {
1052 u32 tmp;
1053 int i;
1054
1055 /* Setup L2 cache */
1056 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1057 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1058 EFFECTIVE_L2_QUEUE_SIZE(7));
1059 WREG32(VM_L2_CNTL2, 0);
1060 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1061 /* Setup TLB control */
1062 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1063 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1064 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1065 ENABLE_WAIT_L2_QUERY;
1066 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1067 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1068 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1069 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1070 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1071 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1072 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1073 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1074 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1075 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1076 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1077 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1078 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1079 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1080 for (i = 0; i < 7; i++)
1081 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1082 }
1083
1084 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1085 {
1086 unsigned i;
1087 u32 tmp;
1088
1089 for (i = 0; i < rdev->usec_timeout; i++) {
1090 /* read MC_STATUS */
1091 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1092 if (!tmp)
1093 return 0;
1094 udelay(1);
1095 }
1096 return -1;
1097 }
1098
1099 static void r600_mc_program(struct radeon_device *rdev)
1100 {
1101 struct rv515_mc_save save;
1102 u32 tmp;
1103 int i, j;
1104
1105 /* Initialize HDP */
1106 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1107 WREG32((0x2c14 + j), 0x00000000);
1108 WREG32((0x2c18 + j), 0x00000000);
1109 WREG32((0x2c1c + j), 0x00000000);
1110 WREG32((0x2c20 + j), 0x00000000);
1111 WREG32((0x2c24 + j), 0x00000000);
1112 }
1113 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1114
1115 rv515_mc_stop(rdev, &save);
1116 if (r600_mc_wait_for_idle(rdev)) {
1117 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1118 }
1119 /* Lockout access through VGA aperture (doesn't exist before R600) */
1120 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1121 /* Update configuration */
1122 if (rdev->flags & RADEON_IS_AGP) {
1123 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1124 /* VRAM before AGP */
1125 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1126 rdev->mc.vram_start >> 12);
1127 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1128 rdev->mc.gtt_end >> 12);
1129 } else {
1130 /* VRAM after AGP */
1131 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1132 rdev->mc.gtt_start >> 12);
1133 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1134 rdev->mc.vram_end >> 12);
1135 }
1136 } else {
1137 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1138 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1139 }
1140 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1141 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1142 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1143 WREG32(MC_VM_FB_LOCATION, tmp);
1144 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1145 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1146 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1147 if (rdev->flags & RADEON_IS_AGP) {
1148 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1149 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1150 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1151 } else {
1152 WREG32(MC_VM_AGP_BASE, 0);
1153 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1154 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1155 }
1156 if (r600_mc_wait_for_idle(rdev)) {
1157 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1158 }
1159 rv515_mc_resume(rdev, &save);
1160 /* we need to own VRAM, so turn off the VGA renderer here
1161 * to stop it overwriting our objects */
1162 rv515_vga_render_disable(rdev);
1163 }
1164
1165 /**
1166 * r600_vram_gtt_location - try to find VRAM & GTT location
1167 * @rdev: radeon device structure holding all necessary informations
1168 * @mc: memory controller structure holding memory informations
1169 *
1170 * Function will place try to place VRAM at same place as in CPU (PCI)
1171 * address space as some GPU seems to have issue when we reprogram at
1172 * different address space.
1173 *
1174 * If there is not enough space to fit the unvisible VRAM after the
1175 * aperture then we limit the VRAM size to the aperture.
1176 *
1177 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1178 * them to be in one from GPU point of view so that we can program GPU to
1179 * catch access outside them (weird GPU policy see ??).
1180 *
1181 * This function will never fails, worst case are limiting VRAM or GTT.
1182 *
1183 * Note: GTT start, end, size should be initialized before calling this
1184 * function on AGP platform.
1185 */
1186 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1187 {
1188 u64 size_bf, size_af;
1189
1190 if (mc->mc_vram_size > 0xE0000000) {
1191 /* leave room for at least 512M GTT */
1192 dev_warn(rdev->dev, "limiting VRAM\n");
1193 mc->real_vram_size = 0xE0000000;
1194 mc->mc_vram_size = 0xE0000000;
1195 }
1196 if (rdev->flags & RADEON_IS_AGP) {
1197 size_bf = mc->gtt_start;
1198 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1199 if (size_bf > size_af) {
1200 if (mc->mc_vram_size > size_bf) {
1201 dev_warn(rdev->dev, "limiting VRAM\n");
1202 mc->real_vram_size = size_bf;
1203 mc->mc_vram_size = size_bf;
1204 }
1205 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1206 } else {
1207 if (mc->mc_vram_size > size_af) {
1208 dev_warn(rdev->dev, "limiting VRAM\n");
1209 mc->real_vram_size = size_af;
1210 mc->mc_vram_size = size_af;
1211 }
1212 mc->vram_start = mc->gtt_end;
1213 }
1214 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1215 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1216 mc->mc_vram_size >> 20, mc->vram_start,
1217 mc->vram_end, mc->real_vram_size >> 20);
1218 } else {
1219 u64 base = 0;
1220 if (rdev->flags & RADEON_IS_IGP) {
1221 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1222 base <<= 24;
1223 }
1224 radeon_vram_location(rdev, &rdev->mc, base);
1225 rdev->mc.gtt_base_align = 0;
1226 radeon_gtt_location(rdev, mc);
1227 }
1228 }
1229
1230 int r600_mc_init(struct radeon_device *rdev)
1231 {
1232 u32 tmp;
1233 int chansize, numchan;
1234
1235 /* Get VRAM informations */
1236 rdev->mc.vram_is_ddr = true;
1237 tmp = RREG32(RAMCFG);
1238 if (tmp & CHANSIZE_OVERRIDE) {
1239 chansize = 16;
1240 } else if (tmp & CHANSIZE_MASK) {
1241 chansize = 64;
1242 } else {
1243 chansize = 32;
1244 }
1245 tmp = RREG32(CHMAP);
1246 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1247 case 0:
1248 default:
1249 numchan = 1;
1250 break;
1251 case 1:
1252 numchan = 2;
1253 break;
1254 case 2:
1255 numchan = 4;
1256 break;
1257 case 3:
1258 numchan = 8;
1259 break;
1260 }
1261 rdev->mc.vram_width = numchan * chansize;
1262 /* Could aper size report 0 ? */
1263 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1264 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1265 /* Setup GPU memory space */
1266 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1267 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1268 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1269 r600_vram_gtt_location(rdev, &rdev->mc);
1270
1271 if (rdev->flags & RADEON_IS_IGP) {
1272 rs690_pm_info(rdev);
1273 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1274 }
1275 radeon_update_bandwidth_info(rdev);
1276 return 0;
1277 }
1278
1279 /* We doesn't check that the GPU really needs a reset we simply do the
1280 * reset, it's up to the caller to determine if the GPU needs one. We
1281 * might add an helper function to check that.
1282 */
1283 int r600_gpu_soft_reset(struct radeon_device *rdev)
1284 {
1285 struct rv515_mc_save save;
1286 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1287 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1288 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1289 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1290 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1291 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1292 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1293 S_008010_GUI_ACTIVE(1);
1294 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1295 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1296 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1297 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1298 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1299 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1300 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1301 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1302 u32 tmp;
1303
1304 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1305 return 0;
1306
1307 dev_info(rdev->dev, "GPU softreset \n");
1308 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1309 RREG32(R_008010_GRBM_STATUS));
1310 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1311 RREG32(R_008014_GRBM_STATUS2));
1312 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1313 RREG32(R_000E50_SRBM_STATUS));
1314 rv515_mc_stop(rdev, &save);
1315 if (r600_mc_wait_for_idle(rdev)) {
1316 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1317 }
1318 /* Disable CP parsing/prefetching */
1319 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1320 /* Check if any of the rendering block is busy and reset it */
1321 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1322 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1323 tmp = S_008020_SOFT_RESET_CR(1) |
1324 S_008020_SOFT_RESET_DB(1) |
1325 S_008020_SOFT_RESET_CB(1) |
1326 S_008020_SOFT_RESET_PA(1) |
1327 S_008020_SOFT_RESET_SC(1) |
1328 S_008020_SOFT_RESET_SMX(1) |
1329 S_008020_SOFT_RESET_SPI(1) |
1330 S_008020_SOFT_RESET_SX(1) |
1331 S_008020_SOFT_RESET_SH(1) |
1332 S_008020_SOFT_RESET_TC(1) |
1333 S_008020_SOFT_RESET_TA(1) |
1334 S_008020_SOFT_RESET_VC(1) |
1335 S_008020_SOFT_RESET_VGT(1);
1336 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1337 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1338 RREG32(R_008020_GRBM_SOFT_RESET);
1339 mdelay(15);
1340 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1341 }
1342 /* Reset CP (we always reset CP) */
1343 tmp = S_008020_SOFT_RESET_CP(1);
1344 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1345 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1346 RREG32(R_008020_GRBM_SOFT_RESET);
1347 mdelay(15);
1348 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1349 /* Wait a little for things to settle down */
1350 mdelay(1);
1351 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1352 RREG32(R_008010_GRBM_STATUS));
1353 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1354 RREG32(R_008014_GRBM_STATUS2));
1355 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1356 RREG32(R_000E50_SRBM_STATUS));
1357 rv515_mc_resume(rdev, &save);
1358 return 0;
1359 }
1360
1361 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1362 {
1363 u32 srbm_status;
1364 u32 grbm_status;
1365 u32 grbm_status2;
1366 struct r100_gpu_lockup *lockup;
1367 int r;
1368
1369 if (rdev->family >= CHIP_RV770)
1370 lockup = &rdev->config.rv770.lockup;
1371 else
1372 lockup = &rdev->config.r600.lockup;
1373
1374 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1375 grbm_status = RREG32(R_008010_GRBM_STATUS);
1376 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1377 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1378 r100_gpu_lockup_update(lockup, &rdev->cp);
1379 return false;
1380 }
1381 /* force CP activities */
1382 r = radeon_ring_lock(rdev, 2);
1383 if (!r) {
1384 /* PACKET2 NOP */
1385 radeon_ring_write(rdev, 0x80000000);
1386 radeon_ring_write(rdev, 0x80000000);
1387 radeon_ring_unlock_commit(rdev);
1388 }
1389 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1390 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1391 }
1392
1393 int r600_asic_reset(struct radeon_device *rdev)
1394 {
1395 return r600_gpu_soft_reset(rdev);
1396 }
1397
1398 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1399 u32 num_backends,
1400 u32 backend_disable_mask)
1401 {
1402 u32 backend_map = 0;
1403 u32 enabled_backends_mask;
1404 u32 enabled_backends_count;
1405 u32 cur_pipe;
1406 u32 swizzle_pipe[R6XX_MAX_PIPES];
1407 u32 cur_backend;
1408 u32 i;
1409
1410 if (num_tile_pipes > R6XX_MAX_PIPES)
1411 num_tile_pipes = R6XX_MAX_PIPES;
1412 if (num_tile_pipes < 1)
1413 num_tile_pipes = 1;
1414 if (num_backends > R6XX_MAX_BACKENDS)
1415 num_backends = R6XX_MAX_BACKENDS;
1416 if (num_backends < 1)
1417 num_backends = 1;
1418
1419 enabled_backends_mask = 0;
1420 enabled_backends_count = 0;
1421 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1422 if (((backend_disable_mask >> i) & 1) == 0) {
1423 enabled_backends_mask |= (1 << i);
1424 ++enabled_backends_count;
1425 }
1426 if (enabled_backends_count == num_backends)
1427 break;
1428 }
1429
1430 if (enabled_backends_count == 0) {
1431 enabled_backends_mask = 1;
1432 enabled_backends_count = 1;
1433 }
1434
1435 if (enabled_backends_count != num_backends)
1436 num_backends = enabled_backends_count;
1437
1438 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1439 switch (num_tile_pipes) {
1440 case 1:
1441 swizzle_pipe[0] = 0;
1442 break;
1443 case 2:
1444 swizzle_pipe[0] = 0;
1445 swizzle_pipe[1] = 1;
1446 break;
1447 case 3:
1448 swizzle_pipe[0] = 0;
1449 swizzle_pipe[1] = 1;
1450 swizzle_pipe[2] = 2;
1451 break;
1452 case 4:
1453 swizzle_pipe[0] = 0;
1454 swizzle_pipe[1] = 1;
1455 swizzle_pipe[2] = 2;
1456 swizzle_pipe[3] = 3;
1457 break;
1458 case 5:
1459 swizzle_pipe[0] = 0;
1460 swizzle_pipe[1] = 1;
1461 swizzle_pipe[2] = 2;
1462 swizzle_pipe[3] = 3;
1463 swizzle_pipe[4] = 4;
1464 break;
1465 case 6:
1466 swizzle_pipe[0] = 0;
1467 swizzle_pipe[1] = 2;
1468 swizzle_pipe[2] = 4;
1469 swizzle_pipe[3] = 5;
1470 swizzle_pipe[4] = 1;
1471 swizzle_pipe[5] = 3;
1472 break;
1473 case 7:
1474 swizzle_pipe[0] = 0;
1475 swizzle_pipe[1] = 2;
1476 swizzle_pipe[2] = 4;
1477 swizzle_pipe[3] = 6;
1478 swizzle_pipe[4] = 1;
1479 swizzle_pipe[5] = 3;
1480 swizzle_pipe[6] = 5;
1481 break;
1482 case 8:
1483 swizzle_pipe[0] = 0;
1484 swizzle_pipe[1] = 2;
1485 swizzle_pipe[2] = 4;
1486 swizzle_pipe[3] = 6;
1487 swizzle_pipe[4] = 1;
1488 swizzle_pipe[5] = 3;
1489 swizzle_pipe[6] = 5;
1490 swizzle_pipe[7] = 7;
1491 break;
1492 }
1493
1494 cur_backend = 0;
1495 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1496 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1497 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1498
1499 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1500
1501 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1502 }
1503
1504 return backend_map;
1505 }
1506
1507 int r600_count_pipe_bits(uint32_t val)
1508 {
1509 int i, ret = 0;
1510
1511 for (i = 0; i < 32; i++) {
1512 ret += val & 1;
1513 val >>= 1;
1514 }
1515 return ret;
1516 }
1517
1518 void r600_gpu_init(struct radeon_device *rdev)
1519 {
1520 u32 tiling_config;
1521 u32 ramcfg;
1522 u32 backend_map;
1523 u32 cc_rb_backend_disable;
1524 u32 cc_gc_shader_pipe_config;
1525 u32 tmp;
1526 int i, j;
1527 u32 sq_config;
1528 u32 sq_gpr_resource_mgmt_1 = 0;
1529 u32 sq_gpr_resource_mgmt_2 = 0;
1530 u32 sq_thread_resource_mgmt = 0;
1531 u32 sq_stack_resource_mgmt_1 = 0;
1532 u32 sq_stack_resource_mgmt_2 = 0;
1533
1534 /* FIXME: implement */
1535 switch (rdev->family) {
1536 case CHIP_R600:
1537 rdev->config.r600.max_pipes = 4;
1538 rdev->config.r600.max_tile_pipes = 8;
1539 rdev->config.r600.max_simds = 4;
1540 rdev->config.r600.max_backends = 4;
1541 rdev->config.r600.max_gprs = 256;
1542 rdev->config.r600.max_threads = 192;
1543 rdev->config.r600.max_stack_entries = 256;
1544 rdev->config.r600.max_hw_contexts = 8;
1545 rdev->config.r600.max_gs_threads = 16;
1546 rdev->config.r600.sx_max_export_size = 128;
1547 rdev->config.r600.sx_max_export_pos_size = 16;
1548 rdev->config.r600.sx_max_export_smx_size = 128;
1549 rdev->config.r600.sq_num_cf_insts = 2;
1550 break;
1551 case CHIP_RV630:
1552 case CHIP_RV635:
1553 rdev->config.r600.max_pipes = 2;
1554 rdev->config.r600.max_tile_pipes = 2;
1555 rdev->config.r600.max_simds = 3;
1556 rdev->config.r600.max_backends = 1;
1557 rdev->config.r600.max_gprs = 128;
1558 rdev->config.r600.max_threads = 192;
1559 rdev->config.r600.max_stack_entries = 128;
1560 rdev->config.r600.max_hw_contexts = 8;
1561 rdev->config.r600.max_gs_threads = 4;
1562 rdev->config.r600.sx_max_export_size = 128;
1563 rdev->config.r600.sx_max_export_pos_size = 16;
1564 rdev->config.r600.sx_max_export_smx_size = 128;
1565 rdev->config.r600.sq_num_cf_insts = 2;
1566 break;
1567 case CHIP_RV610:
1568 case CHIP_RV620:
1569 case CHIP_RS780:
1570 case CHIP_RS880:
1571 rdev->config.r600.max_pipes = 1;
1572 rdev->config.r600.max_tile_pipes = 1;
1573 rdev->config.r600.max_simds = 2;
1574 rdev->config.r600.max_backends = 1;
1575 rdev->config.r600.max_gprs = 128;
1576 rdev->config.r600.max_threads = 192;
1577 rdev->config.r600.max_stack_entries = 128;
1578 rdev->config.r600.max_hw_contexts = 4;
1579 rdev->config.r600.max_gs_threads = 4;
1580 rdev->config.r600.sx_max_export_size = 128;
1581 rdev->config.r600.sx_max_export_pos_size = 16;
1582 rdev->config.r600.sx_max_export_smx_size = 128;
1583 rdev->config.r600.sq_num_cf_insts = 1;
1584 break;
1585 case CHIP_RV670:
1586 rdev->config.r600.max_pipes = 4;
1587 rdev->config.r600.max_tile_pipes = 4;
1588 rdev->config.r600.max_simds = 4;
1589 rdev->config.r600.max_backends = 4;
1590 rdev->config.r600.max_gprs = 192;
1591 rdev->config.r600.max_threads = 192;
1592 rdev->config.r600.max_stack_entries = 256;
1593 rdev->config.r600.max_hw_contexts = 8;
1594 rdev->config.r600.max_gs_threads = 16;
1595 rdev->config.r600.sx_max_export_size = 128;
1596 rdev->config.r600.sx_max_export_pos_size = 16;
1597 rdev->config.r600.sx_max_export_smx_size = 128;
1598 rdev->config.r600.sq_num_cf_insts = 2;
1599 break;
1600 default:
1601 break;
1602 }
1603
1604 /* Initialize HDP */
1605 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1606 WREG32((0x2c14 + j), 0x00000000);
1607 WREG32((0x2c18 + j), 0x00000000);
1608 WREG32((0x2c1c + j), 0x00000000);
1609 WREG32((0x2c20 + j), 0x00000000);
1610 WREG32((0x2c24 + j), 0x00000000);
1611 }
1612
1613 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1614
1615 /* Setup tiling */
1616 tiling_config = 0;
1617 ramcfg = RREG32(RAMCFG);
1618 switch (rdev->config.r600.max_tile_pipes) {
1619 case 1:
1620 tiling_config |= PIPE_TILING(0);
1621 break;
1622 case 2:
1623 tiling_config |= PIPE_TILING(1);
1624 break;
1625 case 4:
1626 tiling_config |= PIPE_TILING(2);
1627 break;
1628 case 8:
1629 tiling_config |= PIPE_TILING(3);
1630 break;
1631 default:
1632 break;
1633 }
1634 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1635 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1636 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1637 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1638 if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1639 rdev->config.r600.tiling_group_size = 512;
1640 else
1641 rdev->config.r600.tiling_group_size = 256;
1642 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1643 if (tmp > 3) {
1644 tiling_config |= ROW_TILING(3);
1645 tiling_config |= SAMPLE_SPLIT(3);
1646 } else {
1647 tiling_config |= ROW_TILING(tmp);
1648 tiling_config |= SAMPLE_SPLIT(tmp);
1649 }
1650 tiling_config |= BANK_SWAPS(1);
1651
1652 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1653 cc_rb_backend_disable |=
1654 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1655
1656 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1657 cc_gc_shader_pipe_config |=
1658 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1659 cc_gc_shader_pipe_config |=
1660 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1661
1662 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1663 (R6XX_MAX_BACKENDS -
1664 r600_count_pipe_bits((cc_rb_backend_disable &
1665 R6XX_MAX_BACKENDS_MASK) >> 16)),
1666 (cc_rb_backend_disable >> 16));
1667 rdev->config.r600.tile_config = tiling_config;
1668 rdev->config.r600.backend_map = backend_map;
1669 tiling_config |= BACKEND_MAP(backend_map);
1670 WREG32(GB_TILING_CONFIG, tiling_config);
1671 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1672 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1673
1674 /* Setup pipes */
1675 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1676 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1677 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1678
1679 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1680 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1681 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1682
1683 /* Setup some CP states */
1684 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1685 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1686
1687 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1688 SYNC_WALKER | SYNC_ALIGNER));
1689 /* Setup various GPU states */
1690 if (rdev->family == CHIP_RV670)
1691 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1692
1693 tmp = RREG32(SX_DEBUG_1);
1694 tmp |= SMX_EVENT_RELEASE;
1695 if ((rdev->family > CHIP_R600))
1696 tmp |= ENABLE_NEW_SMX_ADDRESS;
1697 WREG32(SX_DEBUG_1, tmp);
1698
1699 if (((rdev->family) == CHIP_R600) ||
1700 ((rdev->family) == CHIP_RV630) ||
1701 ((rdev->family) == CHIP_RV610) ||
1702 ((rdev->family) == CHIP_RV620) ||
1703 ((rdev->family) == CHIP_RS780) ||
1704 ((rdev->family) == CHIP_RS880)) {
1705 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1706 } else {
1707 WREG32(DB_DEBUG, 0);
1708 }
1709 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1710 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1711
1712 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1713 WREG32(VGT_NUM_INSTANCES, 0);
1714
1715 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1716 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1717
1718 tmp = RREG32(SQ_MS_FIFO_SIZES);
1719 if (((rdev->family) == CHIP_RV610) ||
1720 ((rdev->family) == CHIP_RV620) ||
1721 ((rdev->family) == CHIP_RS780) ||
1722 ((rdev->family) == CHIP_RS880)) {
1723 tmp = (CACHE_FIFO_SIZE(0xa) |
1724 FETCH_FIFO_HIWATER(0xa) |
1725 DONE_FIFO_HIWATER(0xe0) |
1726 ALU_UPDATE_FIFO_HIWATER(0x8));
1727 } else if (((rdev->family) == CHIP_R600) ||
1728 ((rdev->family) == CHIP_RV630)) {
1729 tmp &= ~DONE_FIFO_HIWATER(0xff);
1730 tmp |= DONE_FIFO_HIWATER(0x4);
1731 }
1732 WREG32(SQ_MS_FIFO_SIZES, tmp);
1733
1734 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1735 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1736 */
1737 sq_config = RREG32(SQ_CONFIG);
1738 sq_config &= ~(PS_PRIO(3) |
1739 VS_PRIO(3) |
1740 GS_PRIO(3) |
1741 ES_PRIO(3));
1742 sq_config |= (DX9_CONSTS |
1743 VC_ENABLE |
1744 PS_PRIO(0) |
1745 VS_PRIO(1) |
1746 GS_PRIO(2) |
1747 ES_PRIO(3));
1748
1749 if ((rdev->family) == CHIP_R600) {
1750 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1751 NUM_VS_GPRS(124) |
1752 NUM_CLAUSE_TEMP_GPRS(4));
1753 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1754 NUM_ES_GPRS(0));
1755 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1756 NUM_VS_THREADS(48) |
1757 NUM_GS_THREADS(4) |
1758 NUM_ES_THREADS(4));
1759 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1760 NUM_VS_STACK_ENTRIES(128));
1761 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1762 NUM_ES_STACK_ENTRIES(0));
1763 } else if (((rdev->family) == CHIP_RV610) ||
1764 ((rdev->family) == CHIP_RV620) ||
1765 ((rdev->family) == CHIP_RS780) ||
1766 ((rdev->family) == CHIP_RS880)) {
1767 /* no vertex cache */
1768 sq_config &= ~VC_ENABLE;
1769
1770 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1771 NUM_VS_GPRS(44) |
1772 NUM_CLAUSE_TEMP_GPRS(2));
1773 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1774 NUM_ES_GPRS(17));
1775 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1776 NUM_VS_THREADS(78) |
1777 NUM_GS_THREADS(4) |
1778 NUM_ES_THREADS(31));
1779 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1780 NUM_VS_STACK_ENTRIES(40));
1781 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1782 NUM_ES_STACK_ENTRIES(16));
1783 } else if (((rdev->family) == CHIP_RV630) ||
1784 ((rdev->family) == CHIP_RV635)) {
1785 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1786 NUM_VS_GPRS(44) |
1787 NUM_CLAUSE_TEMP_GPRS(2));
1788 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1789 NUM_ES_GPRS(18));
1790 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1791 NUM_VS_THREADS(78) |
1792 NUM_GS_THREADS(4) |
1793 NUM_ES_THREADS(31));
1794 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1795 NUM_VS_STACK_ENTRIES(40));
1796 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1797 NUM_ES_STACK_ENTRIES(16));
1798 } else if ((rdev->family) == CHIP_RV670) {
1799 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1800 NUM_VS_GPRS(44) |
1801 NUM_CLAUSE_TEMP_GPRS(2));
1802 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1803 NUM_ES_GPRS(17));
1804 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1805 NUM_VS_THREADS(78) |
1806 NUM_GS_THREADS(4) |
1807 NUM_ES_THREADS(31));
1808 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1809 NUM_VS_STACK_ENTRIES(64));
1810 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1811 NUM_ES_STACK_ENTRIES(64));
1812 }
1813
1814 WREG32(SQ_CONFIG, sq_config);
1815 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1816 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1817 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1818 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1819 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1820
1821 if (((rdev->family) == CHIP_RV610) ||
1822 ((rdev->family) == CHIP_RV620) ||
1823 ((rdev->family) == CHIP_RS780) ||
1824 ((rdev->family) == CHIP_RS880)) {
1825 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1826 } else {
1827 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1828 }
1829
1830 /* More default values. 2D/3D driver should adjust as needed */
1831 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1832 S1_X(0x4) | S1_Y(0xc)));
1833 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1834 S1_X(0x2) | S1_Y(0x2) |
1835 S2_X(0xa) | S2_Y(0x6) |
1836 S3_X(0x6) | S3_Y(0xa)));
1837 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1838 S1_X(0x4) | S1_Y(0xc) |
1839 S2_X(0x1) | S2_Y(0x6) |
1840 S3_X(0xa) | S3_Y(0xe)));
1841 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1842 S5_X(0x0) | S5_Y(0x0) |
1843 S6_X(0xb) | S6_Y(0x4) |
1844 S7_X(0x7) | S7_Y(0x8)));
1845
1846 WREG32(VGT_STRMOUT_EN, 0);
1847 tmp = rdev->config.r600.max_pipes * 16;
1848 switch (rdev->family) {
1849 case CHIP_RV610:
1850 case CHIP_RV620:
1851 case CHIP_RS780:
1852 case CHIP_RS880:
1853 tmp += 32;
1854 break;
1855 case CHIP_RV670:
1856 tmp += 128;
1857 break;
1858 default:
1859 break;
1860 }
1861 if (tmp > 256) {
1862 tmp = 256;
1863 }
1864 WREG32(VGT_ES_PER_GS, 128);
1865 WREG32(VGT_GS_PER_ES, tmp);
1866 WREG32(VGT_GS_PER_VS, 2);
1867 WREG32(VGT_GS_VERTEX_REUSE, 16);
1868
1869 /* more default values. 2D/3D driver should adjust as needed */
1870 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1871 WREG32(VGT_STRMOUT_EN, 0);
1872 WREG32(SX_MISC, 0);
1873 WREG32(PA_SC_MODE_CNTL, 0);
1874 WREG32(PA_SC_AA_CONFIG, 0);
1875 WREG32(PA_SC_LINE_STIPPLE, 0);
1876 WREG32(SPI_INPUT_Z, 0);
1877 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1878 WREG32(CB_COLOR7_FRAG, 0);
1879
1880 /* Clear render buffer base addresses */
1881 WREG32(CB_COLOR0_BASE, 0);
1882 WREG32(CB_COLOR1_BASE, 0);
1883 WREG32(CB_COLOR2_BASE, 0);
1884 WREG32(CB_COLOR3_BASE, 0);
1885 WREG32(CB_COLOR4_BASE, 0);
1886 WREG32(CB_COLOR5_BASE, 0);
1887 WREG32(CB_COLOR6_BASE, 0);
1888 WREG32(CB_COLOR7_BASE, 0);
1889 WREG32(CB_COLOR7_FRAG, 0);
1890
1891 switch (rdev->family) {
1892 case CHIP_RV610:
1893 case CHIP_RV620:
1894 case CHIP_RS780:
1895 case CHIP_RS880:
1896 tmp = TC_L2_SIZE(8);
1897 break;
1898 case CHIP_RV630:
1899 case CHIP_RV635:
1900 tmp = TC_L2_SIZE(4);
1901 break;
1902 case CHIP_R600:
1903 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1904 break;
1905 default:
1906 tmp = TC_L2_SIZE(0);
1907 break;
1908 }
1909 WREG32(TC_CNTL, tmp);
1910
1911 tmp = RREG32(HDP_HOST_PATH_CNTL);
1912 WREG32(HDP_HOST_PATH_CNTL, tmp);
1913
1914 tmp = RREG32(ARB_POP);
1915 tmp |= ENABLE_TC128;
1916 WREG32(ARB_POP, tmp);
1917
1918 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1919 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1920 NUM_CLIP_SEQ(3)));
1921 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1922 }
1923
1924
1925 /*
1926 * Indirect registers accessor
1927 */
1928 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1929 {
1930 u32 r;
1931
1932 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1933 (void)RREG32(PCIE_PORT_INDEX);
1934 r = RREG32(PCIE_PORT_DATA);
1935 return r;
1936 }
1937
1938 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1939 {
1940 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1941 (void)RREG32(PCIE_PORT_INDEX);
1942 WREG32(PCIE_PORT_DATA, (v));
1943 (void)RREG32(PCIE_PORT_DATA);
1944 }
1945
1946 /*
1947 * CP & Ring
1948 */
1949 void r600_cp_stop(struct radeon_device *rdev)
1950 {
1951 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1952 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1953 WREG32(SCRATCH_UMSK, 0);
1954 }
1955
1956 int r600_init_microcode(struct radeon_device *rdev)
1957 {
1958 struct platform_device *pdev;
1959 const char *chip_name;
1960 const char *rlc_chip_name;
1961 size_t pfp_req_size, me_req_size, rlc_req_size;
1962 char fw_name[30];
1963 int err;
1964
1965 DRM_DEBUG("\n");
1966
1967 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1968 err = IS_ERR(pdev);
1969 if (err) {
1970 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1971 return -EINVAL;
1972 }
1973
1974 switch (rdev->family) {
1975 case CHIP_R600:
1976 chip_name = "R600";
1977 rlc_chip_name = "R600";
1978 break;
1979 case CHIP_RV610:
1980 chip_name = "RV610";
1981 rlc_chip_name = "R600";
1982 break;
1983 case CHIP_RV630:
1984 chip_name = "RV630";
1985 rlc_chip_name = "R600";
1986 break;
1987 case CHIP_RV620:
1988 chip_name = "RV620";
1989 rlc_chip_name = "R600";
1990 break;
1991 case CHIP_RV635:
1992 chip_name = "RV635";
1993 rlc_chip_name = "R600";
1994 break;
1995 case CHIP_RV670:
1996 chip_name = "RV670";
1997 rlc_chip_name = "R600";
1998 break;
1999 case CHIP_RS780:
2000 case CHIP_RS880:
2001 chip_name = "RS780";
2002 rlc_chip_name = "R600";
2003 break;
2004 case CHIP_RV770:
2005 chip_name = "RV770";
2006 rlc_chip_name = "R700";
2007 break;
2008 case CHIP_RV730:
2009 case CHIP_RV740:
2010 chip_name = "RV730";
2011 rlc_chip_name = "R700";
2012 break;
2013 case CHIP_RV710:
2014 chip_name = "RV710";
2015 rlc_chip_name = "R700";
2016 break;
2017 case CHIP_CEDAR:
2018 chip_name = "CEDAR";
2019 rlc_chip_name = "CEDAR";
2020 break;
2021 case CHIP_REDWOOD:
2022 chip_name = "REDWOOD";
2023 rlc_chip_name = "REDWOOD";
2024 break;
2025 case CHIP_JUNIPER:
2026 chip_name = "JUNIPER";
2027 rlc_chip_name = "JUNIPER";
2028 break;
2029 case CHIP_CYPRESS:
2030 case CHIP_HEMLOCK:
2031 chip_name = "CYPRESS";
2032 rlc_chip_name = "CYPRESS";
2033 break;
2034 case CHIP_PALM:
2035 chip_name = "PALM";
2036 rlc_chip_name = "SUMO";
2037 break;
2038 case CHIP_SUMO:
2039 chip_name = "SUMO";
2040 rlc_chip_name = "SUMO";
2041 break;
2042 case CHIP_SUMO2:
2043 chip_name = "SUMO2";
2044 rlc_chip_name = "SUMO";
2045 break;
2046 default: BUG();
2047 }
2048
2049 if (rdev->family >= CHIP_CEDAR) {
2050 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2051 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2052 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2053 } else if (rdev->family >= CHIP_RV770) {
2054 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2055 me_req_size = R700_PM4_UCODE_SIZE * 4;
2056 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2057 } else {
2058 pfp_req_size = PFP_UCODE_SIZE * 4;
2059 me_req_size = PM4_UCODE_SIZE * 12;
2060 rlc_req_size = RLC_UCODE_SIZE * 4;
2061 }
2062
2063 DRM_INFO("Loading %s Microcode\n", chip_name);
2064
2065 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2066 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2067 if (err)
2068 goto out;
2069 if (rdev->pfp_fw->size != pfp_req_size) {
2070 printk(KERN_ERR
2071 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2072 rdev->pfp_fw->size, fw_name);
2073 err = -EINVAL;
2074 goto out;
2075 }
2076
2077 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2078 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2079 if (err)
2080 goto out;
2081 if (rdev->me_fw->size != me_req_size) {
2082 printk(KERN_ERR
2083 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2084 rdev->me_fw->size, fw_name);
2085 err = -EINVAL;
2086 }
2087
2088 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2089 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2090 if (err)
2091 goto out;
2092 if (rdev->rlc_fw->size != rlc_req_size) {
2093 printk(KERN_ERR
2094 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2095 rdev->rlc_fw->size, fw_name);
2096 err = -EINVAL;
2097 }
2098
2099 out:
2100 platform_device_unregister(pdev);
2101
2102 if (err) {
2103 if (err != -EINVAL)
2104 printk(KERN_ERR
2105 "r600_cp: Failed to load firmware \"%s\"\n",
2106 fw_name);
2107 release_firmware(rdev->pfp_fw);
2108 rdev->pfp_fw = NULL;
2109 release_firmware(rdev->me_fw);
2110 rdev->me_fw = NULL;
2111 release_firmware(rdev->rlc_fw);
2112 rdev->rlc_fw = NULL;
2113 }
2114 return err;
2115 }
2116
2117 static int r600_cp_load_microcode(struct radeon_device *rdev)
2118 {
2119 const __be32 *fw_data;
2120 int i;
2121
2122 if (!rdev->me_fw || !rdev->pfp_fw)
2123 return -EINVAL;
2124
2125 r600_cp_stop(rdev);
2126
2127 WREG32(CP_RB_CNTL,
2128 #ifdef __BIG_ENDIAN
2129 BUF_SWAP_32BIT |
2130 #endif
2131 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2132
2133 /* Reset cp */
2134 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2135 RREG32(GRBM_SOFT_RESET);
2136 mdelay(15);
2137 WREG32(GRBM_SOFT_RESET, 0);
2138
2139 WREG32(CP_ME_RAM_WADDR, 0);
2140
2141 fw_data = (const __be32 *)rdev->me_fw->data;
2142 WREG32(CP_ME_RAM_WADDR, 0);
2143 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2144 WREG32(CP_ME_RAM_DATA,
2145 be32_to_cpup(fw_data++));
2146
2147 fw_data = (const __be32 *)rdev->pfp_fw->data;
2148 WREG32(CP_PFP_UCODE_ADDR, 0);
2149 for (i = 0; i < PFP_UCODE_SIZE; i++)
2150 WREG32(CP_PFP_UCODE_DATA,
2151 be32_to_cpup(fw_data++));
2152
2153 WREG32(CP_PFP_UCODE_ADDR, 0);
2154 WREG32(CP_ME_RAM_WADDR, 0);
2155 WREG32(CP_ME_RAM_RADDR, 0);
2156 return 0;
2157 }
2158
2159 int r600_cp_start(struct radeon_device *rdev)
2160 {
2161 int r;
2162 uint32_t cp_me;
2163
2164 r = radeon_ring_lock(rdev, 7);
2165 if (r) {
2166 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2167 return r;
2168 }
2169 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2170 radeon_ring_write(rdev, 0x1);
2171 if (rdev->family >= CHIP_RV770) {
2172 radeon_ring_write(rdev, 0x0);
2173 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2174 } else {
2175 radeon_ring_write(rdev, 0x3);
2176 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2177 }
2178 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2179 radeon_ring_write(rdev, 0);
2180 radeon_ring_write(rdev, 0);
2181 radeon_ring_unlock_commit(rdev);
2182
2183 cp_me = 0xff;
2184 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2185 return 0;
2186 }
2187
2188 int r600_cp_resume(struct radeon_device *rdev)
2189 {
2190 u32 tmp;
2191 u32 rb_bufsz;
2192 int r;
2193
2194 /* Reset cp */
2195 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2196 RREG32(GRBM_SOFT_RESET);
2197 mdelay(15);
2198 WREG32(GRBM_SOFT_RESET, 0);
2199
2200 /* Set ring buffer size */
2201 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2202 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2203 #ifdef __BIG_ENDIAN
2204 tmp |= BUF_SWAP_32BIT;
2205 #endif
2206 WREG32(CP_RB_CNTL, tmp);
2207 WREG32(CP_SEM_WAIT_TIMER, 0x4);
2208
2209 /* Set the write pointer delay */
2210 WREG32(CP_RB_WPTR_DELAY, 0);
2211
2212 /* Initialize the ring buffer's read and write pointers */
2213 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2214 WREG32(CP_RB_RPTR_WR, 0);
2215 WREG32(CP_RB_WPTR, 0);
2216
2217 /* set the wb address whether it's enabled or not */
2218 WREG32(CP_RB_RPTR_ADDR,
2219 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2220 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2221 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2222
2223 if (rdev->wb.enabled)
2224 WREG32(SCRATCH_UMSK, 0xff);
2225 else {
2226 tmp |= RB_NO_UPDATE;
2227 WREG32(SCRATCH_UMSK, 0);
2228 }
2229
2230 mdelay(1);
2231 WREG32(CP_RB_CNTL, tmp);
2232
2233 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2234 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2235
2236 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2237 rdev->cp.wptr = RREG32(CP_RB_WPTR);
2238
2239 r600_cp_start(rdev);
2240 rdev->cp.ready = true;
2241 r = radeon_ring_test(rdev);
2242 if (r) {
2243 rdev->cp.ready = false;
2244 return r;
2245 }
2246 return 0;
2247 }
2248
2249 void r600_cp_commit(struct radeon_device *rdev)
2250 {
2251 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2252 (void)RREG32(CP_RB_WPTR);
2253 }
2254
2255 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2256 {
2257 u32 rb_bufsz;
2258
2259 /* Align ring size */
2260 rb_bufsz = drm_order(ring_size / 8);
2261 ring_size = (1 << (rb_bufsz + 1)) * 4;
2262 rdev->cp.ring_size = ring_size;
2263 rdev->cp.align_mask = 16 - 1;
2264 }
2265
2266 void r600_cp_fini(struct radeon_device *rdev)
2267 {
2268 r600_cp_stop(rdev);
2269 radeon_ring_fini(rdev);
2270 }
2271
2272
2273 /*
2274 * GPU scratch registers helpers function.
2275 */
2276 void r600_scratch_init(struct radeon_device *rdev)
2277 {
2278 int i;
2279
2280 rdev->scratch.num_reg = 7;
2281 rdev->scratch.reg_base = SCRATCH_REG0;
2282 for (i = 0; i < rdev->scratch.num_reg; i++) {
2283 rdev->scratch.free[i] = true;
2284 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2285 }
2286 }
2287
2288 int r600_ring_test(struct radeon_device *rdev)
2289 {
2290 uint32_t scratch;
2291 uint32_t tmp = 0;
2292 unsigned i;
2293 int r;
2294
2295 r = radeon_scratch_get(rdev, &scratch);
2296 if (r) {
2297 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2298 return r;
2299 }
2300 WREG32(scratch, 0xCAFEDEAD);
2301 r = radeon_ring_lock(rdev, 3);
2302 if (r) {
2303 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2304 radeon_scratch_free(rdev, scratch);
2305 return r;
2306 }
2307 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2308 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2309 radeon_ring_write(rdev, 0xDEADBEEF);
2310 radeon_ring_unlock_commit(rdev);
2311 for (i = 0; i < rdev->usec_timeout; i++) {
2312 tmp = RREG32(scratch);
2313 if (tmp == 0xDEADBEEF)
2314 break;
2315 DRM_UDELAY(1);
2316 }
2317 if (i < rdev->usec_timeout) {
2318 DRM_INFO("ring test succeeded in %d usecs\n", i);
2319 } else {
2320 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2321 scratch, tmp);
2322 r = -EINVAL;
2323 }
2324 radeon_scratch_free(rdev, scratch);
2325 return r;
2326 }
2327
2328 void r600_fence_ring_emit(struct radeon_device *rdev,
2329 struct radeon_fence *fence)
2330 {
2331 if (rdev->wb.use_event) {
2332 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2333 (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2334 /* EVENT_WRITE_EOP - flush caches, send int */
2335 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2336 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2337 radeon_ring_write(rdev, addr & 0xffffffff);
2338 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2339 radeon_ring_write(rdev, fence->seq);
2340 radeon_ring_write(rdev, 0);
2341 } else {
2342 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2343 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2344 /* wait for 3D idle clean */
2345 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2346 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2347 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2348 /* Emit fence sequence & fire IRQ */
2349 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2350 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2351 radeon_ring_write(rdev, fence->seq);
2352 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2353 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2354 radeon_ring_write(rdev, RB_INT_STAT);
2355 }
2356 }
2357
2358 int r600_copy_blit(struct radeon_device *rdev,
2359 uint64_t src_offset, uint64_t dst_offset,
2360 unsigned num_pages, struct radeon_fence *fence)
2361 {
2362 int r;
2363
2364 mutex_lock(&rdev->r600_blit.mutex);
2365 rdev->r600_blit.vb_ib = NULL;
2366 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2367 if (r) {
2368 if (rdev->r600_blit.vb_ib)
2369 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2370 mutex_unlock(&rdev->r600_blit.mutex);
2371 return r;
2372 }
2373 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2374 r600_blit_done_copy(rdev, fence);
2375 mutex_unlock(&rdev->r600_blit.mutex);
2376 return 0;
2377 }
2378
2379 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2380 uint32_t tiling_flags, uint32_t pitch,
2381 uint32_t offset, uint32_t obj_size)
2382 {
2383 /* FIXME: implement */
2384 return 0;
2385 }
2386
2387 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2388 {
2389 /* FIXME: implement */
2390 }
2391
2392 int r600_startup(struct radeon_device *rdev)
2393 {
2394 int r;
2395
2396 /* enable pcie gen2 link */
2397 r600_pcie_gen2_enable(rdev);
2398
2399 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2400 r = r600_init_microcode(rdev);
2401 if (r) {
2402 DRM_ERROR("Failed to load firmware!\n");
2403 return r;
2404 }
2405 }
2406
2407 r600_mc_program(rdev);
2408 if (rdev->flags & RADEON_IS_AGP) {
2409 r600_agp_enable(rdev);
2410 } else {
2411 r = r600_pcie_gart_enable(rdev);
2412 if (r)
2413 return r;
2414 }
2415 r600_gpu_init(rdev);
2416 r = r600_blit_init(rdev);
2417 if (r) {
2418 r600_blit_fini(rdev);
2419 rdev->asic->copy = NULL;
2420 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2421 }
2422
2423 /* allocate wb buffer */
2424 r = radeon_wb_init(rdev);
2425 if (r)
2426 return r;
2427
2428 /* Enable IRQ */
2429 r = r600_irq_init(rdev);
2430 if (r) {
2431 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2432 radeon_irq_kms_fini(rdev);
2433 return r;
2434 }
2435 r600_irq_set(rdev);
2436
2437 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2438 if (r)
2439 return r;
2440 r = r600_cp_load_microcode(rdev);
2441 if (r)
2442 return r;
2443 r = r600_cp_resume(rdev);
2444 if (r)
2445 return r;
2446
2447 return 0;
2448 }
2449
2450 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2451 {
2452 uint32_t temp;
2453
2454 temp = RREG32(CONFIG_CNTL);
2455 if (state == false) {
2456 temp &= ~(1<<0);
2457 temp |= (1<<1);
2458 } else {
2459 temp &= ~(1<<1);
2460 }
2461 WREG32(CONFIG_CNTL, temp);
2462 }
2463
2464 int r600_resume(struct radeon_device *rdev)
2465 {
2466 int r;
2467
2468 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2469 * posting will perform necessary task to bring back GPU into good
2470 * shape.
2471 */
2472 /* post card */
2473 atom_asic_init(rdev->mode_info.atom_context);
2474
2475 r = r600_startup(rdev);
2476 if (r) {
2477 DRM_ERROR("r600 startup failed on resume\n");
2478 return r;
2479 }
2480
2481 r = r600_ib_test(rdev);
2482 if (r) {
2483 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2484 return r;
2485 }
2486
2487 r = r600_audio_init(rdev);
2488 if (r) {
2489 DRM_ERROR("radeon: audio resume failed\n");
2490 return r;
2491 }
2492
2493 return r;
2494 }
2495
2496 int r600_suspend(struct radeon_device *rdev)
2497 {
2498 int r;
2499
2500 r600_audio_fini(rdev);
2501 /* FIXME: we should wait for ring to be empty */
2502 r600_cp_stop(rdev);
2503 rdev->cp.ready = false;
2504 r600_irq_suspend(rdev);
2505 radeon_wb_disable(rdev);
2506 r600_pcie_gart_disable(rdev);
2507 /* unpin shaders bo */
2508 if (rdev->r600_blit.shader_obj) {
2509 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2510 if (!r) {
2511 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2512 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2513 }
2514 }
2515 return 0;
2516 }
2517
2518 /* Plan is to move initialization in that function and use
2519 * helper function so that radeon_device_init pretty much
2520 * do nothing more than calling asic specific function. This
2521 * should also allow to remove a bunch of callback function
2522 * like vram_info.
2523 */
2524 int r600_init(struct radeon_device *rdev)
2525 {
2526 int r;
2527
2528 if (r600_debugfs_mc_info_init(rdev)) {
2529 DRM_ERROR("Failed to register debugfs file for mc !\n");
2530 }
2531 /* This don't do much */
2532 r = radeon_gem_init(rdev);
2533 if (r)
2534 return r;
2535 /* Read BIOS */
2536 if (!radeon_get_bios(rdev)) {
2537 if (ASIC_IS_AVIVO(rdev))
2538 return -EINVAL;
2539 }
2540 /* Must be an ATOMBIOS */
2541 if (!rdev->is_atom_bios) {
2542 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2543 return -EINVAL;
2544 }
2545 r = radeon_atombios_init(rdev);
2546 if (r)
2547 return r;
2548 /* Post card if necessary */
2549 if (!radeon_card_posted(rdev)) {
2550 if (!rdev->bios) {
2551 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2552 return -EINVAL;
2553 }
2554 DRM_INFO("GPU not posted. posting now...\n");
2555 atom_asic_init(rdev->mode_info.atom_context);
2556 }
2557 /* Initialize scratch registers */
2558 r600_scratch_init(rdev);
2559 /* Initialize surface registers */
2560 radeon_surface_init(rdev);
2561 /* Initialize clocks */
2562 radeon_get_clock_info(rdev->ddev);
2563 /* Fence driver */
2564 r = radeon_fence_driver_init(rdev);
2565 if (r)
2566 return r;
2567 if (rdev->flags & RADEON_IS_AGP) {
2568 r = radeon_agp_init(rdev);
2569 if (r)
2570 radeon_agp_disable(rdev);
2571 }
2572 r = r600_mc_init(rdev);
2573 if (r)
2574 return r;
2575 /* Memory manager */
2576 r = radeon_bo_init(rdev);
2577 if (r)
2578 return r;
2579
2580 r = radeon_irq_kms_init(rdev);
2581 if (r)
2582 return r;
2583
2584 rdev->cp.ring_obj = NULL;
2585 r600_ring_init(rdev, 1024 * 1024);
2586
2587 rdev->ih.ring_obj = NULL;
2588 r600_ih_ring_init(rdev, 64 * 1024);
2589
2590 r = r600_pcie_gart_init(rdev);
2591 if (r)
2592 return r;
2593
2594 rdev->accel_working = true;
2595 r = r600_startup(rdev);
2596 if (r) {
2597 dev_err(rdev->dev, "disabling GPU acceleration\n");
2598 r600_cp_fini(rdev);
2599 r600_irq_fini(rdev);
2600 radeon_wb_fini(rdev);
2601 radeon_irq_kms_fini(rdev);
2602 r600_pcie_gart_fini(rdev);
2603 rdev->accel_working = false;
2604 }
2605 if (rdev->accel_working) {
2606 r = radeon_ib_pool_init(rdev);
2607 if (r) {
2608 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2609 rdev->accel_working = false;
2610 } else {
2611 r = r600_ib_test(rdev);
2612 if (r) {
2613 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2614 rdev->accel_working = false;
2615 }
2616 }
2617 }
2618
2619 r = r600_audio_init(rdev);
2620 if (r)
2621 return r; /* TODO error handling */
2622 return 0;
2623 }
2624
2625 void r600_fini(struct radeon_device *rdev)
2626 {
2627 r600_audio_fini(rdev);
2628 r600_blit_fini(rdev);
2629 r600_cp_fini(rdev);
2630 r600_irq_fini(rdev);
2631 radeon_wb_fini(rdev);
2632 radeon_ib_pool_fini(rdev);
2633 radeon_irq_kms_fini(rdev);
2634 r600_pcie_gart_fini(rdev);
2635 radeon_agp_fini(rdev);
2636 radeon_gem_fini(rdev);
2637 radeon_fence_driver_fini(rdev);
2638 radeon_bo_fini(rdev);
2639 radeon_atombios_fini(rdev);
2640 kfree(rdev->bios);
2641 rdev->bios = NULL;
2642 }
2643
2644
2645 /*
2646 * CS stuff
2647 */
2648 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2649 {
2650 /* FIXME: implement */
2651 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2652 radeon_ring_write(rdev,
2653 #ifdef __BIG_ENDIAN
2654 (2 << 0) |
2655 #endif
2656 (ib->gpu_addr & 0xFFFFFFFC));
2657 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2658 radeon_ring_write(rdev, ib->length_dw);
2659 }
2660
2661 int r600_ib_test(struct radeon_device *rdev)
2662 {
2663 struct radeon_ib *ib;
2664 uint32_t scratch;
2665 uint32_t tmp = 0;
2666 unsigned i;
2667 int r;
2668
2669 r = radeon_scratch_get(rdev, &scratch);
2670 if (r) {
2671 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2672 return r;
2673 }
2674 WREG32(scratch, 0xCAFEDEAD);
2675 r = radeon_ib_get(rdev, &ib);
2676 if (r) {
2677 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2678 return r;
2679 }
2680 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2681 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2682 ib->ptr[2] = 0xDEADBEEF;
2683 ib->ptr[3] = PACKET2(0);
2684 ib->ptr[4] = PACKET2(0);
2685 ib->ptr[5] = PACKET2(0);
2686 ib->ptr[6] = PACKET2(0);
2687 ib->ptr[7] = PACKET2(0);
2688 ib->ptr[8] = PACKET2(0);
2689 ib->ptr[9] = PACKET2(0);
2690 ib->ptr[10] = PACKET2(0);
2691 ib->ptr[11] = PACKET2(0);
2692 ib->ptr[12] = PACKET2(0);
2693 ib->ptr[13] = PACKET2(0);
2694 ib->ptr[14] = PACKET2(0);
2695 ib->ptr[15] = PACKET2(0);
2696 ib->length_dw = 16;
2697 r = radeon_ib_schedule(rdev, ib);
2698 if (r) {
2699 radeon_scratch_free(rdev, scratch);
2700 radeon_ib_free(rdev, &ib);
2701 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2702 return r;
2703 }
2704 r = radeon_fence_wait(ib->fence, false);
2705 if (r) {
2706 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2707 return r;
2708 }
2709 for (i = 0; i < rdev->usec_timeout; i++) {
2710 tmp = RREG32(scratch);
2711 if (tmp == 0xDEADBEEF)
2712 break;
2713 DRM_UDELAY(1);
2714 }
2715 if (i < rdev->usec_timeout) {
2716 DRM_INFO("ib test succeeded in %u usecs\n", i);
2717 } else {
2718 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2719 scratch, tmp);
2720 r = -EINVAL;
2721 }
2722 radeon_scratch_free(rdev, scratch);
2723 radeon_ib_free(rdev, &ib);
2724 return r;
2725 }
2726
2727 /*
2728 * Interrupts
2729 *
2730 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2731 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2732 * writing to the ring and the GPU consuming, the GPU writes to the ring
2733 * and host consumes. As the host irq handler processes interrupts, it
2734 * increments the rptr. When the rptr catches up with the wptr, all the
2735 * current interrupts have been processed.
2736 */
2737
2738 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2739 {
2740 u32 rb_bufsz;
2741
2742 /* Align ring size */
2743 rb_bufsz = drm_order(ring_size / 4);
2744 ring_size = (1 << rb_bufsz) * 4;
2745 rdev->ih.ring_size = ring_size;
2746 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2747 rdev->ih.rptr = 0;
2748 }
2749
2750 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2751 {
2752 int r;
2753
2754 /* Allocate ring buffer */
2755 if (rdev->ih.ring_obj == NULL) {
2756 r = radeon_bo_create(rdev, rdev->ih.ring_size,
2757 PAGE_SIZE, true,
2758 RADEON_GEM_DOMAIN_GTT,
2759 &rdev->ih.ring_obj);
2760 if (r) {
2761 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2762 return r;
2763 }
2764 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2765 if (unlikely(r != 0))
2766 return r;
2767 r = radeon_bo_pin(rdev->ih.ring_obj,
2768 RADEON_GEM_DOMAIN_GTT,
2769 &rdev->ih.gpu_addr);
2770 if (r) {
2771 radeon_bo_unreserve(rdev->ih.ring_obj);
2772 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2773 return r;
2774 }
2775 r = radeon_bo_kmap(rdev->ih.ring_obj,
2776 (void **)&rdev->ih.ring);
2777 radeon_bo_unreserve(rdev->ih.ring_obj);
2778 if (r) {
2779 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2780 return r;
2781 }
2782 }
2783 return 0;
2784 }
2785
2786 static void r600_ih_ring_fini(struct radeon_device *rdev)
2787 {
2788 int r;
2789 if (rdev->ih.ring_obj) {
2790 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2791 if (likely(r == 0)) {
2792 radeon_bo_kunmap(rdev->ih.ring_obj);
2793 radeon_bo_unpin(rdev->ih.ring_obj);
2794 radeon_bo_unreserve(rdev->ih.ring_obj);
2795 }
2796 radeon_bo_unref(&rdev->ih.ring_obj);
2797 rdev->ih.ring = NULL;
2798 rdev->ih.ring_obj = NULL;
2799 }
2800 }
2801
2802 void r600_rlc_stop(struct radeon_device *rdev)
2803 {
2804
2805 if ((rdev->family >= CHIP_RV770) &&
2806 (rdev->family <= CHIP_RV740)) {
2807 /* r7xx asics need to soft reset RLC before halting */
2808 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2809 RREG32(SRBM_SOFT_RESET);
2810 udelay(15000);
2811 WREG32(SRBM_SOFT_RESET, 0);
2812 RREG32(SRBM_SOFT_RESET);
2813 }
2814
2815 WREG32(RLC_CNTL, 0);
2816 }
2817
2818 static void r600_rlc_start(struct radeon_device *rdev)
2819 {
2820 WREG32(RLC_CNTL, RLC_ENABLE);
2821 }
2822
2823 static int r600_rlc_init(struct radeon_device *rdev)
2824 {
2825 u32 i;
2826 const __be32 *fw_data;
2827
2828 if (!rdev->rlc_fw)
2829 return -EINVAL;
2830
2831 r600_rlc_stop(rdev);
2832
2833 WREG32(RLC_HB_BASE, 0);
2834 WREG32(RLC_HB_CNTL, 0);
2835 WREG32(RLC_HB_RPTR, 0);
2836 WREG32(RLC_HB_WPTR, 0);
2837 if (rdev->family <= CHIP_CAICOS) {
2838 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2839 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2840 }
2841 WREG32(RLC_MC_CNTL, 0);
2842 WREG32(RLC_UCODE_CNTL, 0);
2843
2844 fw_data = (const __be32 *)rdev->rlc_fw->data;
2845 if (rdev->family >= CHIP_CAYMAN) {
2846 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2847 WREG32(RLC_UCODE_ADDR, i);
2848 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2849 }
2850 } else if (rdev->family >= CHIP_CEDAR) {
2851 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2852 WREG32(RLC_UCODE_ADDR, i);
2853 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2854 }
2855 } else if (rdev->family >= CHIP_RV770) {
2856 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2857 WREG32(RLC_UCODE_ADDR, i);
2858 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2859 }
2860 } else {
2861 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2862 WREG32(RLC_UCODE_ADDR, i);
2863 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2864 }
2865 }
2866 WREG32(RLC_UCODE_ADDR, 0);
2867
2868 r600_rlc_start(rdev);
2869
2870 return 0;
2871 }
2872
2873 static void r600_enable_interrupts(struct radeon_device *rdev)
2874 {
2875 u32 ih_cntl = RREG32(IH_CNTL);
2876 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2877
2878 ih_cntl |= ENABLE_INTR;
2879 ih_rb_cntl |= IH_RB_ENABLE;
2880 WREG32(IH_CNTL, ih_cntl);
2881 WREG32(IH_RB_CNTL, ih_rb_cntl);
2882 rdev->ih.enabled = true;
2883 }
2884
2885 void r600_disable_interrupts(struct radeon_device *rdev)
2886 {
2887 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2888 u32 ih_cntl = RREG32(IH_CNTL);
2889
2890 ih_rb_cntl &= ~IH_RB_ENABLE;
2891 ih_cntl &= ~ENABLE_INTR;
2892 WREG32(IH_RB_CNTL, ih_rb_cntl);
2893 WREG32(IH_CNTL, ih_cntl);
2894 /* set rptr, wptr to 0 */
2895 WREG32(IH_RB_RPTR, 0);
2896 WREG32(IH_RB_WPTR, 0);
2897 rdev->ih.enabled = false;
2898 rdev->ih.wptr = 0;
2899 rdev->ih.rptr = 0;
2900 }
2901
2902 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2903 {
2904 u32 tmp;
2905
2906 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2907 WREG32(GRBM_INT_CNTL, 0);
2908 WREG32(DxMODE_INT_MASK, 0);
2909 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2910 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
2911 if (ASIC_IS_DCE3(rdev)) {
2912 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2913 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2914 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2915 WREG32(DC_HPD1_INT_CONTROL, tmp);
2916 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2917 WREG32(DC_HPD2_INT_CONTROL, tmp);
2918 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2919 WREG32(DC_HPD3_INT_CONTROL, tmp);
2920 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2921 WREG32(DC_HPD4_INT_CONTROL, tmp);
2922 if (ASIC_IS_DCE32(rdev)) {
2923 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2924 WREG32(DC_HPD5_INT_CONTROL, tmp);
2925 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2926 WREG32(DC_HPD6_INT_CONTROL, tmp);
2927 }
2928 } else {
2929 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2930 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2931 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2932 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2933 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2934 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2935 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2936 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2937 }
2938 }
2939
2940 int r600_irq_init(struct radeon_device *rdev)
2941 {
2942 int ret = 0;
2943 int rb_bufsz;
2944 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2945
2946 /* allocate ring */
2947 ret = r600_ih_ring_alloc(rdev);
2948 if (ret)
2949 return ret;
2950
2951 /* disable irqs */
2952 r600_disable_interrupts(rdev);
2953
2954 /* init rlc */
2955 ret = r600_rlc_init(rdev);
2956 if (ret) {
2957 r600_ih_ring_fini(rdev);
2958 return ret;
2959 }
2960
2961 /* setup interrupt control */
2962 /* set dummy read address to ring address */
2963 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2964 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2965 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2966 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2967 */
2968 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2969 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2970 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2971 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2972
2973 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2974 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2975
2976 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2977 IH_WPTR_OVERFLOW_CLEAR |
2978 (rb_bufsz << 1));
2979
2980 if (rdev->wb.enabled)
2981 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2982
2983 /* set the writeback address whether it's enabled or not */
2984 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2985 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
2986
2987 WREG32(IH_RB_CNTL, ih_rb_cntl);
2988
2989 /* set rptr, wptr to 0 */
2990 WREG32(IH_RB_RPTR, 0);
2991 WREG32(IH_RB_WPTR, 0);
2992
2993 /* Default settings for IH_CNTL (disabled at first) */
2994 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2995 /* RPTR_REARM only works if msi's are enabled */
2996 if (rdev->msi_enabled)
2997 ih_cntl |= RPTR_REARM;
2998 WREG32(IH_CNTL, ih_cntl);
2999
3000 /* force the active interrupt state to all disabled */
3001 if (rdev->family >= CHIP_CEDAR)
3002 evergreen_disable_interrupt_state(rdev);
3003 else
3004 r600_disable_interrupt_state(rdev);
3005
3006 /* enable irqs */
3007 r600_enable_interrupts(rdev);
3008
3009 return ret;
3010 }
3011
3012 void r600_irq_suspend(struct radeon_device *rdev)
3013 {
3014 r600_irq_disable(rdev);
3015 r600_rlc_stop(rdev);
3016 }
3017
3018 void r600_irq_fini(struct radeon_device *rdev)
3019 {
3020 r600_irq_suspend(rdev);
3021 r600_ih_ring_fini(rdev);
3022 }
3023
3024 int r600_irq_set(struct radeon_device *rdev)
3025 {
3026 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3027 u32 mode_int = 0;
3028 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3029 u32 grbm_int_cntl = 0;
3030 u32 hdmi1, hdmi2;
3031 u32 d1grph = 0, d2grph = 0;
3032
3033 if (!rdev->irq.installed) {
3034 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3035 return -EINVAL;
3036 }
3037 /* don't enable anything if the ih is disabled */
3038 if (!rdev->ih.enabled) {
3039 r600_disable_interrupts(rdev);
3040 /* force the active interrupt state to all disabled */
3041 r600_disable_interrupt_state(rdev);
3042 return 0;
3043 }
3044
3045 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3046 if (ASIC_IS_DCE3(rdev)) {
3047 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3048 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3049 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3050 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3051 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3052 if (ASIC_IS_DCE32(rdev)) {
3053 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3054 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3055 }
3056 } else {
3057 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3058 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3059 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3060 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3061 }
3062
3063 if (rdev->irq.sw_int) {
3064 DRM_DEBUG("r600_irq_set: sw int\n");
3065 cp_int_cntl |= RB_INT_ENABLE;
3066 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3067 }
3068 if (rdev->irq.crtc_vblank_int[0] ||
3069 rdev->irq.pflip[0]) {
3070 DRM_DEBUG("r600_irq_set: vblank 0\n");
3071 mode_int |= D1MODE_VBLANK_INT_MASK;
3072 }
3073 if (rdev->irq.crtc_vblank_int[1] ||
3074 rdev->irq.pflip[1]) {
3075 DRM_DEBUG("r600_irq_set: vblank 1\n");
3076 mode_int |= D2MODE_VBLANK_INT_MASK;
3077 }
3078 if (rdev->irq.hpd[0]) {
3079 DRM_DEBUG("r600_irq_set: hpd 1\n");
3080 hpd1 |= DC_HPDx_INT_EN;
3081 }
3082 if (rdev->irq.hpd[1]) {
3083 DRM_DEBUG("r600_irq_set: hpd 2\n");
3084 hpd2 |= DC_HPDx_INT_EN;
3085 }
3086 if (rdev->irq.hpd[2]) {
3087 DRM_DEBUG("r600_irq_set: hpd 3\n");
3088 hpd3 |= DC_HPDx_INT_EN;
3089 }
3090 if (rdev->irq.hpd[3]) {
3091 DRM_DEBUG("r600_irq_set: hpd 4\n");
3092 hpd4 |= DC_HPDx_INT_EN;
3093 }
3094 if (rdev->irq.hpd[4]) {
3095 DRM_DEBUG("r600_irq_set: hpd 5\n");
3096 hpd5 |= DC_HPDx_INT_EN;
3097 }
3098 if (rdev->irq.hpd[5]) {
3099 DRM_DEBUG("r600_irq_set: hpd 6\n");
3100 hpd6 |= DC_HPDx_INT_EN;
3101 }
3102 if (rdev->irq.hdmi[0]) {
3103 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3104 hdmi1 |= R600_HDMI_INT_EN;
3105 }
3106 if (rdev->irq.hdmi[1]) {
3107 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3108 hdmi2 |= R600_HDMI_INT_EN;
3109 }
3110 if (rdev->irq.gui_idle) {
3111 DRM_DEBUG("gui idle\n");
3112 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3113 }
3114
3115 WREG32(CP_INT_CNTL, cp_int_cntl);
3116 WREG32(DxMODE_INT_MASK, mode_int);
3117 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3118 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3119 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3120 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3121 if (ASIC_IS_DCE3(rdev)) {
3122 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3123 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3124 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3125 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3126 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3127 if (ASIC_IS_DCE32(rdev)) {
3128 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3129 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3130 }
3131 } else {
3132 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3133 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3134 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3135 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3136 }
3137
3138 return 0;
3139 }
3140
3141 static inline void r600_irq_ack(struct radeon_device *rdev)
3142 {
3143 u32 tmp;
3144
3145 if (ASIC_IS_DCE3(rdev)) {
3146 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3147 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3148 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3149 } else {
3150 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3151 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3152 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3153 }
3154 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3155 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3156
3157 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3158 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3159 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3160 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3161 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3162 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3163 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3164 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3165 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3166 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3167 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3168 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3169 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3170 if (ASIC_IS_DCE3(rdev)) {
3171 tmp = RREG32(DC_HPD1_INT_CONTROL);
3172 tmp |= DC_HPDx_INT_ACK;
3173 WREG32(DC_HPD1_INT_CONTROL, tmp);
3174 } else {
3175 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3176 tmp |= DC_HPDx_INT_ACK;
3177 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3178 }
3179 }
3180 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3181 if (ASIC_IS_DCE3(rdev)) {
3182 tmp = RREG32(DC_HPD2_INT_CONTROL);
3183 tmp |= DC_HPDx_INT_ACK;
3184 WREG32(DC_HPD2_INT_CONTROL, tmp);
3185 } else {
3186 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3187 tmp |= DC_HPDx_INT_ACK;
3188 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3189 }
3190 }
3191 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3192 if (ASIC_IS_DCE3(rdev)) {
3193 tmp = RREG32(DC_HPD3_INT_CONTROL);
3194 tmp |= DC_HPDx_INT_ACK;
3195 WREG32(DC_HPD3_INT_CONTROL, tmp);
3196 } else {
3197 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3198 tmp |= DC_HPDx_INT_ACK;
3199 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3200 }
3201 }
3202 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3203 tmp = RREG32(DC_HPD4_INT_CONTROL);
3204 tmp |= DC_HPDx_INT_ACK;
3205 WREG32(DC_HPD4_INT_CONTROL, tmp);
3206 }
3207 if (ASIC_IS_DCE32(rdev)) {
3208 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3209 tmp = RREG32(DC_HPD5_INT_CONTROL);
3210 tmp |= DC_HPDx_INT_ACK;
3211 WREG32(DC_HPD5_INT_CONTROL, tmp);
3212 }
3213 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3214 tmp = RREG32(DC_HPD5_INT_CONTROL);
3215 tmp |= DC_HPDx_INT_ACK;
3216 WREG32(DC_HPD6_INT_CONTROL, tmp);
3217 }
3218 }
3219 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3220 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3221 }
3222 if (ASIC_IS_DCE3(rdev)) {
3223 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3224 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3225 }
3226 } else {
3227 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3228 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3229 }
3230 }
3231 }
3232
3233 void r600_irq_disable(struct radeon_device *rdev)
3234 {
3235 r600_disable_interrupts(rdev);
3236 /* Wait and acknowledge irq */
3237 mdelay(1);
3238 r600_irq_ack(rdev);
3239 r600_disable_interrupt_state(rdev);
3240 }
3241
3242 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3243 {
3244 u32 wptr, tmp;
3245
3246 if (rdev->wb.enabled)
3247 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3248 else
3249 wptr = RREG32(IH_RB_WPTR);
3250
3251 if (wptr & RB_OVERFLOW) {
3252 /* When a ring buffer overflow happen start parsing interrupt
3253 * from the last not overwritten vector (wptr + 16). Hopefully
3254 * this should allow us to catchup.
3255 */
3256 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3257 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3258 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3259 tmp = RREG32(IH_RB_CNTL);
3260 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3261 WREG32(IH_RB_CNTL, tmp);
3262 }
3263 return (wptr & rdev->ih.ptr_mask);
3264 }
3265
3266 /* r600 IV Ring
3267 * Each IV ring entry is 128 bits:
3268 * [7:0] - interrupt source id
3269 * [31:8] - reserved
3270 * [59:32] - interrupt source data
3271 * [127:60] - reserved
3272 *
3273 * The basic interrupt vector entries
3274 * are decoded as follows:
3275 * src_id src_data description
3276 * 1 0 D1 Vblank
3277 * 1 1 D1 Vline
3278 * 5 0 D2 Vblank
3279 * 5 1 D2 Vline
3280 * 19 0 FP Hot plug detection A
3281 * 19 1 FP Hot plug detection B
3282 * 19 2 DAC A auto-detection
3283 * 19 3 DAC B auto-detection
3284 * 21 4 HDMI block A
3285 * 21 5 HDMI block B
3286 * 176 - CP_INT RB
3287 * 177 - CP_INT IB1
3288 * 178 - CP_INT IB2
3289 * 181 - EOP Interrupt
3290 * 233 - GUI Idle
3291 *
3292 * Note, these are based on r600 and may need to be
3293 * adjusted or added to on newer asics
3294 */
3295
3296 int r600_irq_process(struct radeon_device *rdev)
3297 {
3298 u32 wptr;
3299 u32 rptr;
3300 u32 src_id, src_data;
3301 u32 ring_index;
3302 unsigned long flags;
3303 bool queue_hotplug = false;
3304
3305 if (!rdev->ih.enabled || rdev->shutdown)
3306 return IRQ_NONE;
3307
3308 /* No MSIs, need a dummy read to flush PCI DMAs */
3309 if (!rdev->msi_enabled)
3310 RREG32(IH_RB_WPTR);
3311
3312 wptr = r600_get_ih_wptr(rdev);
3313 rptr = rdev->ih.rptr;
3314 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3315
3316 spin_lock_irqsave(&rdev->ih.lock, flags);
3317
3318 if (rptr == wptr) {
3319 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3320 return IRQ_NONE;
3321 }
3322
3323 restart_ih:
3324 /* Order reading of wptr vs. reading of IH ring data */
3325 rmb();
3326
3327 /* display interrupts */
3328 r600_irq_ack(rdev);
3329
3330 rdev->ih.wptr = wptr;
3331 while (rptr != wptr) {
3332 /* wptr/rptr are in bytes! */
3333 ring_index = rptr / 4;
3334 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3335 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3336
3337 switch (src_id) {
3338 case 1: /* D1 vblank/vline */
3339 switch (src_data) {
3340 case 0: /* D1 vblank */
3341 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3342 if (rdev->irq.crtc_vblank_int[0]) {
3343 drm_handle_vblank(rdev->ddev, 0);
3344 rdev->pm.vblank_sync = true;
3345 wake_up(&rdev->irq.vblank_queue);
3346 }
3347 if (rdev->irq.pflip[0])
3348 radeon_crtc_handle_flip(rdev, 0);
3349 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3350 DRM_DEBUG("IH: D1 vblank\n");
3351 }
3352 break;
3353 case 1: /* D1 vline */
3354 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3355 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3356 DRM_DEBUG("IH: D1 vline\n");
3357 }
3358 break;
3359 default:
3360 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3361 break;
3362 }
3363 break;
3364 case 5: /* D2 vblank/vline */
3365 switch (src_data) {
3366 case 0: /* D2 vblank */
3367 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3368 if (rdev->irq.crtc_vblank_int[1]) {
3369 drm_handle_vblank(rdev->ddev, 1);
3370 rdev->pm.vblank_sync = true;
3371 wake_up(&rdev->irq.vblank_queue);
3372 }
3373 if (rdev->irq.pflip[1])
3374 radeon_crtc_handle_flip(rdev, 1);
3375 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3376 DRM_DEBUG("IH: D2 vblank\n");
3377 }
3378 break;
3379 case 1: /* D1 vline */
3380 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3381 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3382 DRM_DEBUG("IH: D2 vline\n");
3383 }
3384 break;
3385 default:
3386 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3387 break;
3388 }
3389 break;
3390 case 19: /* HPD/DAC hotplug */
3391 switch (src_data) {
3392 case 0:
3393 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3394 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3395 queue_hotplug = true;
3396 DRM_DEBUG("IH: HPD1\n");
3397 }
3398 break;
3399 case 1:
3400 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3401 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3402 queue_hotplug = true;
3403 DRM_DEBUG("IH: HPD2\n");
3404 }
3405 break;
3406 case 4:
3407 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3408 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3409 queue_hotplug = true;
3410 DRM_DEBUG("IH: HPD3\n");
3411 }
3412 break;
3413 case 5:
3414 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3415 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3416 queue_hotplug = true;
3417 DRM_DEBUG("IH: HPD4\n");
3418 }
3419 break;
3420 case 10:
3421 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3422 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3423 queue_hotplug = true;
3424 DRM_DEBUG("IH: HPD5\n");
3425 }
3426 break;
3427 case 12:
3428 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3429 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3430 queue_hotplug = true;
3431 DRM_DEBUG("IH: HPD6\n");
3432 }
3433 break;
3434 default:
3435 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3436 break;
3437 }
3438 break;
3439 case 21: /* HDMI */
3440 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3441 r600_audio_schedule_polling(rdev);
3442 break;
3443 case 176: /* CP_INT in ring buffer */
3444 case 177: /* CP_INT in IB1 */
3445 case 178: /* CP_INT in IB2 */
3446 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3447 radeon_fence_process(rdev);
3448 break;
3449 case 181: /* CP EOP event */
3450 DRM_DEBUG("IH: CP EOP\n");
3451 radeon_fence_process(rdev);
3452 break;
3453 case 233: /* GUI IDLE */
3454 DRM_DEBUG("IH: GUI idle\n");
3455 rdev->pm.gui_idle = true;
3456 wake_up(&rdev->irq.idle_queue);
3457 break;
3458 default:
3459 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3460 break;
3461 }
3462
3463 /* wptr/rptr are in bytes! */
3464 rptr += 16;
3465 rptr &= rdev->ih.ptr_mask;
3466 }
3467 /* make sure wptr hasn't changed while processing */
3468 wptr = r600_get_ih_wptr(rdev);
3469 if (wptr != rdev->ih.wptr)
3470 goto restart_ih;
3471 if (queue_hotplug)
3472 schedule_work(&rdev->hotplug_work);
3473 rdev->ih.rptr = rptr;
3474 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3475 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3476 return IRQ_HANDLED;
3477 }
3478
3479 /*
3480 * Debugfs info
3481 */
3482 #if defined(CONFIG_DEBUG_FS)
3483
3484 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3485 {
3486 struct drm_info_node *node = (struct drm_info_node *) m->private;
3487 struct drm_device *dev = node->minor->dev;
3488 struct radeon_device *rdev = dev->dev_private;
3489 unsigned count, i, j;
3490
3491 radeon_ring_free_size(rdev);
3492 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3493 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3494 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3495 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3496 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3497 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3498 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3499 seq_printf(m, "%u dwords in ring\n", count);
3500 i = rdev->cp.rptr;
3501 for (j = 0; j <= count; j++) {
3502 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3503 i = (i + 1) & rdev->cp.ptr_mask;
3504 }
3505 return 0;
3506 }
3507
3508 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3509 {
3510 struct drm_info_node *node = (struct drm_info_node *) m->private;
3511 struct drm_device *dev = node->minor->dev;
3512 struct radeon_device *rdev = dev->dev_private;
3513
3514 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3515 DREG32_SYS(m, rdev, VM_L2_STATUS);
3516 return 0;
3517 }
3518
3519 static struct drm_info_list r600_mc_info_list[] = {
3520 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3521 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3522 };
3523 #endif
3524
3525 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3526 {
3527 #if defined(CONFIG_DEBUG_FS)
3528 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3529 #else
3530 return 0;
3531 #endif
3532 }
3533
3534 /**
3535 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3536 * rdev: radeon device structure
3537 * bo: buffer object struct which userspace is waiting for idle
3538 *
3539 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3540 * through ring buffer, this leads to corruption in rendering, see
3541 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3542 * directly perform HDP flush by writing register through MMIO.
3543 */
3544 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3545 {
3546 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3547 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3548 * This seems to cause problems on some AGP cards. Just use the old
3549 * method for them.
3550 */
3551 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3552 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3553 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3554 u32 tmp;
3555
3556 WREG32(HDP_DEBUG1, 0);
3557 tmp = readl((void __iomem *)ptr);
3558 } else
3559 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3560 }
3561
3562 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3563 {
3564 u32 link_width_cntl, mask, target_reg;
3565
3566 if (rdev->flags & RADEON_IS_IGP)
3567 return;
3568
3569 if (!(rdev->flags & RADEON_IS_PCIE))
3570 return;
3571
3572 /* x2 cards have a special sequence */
3573 if (ASIC_IS_X2(rdev))
3574 return;
3575
3576 /* FIXME wait for idle */
3577
3578 switch (lanes) {
3579 case 0:
3580 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3581 break;
3582 case 1:
3583 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3584 break;
3585 case 2:
3586 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3587 break;
3588 case 4:
3589 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3590 break;
3591 case 8:
3592 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3593 break;
3594 case 12:
3595 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3596 break;
3597 case 16:
3598 default:
3599 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3600 break;
3601 }
3602
3603 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3604
3605 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3606 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3607 return;
3608
3609 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3610 return;
3611
3612 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3613 RADEON_PCIE_LC_RECONFIG_NOW |
3614 R600_PCIE_LC_RENEGOTIATE_EN |
3615 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3616 link_width_cntl |= mask;
3617
3618 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3619
3620 /* some northbridges can renegotiate the link rather than requiring
3621 * a complete re-config.
3622 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3623 */
3624 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3625 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3626 else
3627 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3628
3629 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3630 RADEON_PCIE_LC_RECONFIG_NOW));
3631
3632 if (rdev->family >= CHIP_RV770)
3633 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3634 else
3635 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3636
3637 /* wait for lane set to complete */
3638 link_width_cntl = RREG32(target_reg);
3639 while (link_width_cntl == 0xffffffff)
3640 link_width_cntl = RREG32(target_reg);
3641
3642 }
3643
3644 int r600_get_pcie_lanes(struct radeon_device *rdev)
3645 {
3646 u32 link_width_cntl;
3647
3648 if (rdev->flags & RADEON_IS_IGP)
3649 return 0;
3650
3651 if (!(rdev->flags & RADEON_IS_PCIE))
3652 return 0;
3653
3654 /* x2 cards have a special sequence */
3655 if (ASIC_IS_X2(rdev))
3656 return 0;
3657
3658 /* FIXME wait for idle */
3659
3660 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3661
3662 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3663 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3664 return 0;
3665 case RADEON_PCIE_LC_LINK_WIDTH_X1:
3666 return 1;
3667 case RADEON_PCIE_LC_LINK_WIDTH_X2:
3668 return 2;
3669 case RADEON_PCIE_LC_LINK_WIDTH_X4:
3670 return 4;
3671 case RADEON_PCIE_LC_LINK_WIDTH_X8:
3672 return 8;
3673 case RADEON_PCIE_LC_LINK_WIDTH_X16:
3674 default:
3675 return 16;
3676 }
3677 }
3678
3679 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3680 {
3681 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3682 u16 link_cntl2;
3683
3684 if (radeon_pcie_gen2 == 0)
3685 return;
3686
3687 if (rdev->flags & RADEON_IS_IGP)
3688 return;
3689
3690 if (!(rdev->flags & RADEON_IS_PCIE))
3691 return;
3692
3693 /* x2 cards have a special sequence */
3694 if (ASIC_IS_X2(rdev))
3695 return;
3696
3697 /* only RV6xx+ chips are supported */
3698 if (rdev->family <= CHIP_R600)
3699 return;
3700
3701 /* 55 nm r6xx asics */
3702 if ((rdev->family == CHIP_RV670) ||
3703 (rdev->family == CHIP_RV620) ||
3704 (rdev->family == CHIP_RV635)) {
3705 /* advertise upconfig capability */
3706 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3707 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3708 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3709 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3710 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3711 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3712 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3713 LC_RECONFIG_ARC_MISSING_ESCAPE);
3714 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3715 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3716 } else {
3717 link_width_cntl |= LC_UPCONFIGURE_DIS;
3718 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3719 }
3720 }
3721
3722 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3723 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3724 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3725
3726 /* 55 nm r6xx asics */
3727 if ((rdev->family == CHIP_RV670) ||
3728 (rdev->family == CHIP_RV620) ||
3729 (rdev->family == CHIP_RV635)) {
3730 WREG32(MM_CFGREGS_CNTL, 0x8);
3731 link_cntl2 = RREG32(0x4088);
3732 WREG32(MM_CFGREGS_CNTL, 0);
3733 /* not supported yet */
3734 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3735 return;
3736 }
3737
3738 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3739 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3740 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3741 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3742 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3743 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3744
3745 tmp = RREG32(0x541c);
3746 WREG32(0x541c, tmp | 0x8);
3747 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3748 link_cntl2 = RREG16(0x4088);
3749 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3750 link_cntl2 |= 0x2;
3751 WREG16(0x4088, link_cntl2);
3752 WREG32(MM_CFGREGS_CNTL, 0);
3753
3754 if ((rdev->family == CHIP_RV670) ||
3755 (rdev->family == CHIP_RV620) ||
3756 (rdev->family == CHIP_RV635)) {
3757 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3758 training_cntl &= ~LC_POINT_7_PLUS_EN;
3759 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3760 } else {
3761 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3762 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3763 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3764 }
3765
3766 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3767 speed_cntl |= LC_GEN2_EN_STRAP;
3768 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3769
3770 } else {
3771 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3772 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3773 if (1)
3774 link_width_cntl |= LC_UPCONFIGURE_DIS;
3775 else
3776 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3777 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3778 }
3779 }
Linux with added FPC-III support