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drm/radeon/kms: set DMA mask properly on newer PCI asics
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / radeon_cp.c
blob045ec59478f98210567375c9fa2d5a8c5f9493ac
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "drm_sarea.h"
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
37 #include "r300_reg.h"
38
39 #define RADEON_FIFO_DEBUG 0
40
41 /* Firmware Names */
42 #define FIRMWARE_R100 "radeon/R100_cp.bin"
43 #define FIRMWARE_R200 "radeon/R200_cp.bin"
44 #define FIRMWARE_R300 "radeon/R300_cp.bin"
45 #define FIRMWARE_R420 "radeon/R420_cp.bin"
46 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
47 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
48 #define FIRMWARE_R520 "radeon/R520_cp.bin"
49
50 MODULE_FIRMWARE(FIRMWARE_R100);
51 MODULE_FIRMWARE(FIRMWARE_R200);
52 MODULE_FIRMWARE(FIRMWARE_R300);
53 MODULE_FIRMWARE(FIRMWARE_R420);
54 MODULE_FIRMWARE(FIRMWARE_RS690);
55 MODULE_FIRMWARE(FIRMWARE_RS600);
56 MODULE_FIRMWARE(FIRMWARE_R520);
57
58 static int radeon_do_cleanup_cp(struct drm_device * dev);
59 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
60
61 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
62 {
63 u32 val;
64
65 if (dev_priv->flags & RADEON_IS_AGP) {
66 val = DRM_READ32(dev_priv->ring_rptr, off);
67 } else {
68 val = *(((volatile u32 *)
69 dev_priv->ring_rptr->handle) +
70 (off / sizeof(u32)));
71 val = le32_to_cpu(val);
72 }
73 return val;
74 }
75
76 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
77 {
78 if (dev_priv->writeback_works)
79 return radeon_read_ring_rptr(dev_priv, 0);
80 else {
81 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
82 return RADEON_READ(R600_CP_RB_RPTR);
83 else
84 return RADEON_READ(RADEON_CP_RB_RPTR);
85 }
86 }
87
88 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
89 {
90 if (dev_priv->flags & RADEON_IS_AGP)
91 DRM_WRITE32(dev_priv->ring_rptr, off, val);
92 else
93 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
94 (off / sizeof(u32))) = cpu_to_le32(val);
95 }
96
97 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
98 {
99 radeon_write_ring_rptr(dev_priv, 0, val);
100 }
101
102 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
103 {
104 if (dev_priv->writeback_works) {
105 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
106 return radeon_read_ring_rptr(dev_priv,
107 R600_SCRATCHOFF(index));
108 else
109 return radeon_read_ring_rptr(dev_priv,
110 RADEON_SCRATCHOFF(index));
111 } else {
112 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
113 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
114 else
115 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
116 }
117 }
118
119 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
120 {
121 u32 ret;
122
123 if (addr < 0x10000)
124 ret = DRM_READ32(dev_priv->mmio, addr);
125 else {
126 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
127 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
128 }
129
130 return ret;
131 }
132
133 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
134 {
135 u32 ret;
136 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
137 ret = RADEON_READ(R520_MC_IND_DATA);
138 RADEON_WRITE(R520_MC_IND_INDEX, 0);
139 return ret;
140 }
141
142 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
143 {
144 u32 ret;
145 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
146 ret = RADEON_READ(RS480_NB_MC_DATA);
147 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
148 return ret;
149 }
150
151 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
152 {
153 u32 ret;
154 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
155 ret = RADEON_READ(RS690_MC_DATA);
156 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
157 return ret;
158 }
159
160 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
161 {
162 u32 ret;
163 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
164 RS600_MC_IND_CITF_ARB0));
165 ret = RADEON_READ(RS600_MC_DATA);
166 return ret;
167 }
168
169 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
170 {
171 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
172 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
173 return RS690_READ_MCIND(dev_priv, addr);
174 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
175 return RS600_READ_MCIND(dev_priv, addr);
176 else
177 return RS480_READ_MCIND(dev_priv, addr);
178 }
179
180 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
181 {
182
183 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
184 return RADEON_READ(R700_MC_VM_FB_LOCATION);
185 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
186 return RADEON_READ(R600_MC_VM_FB_LOCATION);
187 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
188 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
189 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
190 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
191 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
192 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
193 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
194 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
195 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
196 else
197 return RADEON_READ(RADEON_MC_FB_LOCATION);
198 }
199
200 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
201 {
202 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
203 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
204 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
205 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
206 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
207 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
208 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
209 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
210 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
211 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
212 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
213 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
214 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
215 else
216 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
217 }
218
219 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
220 {
221 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
222 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
223 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
224 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
225 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
226 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
227 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
228 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
229 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
230 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
231 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
232 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
233 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
234 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
235 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
236 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
237 else
238 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
239 }
240
241 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
242 {
243 u32 agp_base_hi = upper_32_bits(agp_base);
244 u32 agp_base_lo = agp_base & 0xffffffff;
245 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
246
247 /* R6xx/R7xx must be aligned to a 4MB boundary */
248 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
249 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
250 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
251 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
252 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
253 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
254 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
255 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
256 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
257 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
258 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
259 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
260 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
261 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
262 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
263 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
264 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
265 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
266 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
267 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
268 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
269 } else {
270 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
271 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
272 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
273 }
274 }
275
276 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
277 {
278 u32 tmp;
279 /* Turn on bus mastering */
280 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
281 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
282 /* rs600/rs690/rs740 */
283 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
284 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
285 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
286 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
287 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
288 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
289 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
290 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
291 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
292 } /* PCIE cards appears to not need this */
293 }
294
295 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
296 {
297 drm_radeon_private_t *dev_priv = dev->dev_private;
298
299 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
300 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
301 }
302
303 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
304 {
305 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
306 return RADEON_READ(RADEON_PCIE_DATA);
307 }
308
309 #if RADEON_FIFO_DEBUG
310 static void radeon_status(drm_radeon_private_t * dev_priv)
311 {
312 printk("%s:\n", __func__);
313 printk("RBBM_STATUS = 0x%08x\n",
314 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
315 printk("CP_RB_RTPR = 0x%08x\n",
316 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
317 printk("CP_RB_WTPR = 0x%08x\n",
318 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
319 printk("AIC_CNTL = 0x%08x\n",
320 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
321 printk("AIC_STAT = 0x%08x\n",
322 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
323 printk("AIC_PT_BASE = 0x%08x\n",
324 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
325 printk("TLB_ADDR = 0x%08x\n",
326 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
327 printk("TLB_DATA = 0x%08x\n",
328 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
329 }
330 #endif
331
332 /* ================================================================
333 * Engine, FIFO control
334 */
335
336 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
337 {
338 u32 tmp;
339 int i;
340
341 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
342
343 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
344 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
345 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
346 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
347
348 for (i = 0; i < dev_priv->usec_timeout; i++) {
349 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
350 & RADEON_RB3D_DC_BUSY)) {
351 return 0;
352 }
353 DRM_UDELAY(1);
354 }
355 } else {
356 /* don't flush or purge cache here or lockup */
357 return 0;
358 }
359
360 #if RADEON_FIFO_DEBUG
361 DRM_ERROR("failed!\n");
362 radeon_status(dev_priv);
363 #endif
364 return -EBUSY;
365 }
366
367 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
368 {
369 int i;
370
371 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
372
373 for (i = 0; i < dev_priv->usec_timeout; i++) {
374 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
375 & RADEON_RBBM_FIFOCNT_MASK);
376 if (slots >= entries)
377 return 0;
378 DRM_UDELAY(1);
379 }
380 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
381 RADEON_READ(RADEON_RBBM_STATUS),
382 RADEON_READ(R300_VAP_CNTL_STATUS));
383
384 #if RADEON_FIFO_DEBUG
385 DRM_ERROR("failed!\n");
386 radeon_status(dev_priv);
387 #endif
388 return -EBUSY;
389 }
390
391 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
392 {
393 int i, ret;
394
395 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
396
397 ret = radeon_do_wait_for_fifo(dev_priv, 64);
398 if (ret)
399 return ret;
400
401 for (i = 0; i < dev_priv->usec_timeout; i++) {
402 if (!(RADEON_READ(RADEON_RBBM_STATUS)
403 & RADEON_RBBM_ACTIVE)) {
404 radeon_do_pixcache_flush(dev_priv);
405 return 0;
406 }
407 DRM_UDELAY(1);
408 }
409 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
410 RADEON_READ(RADEON_RBBM_STATUS),
411 RADEON_READ(R300_VAP_CNTL_STATUS));
412
413 #if RADEON_FIFO_DEBUG
414 DRM_ERROR("failed!\n");
415 radeon_status(dev_priv);
416 #endif
417 return -EBUSY;
418 }
419
420 static void radeon_init_pipes(struct drm_device *dev)
421 {
422 drm_radeon_private_t *dev_priv = dev->dev_private;
423 uint32_t gb_tile_config, gb_pipe_sel = 0;
424
425 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
426 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
427 if ((z_pipe_sel & 3) == 3)
428 dev_priv->num_z_pipes = 2;
429 else
430 dev_priv->num_z_pipes = 1;
431 } else
432 dev_priv->num_z_pipes = 1;
433
434 /* RS4xx/RS6xx/R4xx/R5xx */
435 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
436 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
437 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
438 /* SE cards have 1 pipe */
439 if ((dev->pdev->device == 0x5e4c) ||
440 (dev->pdev->device == 0x5e4f))
441 dev_priv->num_gb_pipes = 1;
442 } else {
443 /* R3xx */
444 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
445 dev->pdev->device != 0x4144) ||
446 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
447 dev->pdev->device != 0x4148)) {
448 dev_priv->num_gb_pipes = 2;
449 } else {
450 /* RV3xx/R300 AD/R350 AH */
451 dev_priv->num_gb_pipes = 1;
452 }
453 }
454 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
455
456 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
457
458 switch (dev_priv->num_gb_pipes) {
459 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
460 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
461 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
462 default:
463 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
464 }
465
466 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
467 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
468 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
469 }
470 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
471 radeon_do_wait_for_idle(dev_priv);
472 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
473 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
474 R300_DC_AUTOFLUSH_ENABLE |
475 R300_DC_DC_DISABLE_IGNORE_PE));
476
477
478 }
479
480 /* ================================================================
481 * CP control, initialization
482 */
483
484 /* Load the microcode for the CP */
485 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
486 {
487 struct platform_device *pdev;
488 const char *fw_name = NULL;
489 int err;
490
491 DRM_DEBUG("\n");
492
493 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
494 err = IS_ERR(pdev);
495 if (err) {
496 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
497 return -EINVAL;
498 }
499
500 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
501 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
502 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
503 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
504 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
505 DRM_INFO("Loading R100 Microcode\n");
506 fw_name = FIRMWARE_R100;
507 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
508 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
509 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
510 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
511 DRM_INFO("Loading R200 Microcode\n");
512 fw_name = FIRMWARE_R200;
513 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
514 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
515 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
516 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
517 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
518 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
519 DRM_INFO("Loading R300 Microcode\n");
520 fw_name = FIRMWARE_R300;
521 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
522 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
523 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
524 DRM_INFO("Loading R400 Microcode\n");
525 fw_name = FIRMWARE_R420;
526 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
527 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
528 DRM_INFO("Loading RS690/RS740 Microcode\n");
529 fw_name = FIRMWARE_RS690;
530 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
531 DRM_INFO("Loading RS600 Microcode\n");
532 fw_name = FIRMWARE_RS600;
533 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
534 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
535 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
536 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
537 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
538 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
539 DRM_INFO("Loading R500 Microcode\n");
540 fw_name = FIRMWARE_R520;
541 }
542
543 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
544 platform_device_unregister(pdev);
545 if (err) {
546 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
547 fw_name);
548 } else if (dev_priv->me_fw->size % 8) {
549 printk(KERN_ERR
550 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
551 dev_priv->me_fw->size, fw_name);
552 err = -EINVAL;
553 release_firmware(dev_priv->me_fw);
554 dev_priv->me_fw = NULL;
555 }
556 return err;
557 }
558
559 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
560 {
561 const __be32 *fw_data;
562 int i, size;
563
564 radeon_do_wait_for_idle(dev_priv);
565
566 if (dev_priv->me_fw) {
567 size = dev_priv->me_fw->size / 4;
568 fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
569 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
570 for (i = 0; i < size; i += 2) {
571 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
572 be32_to_cpup(&fw_data[i]));
573 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
574 be32_to_cpup(&fw_data[i + 1]));
575 }
576 }
577 }
578
579 /* Flush any pending commands to the CP. This should only be used just
580 * prior to a wait for idle, as it informs the engine that the command
581 * stream is ending.
582 */
583 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
584 {
585 DRM_DEBUG("\n");
586 #if 0
587 u32 tmp;
588
589 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
590 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
591 #endif
592 }
593
594 /* Wait for the CP to go idle.
595 */
596 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
597 {
598 RING_LOCALS;
599 DRM_DEBUG("\n");
600
601 BEGIN_RING(6);
602
603 RADEON_PURGE_CACHE();
604 RADEON_PURGE_ZCACHE();
605 RADEON_WAIT_UNTIL_IDLE();
606
607 ADVANCE_RING();
608 COMMIT_RING();
609
610 return radeon_do_wait_for_idle(dev_priv);
611 }
612
613 /* Start the Command Processor.
614 */
615 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
616 {
617 RING_LOCALS;
618 DRM_DEBUG("\n");
619
620 radeon_do_wait_for_idle(dev_priv);
621
622 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
623
624 dev_priv->cp_running = 1;
625
626 /* on r420, any DMA from CP to system memory while 2D is active
627 * can cause a hang. workaround is to queue a CP RESYNC token
628 */
629 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
630 BEGIN_RING(3);
631 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
632 OUT_RING(5); /* scratch reg 5 */
633 OUT_RING(0xdeadbeef);
634 ADVANCE_RING();
635 COMMIT_RING();
636 }
637
638 BEGIN_RING(8);
639 /* isync can only be written through cp on r5xx write it here */
640 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
641 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
642 RADEON_ISYNC_ANY3D_IDLE2D |
643 RADEON_ISYNC_WAIT_IDLEGUI |
644 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
645 RADEON_PURGE_CACHE();
646 RADEON_PURGE_ZCACHE();
647 RADEON_WAIT_UNTIL_IDLE();
648 ADVANCE_RING();
649 COMMIT_RING();
650
651 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
652 }
653
654 /* Reset the Command Processor. This will not flush any pending
655 * commands, so you must wait for the CP command stream to complete
656 * before calling this routine.
657 */
658 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
659 {
660 u32 cur_read_ptr;
661 DRM_DEBUG("\n");
662
663 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
664 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
665 SET_RING_HEAD(dev_priv, cur_read_ptr);
666 dev_priv->ring.tail = cur_read_ptr;
667 }
668
669 /* Stop the Command Processor. This will not flush any pending
670 * commands, so you must flush the command stream and wait for the CP
671 * to go idle before calling this routine.
672 */
673 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
674 {
675 RING_LOCALS;
676 DRM_DEBUG("\n");
677
678 /* finish the pending CP_RESYNC token */
679 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
680 BEGIN_RING(2);
681 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
682 OUT_RING(R300_RB3D_DC_FINISH);
683 ADVANCE_RING();
684 COMMIT_RING();
685 radeon_do_wait_for_idle(dev_priv);
686 }
687
688 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
689
690 dev_priv->cp_running = 0;
691 }
692
693 /* Reset the engine. This will stop the CP if it is running.
694 */
695 static int radeon_do_engine_reset(struct drm_device * dev)
696 {
697 drm_radeon_private_t *dev_priv = dev->dev_private;
698 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
699 DRM_DEBUG("\n");
700
701 radeon_do_pixcache_flush(dev_priv);
702
703 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
704 /* may need something similar for newer chips */
705 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
706 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
707
708 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
709 RADEON_FORCEON_MCLKA |
710 RADEON_FORCEON_MCLKB |
711 RADEON_FORCEON_YCLKA |
712 RADEON_FORCEON_YCLKB |
713 RADEON_FORCEON_MC |
714 RADEON_FORCEON_AIC));
715 }
716
717 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
718
719 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
720 RADEON_SOFT_RESET_CP |
721 RADEON_SOFT_RESET_HI |
722 RADEON_SOFT_RESET_SE |
723 RADEON_SOFT_RESET_RE |
724 RADEON_SOFT_RESET_PP |
725 RADEON_SOFT_RESET_E2 |
726 RADEON_SOFT_RESET_RB));
727 RADEON_READ(RADEON_RBBM_SOFT_RESET);
728 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
729 ~(RADEON_SOFT_RESET_CP |
730 RADEON_SOFT_RESET_HI |
731 RADEON_SOFT_RESET_SE |
732 RADEON_SOFT_RESET_RE |
733 RADEON_SOFT_RESET_PP |
734 RADEON_SOFT_RESET_E2 |
735 RADEON_SOFT_RESET_RB)));
736 RADEON_READ(RADEON_RBBM_SOFT_RESET);
737
738 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
739 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
740 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
741 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
742 }
743
744 /* setup the raster pipes */
745 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
746 radeon_init_pipes(dev);
747
748 /* Reset the CP ring */
749 radeon_do_cp_reset(dev_priv);
750
751 /* The CP is no longer running after an engine reset */
752 dev_priv->cp_running = 0;
753
754 /* Reset any pending vertex, indirect buffers */
755 radeon_freelist_reset(dev);
756
757 return 0;
758 }
759
760 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
761 drm_radeon_private_t *dev_priv,
762 struct drm_file *file_priv)
763 {
764 struct drm_radeon_master_private *master_priv;
765 u32 ring_start, cur_read_ptr;
766
767 /* Initialize the memory controller. With new memory map, the fb location
768 * is not changed, it should have been properly initialized already. Part
769 * of the problem is that the code below is bogus, assuming the GART is
770 * always appended to the fb which is not necessarily the case
771 */
772 if (!dev_priv->new_memmap)
773 radeon_write_fb_location(dev_priv,
774 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
775 | (dev_priv->fb_location >> 16));
776
777 #if __OS_HAS_AGP
778 if (dev_priv->flags & RADEON_IS_AGP) {
779 radeon_write_agp_base(dev_priv, dev->agp->base);
780
781 radeon_write_agp_location(dev_priv,
782 (((dev_priv->gart_vm_start - 1 +
783 dev_priv->gart_size) & 0xffff0000) |
784 (dev_priv->gart_vm_start >> 16)));
785
786 ring_start = (dev_priv->cp_ring->offset
787 - dev->agp->base
788 + dev_priv->gart_vm_start);
789 } else
790 #endif
791 ring_start = (dev_priv->cp_ring->offset
792 - (unsigned long)dev->sg->virtual
793 + dev_priv->gart_vm_start);
794
795 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
796
797 /* Set the write pointer delay */
798 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
799
800 /* Initialize the ring buffer's read and write pointers */
801 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
802 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
803 SET_RING_HEAD(dev_priv, cur_read_ptr);
804 dev_priv->ring.tail = cur_read_ptr;
805
806 #if __OS_HAS_AGP
807 if (dev_priv->flags & RADEON_IS_AGP) {
808 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
809 dev_priv->ring_rptr->offset
810 - dev->agp->base + dev_priv->gart_vm_start);
811 } else
812 #endif
813 {
814 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
815 dev_priv->ring_rptr->offset
816 - ((unsigned long) dev->sg->virtual)
817 + dev_priv->gart_vm_start);
818 }
819
820 /* Set ring buffer size */
821 #ifdef __BIG_ENDIAN
822 RADEON_WRITE(RADEON_CP_RB_CNTL,
823 RADEON_BUF_SWAP_32BIT |
824 (dev_priv->ring.fetch_size_l2ow << 18) |
825 (dev_priv->ring.rptr_update_l2qw << 8) |
826 dev_priv->ring.size_l2qw);
827 #else
828 RADEON_WRITE(RADEON_CP_RB_CNTL,
829 (dev_priv->ring.fetch_size_l2ow << 18) |
830 (dev_priv->ring.rptr_update_l2qw << 8) |
831 dev_priv->ring.size_l2qw);
832 #endif
833
834
835 /* Initialize the scratch register pointer. This will cause
836 * the scratch register values to be written out to memory
837 * whenever they are updated.
838 *
839 * We simply put this behind the ring read pointer, this works
840 * with PCI GART as well as (whatever kind of) AGP GART
841 */
842 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
843 + RADEON_SCRATCH_REG_OFFSET);
844
845 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
846
847 radeon_enable_bm(dev_priv);
848
849 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
850 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
851
852 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
853 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
854
855 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
856 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
857
858 /* reset sarea copies of these */
859 master_priv = file_priv->master->driver_priv;
860 if (master_priv->sarea_priv) {
861 master_priv->sarea_priv->last_frame = 0;
862 master_priv->sarea_priv->last_dispatch = 0;
863 master_priv->sarea_priv->last_clear = 0;
864 }
865
866 radeon_do_wait_for_idle(dev_priv);
867
868 /* Sync everything up */
869 RADEON_WRITE(RADEON_ISYNC_CNTL,
870 (RADEON_ISYNC_ANY2D_IDLE3D |
871 RADEON_ISYNC_ANY3D_IDLE2D |
872 RADEON_ISYNC_WAIT_IDLEGUI |
873 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
874
875 }
876
877 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
878 {
879 u32 tmp;
880
881 /* Start with assuming that writeback doesn't work */
882 dev_priv->writeback_works = 0;
883
884 /* Writeback doesn't seem to work everywhere, test it here and possibly
885 * enable it if it appears to work
886 */
887 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
888
889 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
890
891 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
892 u32 val;
893
894 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
895 if (val == 0xdeadbeef)
896 break;
897 DRM_UDELAY(1);
898 }
899
900 if (tmp < dev_priv->usec_timeout) {
901 dev_priv->writeback_works = 1;
902 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
903 } else {
904 dev_priv->writeback_works = 0;
905 DRM_INFO("writeback test failed\n");
906 }
907 if (radeon_no_wb == 1) {
908 dev_priv->writeback_works = 0;
909 DRM_INFO("writeback forced off\n");
910 }
911
912 if (!dev_priv->writeback_works) {
913 /* Disable writeback to avoid unnecessary bus master transfer */
914 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
915 RADEON_RB_NO_UPDATE);
916 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
917 }
918 }
919
920 /* Enable or disable IGP GART on the chip */
921 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
922 {
923 u32 temp;
924
925 if (on) {
926 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
927 dev_priv->gart_vm_start,
928 (long)dev_priv->gart_info.bus_addr,
929 dev_priv->gart_size);
930
931 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
932 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
933 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
934 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
935 RS690_BLOCK_GFX_D3_EN));
936 else
937 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
938
939 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
940 RS480_VA_SIZE_32MB));
941
942 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
943 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
944 RS480_TLB_ENABLE |
945 RS480_GTW_LAC_EN |
946 RS480_1LEVEL_GART));
947
948 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
949 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
950 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
951
952 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
953 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
954 RS480_REQ_TYPE_SNOOP_DIS));
955
956 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
957
958 dev_priv->gart_size = 32*1024*1024;
959 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
960 0xffff0000) | (dev_priv->gart_vm_start >> 16));
961
962 radeon_write_agp_location(dev_priv, temp);
963
964 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
965 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
966 RS480_VA_SIZE_32MB));
967
968 do {
969 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
970 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
971 break;
972 DRM_UDELAY(1);
973 } while (1);
974
975 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
976 RS480_GART_CACHE_INVALIDATE);
977
978 do {
979 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
980 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
981 break;
982 DRM_UDELAY(1);
983 } while (1);
984
985 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
986 } else {
987 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
988 }
989 }
990
991 /* Enable or disable IGP GART on the chip */
992 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
993 {
994 u32 temp;
995 int i;
996
997 if (on) {
998 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
999 dev_priv->gart_vm_start,
1000 (long)dev_priv->gart_info.bus_addr,
1001 dev_priv->gart_size);
1002
1003 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
1004 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
1005
1006 for (i = 0; i < 19; i++)
1007 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
1008 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
1009 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
1010 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
1011 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
1012 RS600_ENABLE_FRAGMENT_PROCESSING |
1013 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
1014
1015 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
1016 RS600_PAGE_TABLE_TYPE_FLAT));
1017
1018 /* disable all other contexts */
1019 for (i = 1; i < 8; i++)
1020 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
1021
1022 /* setup the page table aperture */
1023 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
1024 dev_priv->gart_info.bus_addr);
1025 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
1026 dev_priv->gart_vm_start);
1027 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
1028 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1029 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1030
1031 /* setup the system aperture */
1032 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
1033 dev_priv->gart_vm_start);
1034 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
1035 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1036
1037 /* enable page tables */
1038 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1039 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1040
1041 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1042 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1043
1044 /* invalidate the cache */
1045 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1046
1047 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1048 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1049 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1050
1051 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1052 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1053 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1054
1055 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1056 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1057 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1058
1059 } else {
1060 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1061 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1062 temp &= ~RS600_ENABLE_PAGE_TABLES;
1063 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1064 }
1065 }
1066
1067 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1068 {
1069 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1070 if (on) {
1071
1072 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1073 dev_priv->gart_vm_start,
1074 (long)dev_priv->gart_info.bus_addr,
1075 dev_priv->gart_size);
1076 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1077 dev_priv->gart_vm_start);
1078 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1079 dev_priv->gart_info.bus_addr);
1080 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1081 dev_priv->gart_vm_start);
1082 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1083 dev_priv->gart_vm_start +
1084 dev_priv->gart_size - 1);
1085
1086 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1087
1088 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1089 RADEON_PCIE_TX_GART_EN);
1090 } else {
1091 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1092 tmp & ~RADEON_PCIE_TX_GART_EN);
1093 }
1094 }
1095
1096 /* Enable or disable PCI GART on the chip */
1097 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1098 {
1099 u32 tmp;
1100
1101 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1102 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1103 (dev_priv->flags & RADEON_IS_IGPGART)) {
1104 radeon_set_igpgart(dev_priv, on);
1105 return;
1106 }
1107
1108 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1109 rs600_set_igpgart(dev_priv, on);
1110 return;
1111 }
1112
1113 if (dev_priv->flags & RADEON_IS_PCIE) {
1114 radeon_set_pciegart(dev_priv, on);
1115 return;
1116 }
1117
1118 tmp = RADEON_READ(RADEON_AIC_CNTL);
1119
1120 if (on) {
1121 RADEON_WRITE(RADEON_AIC_CNTL,
1122 tmp | RADEON_PCIGART_TRANSLATE_EN);
1123
1124 /* set PCI GART page-table base address
1125 */
1126 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1127
1128 /* set address range for PCI address translate
1129 */
1130 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1131 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1132 + dev_priv->gart_size - 1);
1133
1134 /* Turn off AGP aperture -- is this required for PCI GART?
1135 */
1136 radeon_write_agp_location(dev_priv, 0xffffffc0);
1137 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1138 } else {
1139 RADEON_WRITE(RADEON_AIC_CNTL,
1140 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1141 }
1142 }
1143
1144 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1145 {
1146 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1147 struct radeon_virt_surface *vp;
1148 int i;
1149
1150 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1151 if (!dev_priv->virt_surfaces[i].file_priv ||
1152 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1153 break;
1154 }
1155 if (i >= 2 * RADEON_MAX_SURFACES)
1156 return -ENOMEM;
1157 vp = &dev_priv->virt_surfaces[i];
1158
1159 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1160 struct radeon_surface *sp = &dev_priv->surfaces[i];
1161 if (sp->refcount)
1162 continue;
1163
1164 vp->surface_index = i;
1165 vp->lower = gart_info->bus_addr;
1166 vp->upper = vp->lower + gart_info->table_size;
1167 vp->flags = 0;
1168 vp->file_priv = PCIGART_FILE_PRIV;
1169
1170 sp->refcount = 1;
1171 sp->lower = vp->lower;
1172 sp->upper = vp->upper;
1173 sp->flags = 0;
1174
1175 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1176 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1177 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1178 return 0;
1179 }
1180
1181 return -ENOMEM;
1182 }
1183
1184 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1185 struct drm_file *file_priv)
1186 {
1187 drm_radeon_private_t *dev_priv = dev->dev_private;
1188 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1189
1190 DRM_DEBUG("\n");
1191
1192 /* if we require new memory map but we don't have it fail */
1193 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1194 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1195 radeon_do_cleanup_cp(dev);
1196 return -EINVAL;
1197 }
1198
1199 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1200 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1201 dev_priv->flags &= ~RADEON_IS_AGP;
1202 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1203 && !init->is_pci) {
1204 DRM_DEBUG("Restoring AGP flag\n");
1205 dev_priv->flags |= RADEON_IS_AGP;
1206 }
1207
1208 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1209 DRM_ERROR("PCI GART memory not allocated!\n");
1210 radeon_do_cleanup_cp(dev);
1211 return -EINVAL;
1212 }
1213
1214 dev_priv->usec_timeout = init->usec_timeout;
1215 if (dev_priv->usec_timeout < 1 ||
1216 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1217 DRM_DEBUG("TIMEOUT problem!\n");
1218 radeon_do_cleanup_cp(dev);
1219 return -EINVAL;
1220 }
1221
1222 /* Enable vblank on CRTC1 for older X servers
1223 */
1224 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1225
1226 switch(init->func) {
1227 case RADEON_INIT_R200_CP:
1228 dev_priv->microcode_version = UCODE_R200;
1229 break;
1230 case RADEON_INIT_R300_CP:
1231 dev_priv->microcode_version = UCODE_R300;
1232 break;
1233 default:
1234 dev_priv->microcode_version = UCODE_R100;
1235 }
1236
1237 dev_priv->do_boxes = 0;
1238 dev_priv->cp_mode = init->cp_mode;
1239
1240 /* We don't support anything other than bus-mastering ring mode,
1241 * but the ring can be in either AGP or PCI space for the ring
1242 * read pointer.
1243 */
1244 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1245 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1246 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1247 radeon_do_cleanup_cp(dev);
1248 return -EINVAL;
1249 }
1250
1251 switch (init->fb_bpp) {
1252 case 16:
1253 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1254 break;
1255 case 32:
1256 default:
1257 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1258 break;
1259 }
1260 dev_priv->front_offset = init->front_offset;
1261 dev_priv->front_pitch = init->front_pitch;
1262 dev_priv->back_offset = init->back_offset;
1263 dev_priv->back_pitch = init->back_pitch;
1264
1265 switch (init->depth_bpp) {
1266 case 16:
1267 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1268 break;
1269 case 32:
1270 default:
1271 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1272 break;
1273 }
1274 dev_priv->depth_offset = init->depth_offset;
1275 dev_priv->depth_pitch = init->depth_pitch;
1276
1277 /* Hardware state for depth clears. Remove this if/when we no
1278 * longer clear the depth buffer with a 3D rectangle. Hard-code
1279 * all values to prevent unwanted 3D state from slipping through
1280 * and screwing with the clear operation.
1281 */
1282 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1283 (dev_priv->color_fmt << 10) |
1284 (dev_priv->microcode_version ==
1285 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1286
1287 dev_priv->depth_clear.rb3d_zstencilcntl =
1288 (dev_priv->depth_fmt |
1289 RADEON_Z_TEST_ALWAYS |
1290 RADEON_STENCIL_TEST_ALWAYS |
1291 RADEON_STENCIL_S_FAIL_REPLACE |
1292 RADEON_STENCIL_ZPASS_REPLACE |
1293 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1294
1295 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1296 RADEON_BFACE_SOLID |
1297 RADEON_FFACE_SOLID |
1298 RADEON_FLAT_SHADE_VTX_LAST |
1299 RADEON_DIFFUSE_SHADE_FLAT |
1300 RADEON_ALPHA_SHADE_FLAT |
1301 RADEON_SPECULAR_SHADE_FLAT |
1302 RADEON_FOG_SHADE_FLAT |
1303 RADEON_VTX_PIX_CENTER_OGL |
1304 RADEON_ROUND_MODE_TRUNC |
1305 RADEON_ROUND_PREC_8TH_PIX);
1306
1307
1308 dev_priv->ring_offset = init->ring_offset;
1309 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1310 dev_priv->buffers_offset = init->buffers_offset;
1311 dev_priv->gart_textures_offset = init->gart_textures_offset;
1312
1313 master_priv->sarea = drm_getsarea(dev);
1314 if (!master_priv->sarea) {
1315 DRM_ERROR("could not find sarea!\n");
1316 radeon_do_cleanup_cp(dev);
1317 return -EINVAL;
1318 }
1319
1320 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1321 if (!dev_priv->cp_ring) {
1322 DRM_ERROR("could not find cp ring region!\n");
1323 radeon_do_cleanup_cp(dev);
1324 return -EINVAL;
1325 }
1326 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1327 if (!dev_priv->ring_rptr) {
1328 DRM_ERROR("could not find ring read pointer!\n");
1329 radeon_do_cleanup_cp(dev);
1330 return -EINVAL;
1331 }
1332 dev->agp_buffer_token = init->buffers_offset;
1333 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1334 if (!dev->agp_buffer_map) {
1335 DRM_ERROR("could not find dma buffer region!\n");
1336 radeon_do_cleanup_cp(dev);
1337 return -EINVAL;
1338 }
1339
1340 if (init->gart_textures_offset) {
1341 dev_priv->gart_textures =
1342 drm_core_findmap(dev, init->gart_textures_offset);
1343 if (!dev_priv->gart_textures) {
1344 DRM_ERROR("could not find GART texture region!\n");
1345 radeon_do_cleanup_cp(dev);
1346 return -EINVAL;
1347 }
1348 }
1349
1350 #if __OS_HAS_AGP
1351 if (dev_priv->flags & RADEON_IS_AGP) {
1352 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1353 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1354 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1355 if (!dev_priv->cp_ring->handle ||
1356 !dev_priv->ring_rptr->handle ||
1357 !dev->agp_buffer_map->handle) {
1358 DRM_ERROR("could not find ioremap agp regions!\n");
1359 radeon_do_cleanup_cp(dev);
1360 return -EINVAL;
1361 }
1362 } else
1363 #endif
1364 {
1365 dev_priv->cp_ring->handle =
1366 (void *)(unsigned long)dev_priv->cp_ring->offset;
1367 dev_priv->ring_rptr->handle =
1368 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1369 dev->agp_buffer_map->handle =
1370 (void *)(unsigned long)dev->agp_buffer_map->offset;
1371
1372 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1373 dev_priv->cp_ring->handle);
1374 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1375 dev_priv->ring_rptr->handle);
1376 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1377 dev->agp_buffer_map->handle);
1378 }
1379
1380 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1381 dev_priv->fb_size =
1382 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1383 - dev_priv->fb_location;
1384
1385 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1386 ((dev_priv->front_offset
1387 + dev_priv->fb_location) >> 10));
1388
1389 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1390 ((dev_priv->back_offset
1391 + dev_priv->fb_location) >> 10));
1392
1393 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1394 ((dev_priv->depth_offset
1395 + dev_priv->fb_location) >> 10));
1396
1397 dev_priv->gart_size = init->gart_size;
1398
1399 /* New let's set the memory map ... */
1400 if (dev_priv->new_memmap) {
1401 u32 base = 0;
1402
1403 DRM_INFO("Setting GART location based on new memory map\n");
1404
1405 /* If using AGP, try to locate the AGP aperture at the same
1406 * location in the card and on the bus, though we have to
1407 * align it down.
1408 */
1409 #if __OS_HAS_AGP
1410 if (dev_priv->flags & RADEON_IS_AGP) {
1411 base = dev->agp->base;
1412 /* Check if valid */
1413 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1414 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1415 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1416 dev->agp->base);
1417 base = 0;
1418 }
1419 }
1420 #endif
1421 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1422 if (base == 0) {
1423 base = dev_priv->fb_location + dev_priv->fb_size;
1424 if (base < dev_priv->fb_location ||
1425 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1426 base = dev_priv->fb_location
1427 - dev_priv->gart_size;
1428 }
1429 dev_priv->gart_vm_start = base & 0xffc00000u;
1430 if (dev_priv->gart_vm_start != base)
1431 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1432 base, dev_priv->gart_vm_start);
1433 } else {
1434 DRM_INFO("Setting GART location based on old memory map\n");
1435 dev_priv->gart_vm_start = dev_priv->fb_location +
1436 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1437 }
1438
1439 #if __OS_HAS_AGP
1440 if (dev_priv->flags & RADEON_IS_AGP)
1441 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1442 - dev->agp->base
1443 + dev_priv->gart_vm_start);
1444 else
1445 #endif
1446 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1447 - (unsigned long)dev->sg->virtual
1448 + dev_priv->gart_vm_start);
1449
1450 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1451 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1452 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1453 dev_priv->gart_buffers_offset);
1454
1455 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1456 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1457 + init->ring_size / sizeof(u32));
1458 dev_priv->ring.size = init->ring_size;
1459 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1460
1461 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1462 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1463
1464 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1465 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1466 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1467
1468 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1469
1470 #if __OS_HAS_AGP
1471 if (dev_priv->flags & RADEON_IS_AGP) {
1472 /* Turn off PCI GART */
1473 radeon_set_pcigart(dev_priv, 0);
1474 } else
1475 #endif
1476 {
1477 u32 sctrl;
1478 int ret;
1479
1480 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1481 /* if we have an offset set from userspace */
1482 if (dev_priv->pcigart_offset_set) {
1483 dev_priv->gart_info.bus_addr =
1484 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1485 dev_priv->gart_info.mapping.offset =
1486 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1487 dev_priv->gart_info.mapping.size =
1488 dev_priv->gart_info.table_size;
1489
1490 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1491 dev_priv->gart_info.addr =
1492 dev_priv->gart_info.mapping.handle;
1493
1494 if (dev_priv->flags & RADEON_IS_PCIE)
1495 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1496 else
1497 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1498 dev_priv->gart_info.gart_table_location =
1499 DRM_ATI_GART_FB;
1500
1501 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1502 dev_priv->gart_info.addr,
1503 dev_priv->pcigart_offset);
1504 } else {
1505 if (dev_priv->flags & RADEON_IS_IGPGART)
1506 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1507 else
1508 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1509 dev_priv->gart_info.gart_table_location =
1510 DRM_ATI_GART_MAIN;
1511 dev_priv->gart_info.addr = NULL;
1512 dev_priv->gart_info.bus_addr = 0;
1513 if (dev_priv->flags & RADEON_IS_PCIE) {
1514 DRM_ERROR
1515 ("Cannot use PCI Express without GART in FB memory\n");
1516 radeon_do_cleanup_cp(dev);
1517 return -EINVAL;
1518 }
1519 }
1520
1521 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1522 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1523 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1524 ret = r600_page_table_init(dev);
1525 else
1526 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1527 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1528
1529 if (!ret) {
1530 DRM_ERROR("failed to init PCI GART!\n");
1531 radeon_do_cleanup_cp(dev);
1532 return -ENOMEM;
1533 }
1534
1535 ret = radeon_setup_pcigart_surface(dev_priv);
1536 if (ret) {
1537 DRM_ERROR("failed to setup GART surface!\n");
1538 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1539 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1540 else
1541 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1542 radeon_do_cleanup_cp(dev);
1543 return ret;
1544 }
1545
1546 /* Turn on PCI GART */
1547 radeon_set_pcigart(dev_priv, 1);
1548 }
1549
1550 if (!dev_priv->me_fw) {
1551 int err = radeon_cp_init_microcode(dev_priv);
1552 if (err) {
1553 DRM_ERROR("Failed to load firmware!\n");
1554 radeon_do_cleanup_cp(dev);
1555 return err;
1556 }
1557 }
1558 radeon_cp_load_microcode(dev_priv);
1559 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1560
1561 dev_priv->last_buf = 0;
1562
1563 radeon_do_engine_reset(dev);
1564 radeon_test_writeback(dev_priv);
1565
1566 return 0;
1567 }
1568
1569 static int radeon_do_cleanup_cp(struct drm_device * dev)
1570 {
1571 drm_radeon_private_t *dev_priv = dev->dev_private;
1572 DRM_DEBUG("\n");
1573
1574 /* Make sure interrupts are disabled here because the uninstall ioctl
1575 * may not have been called from userspace and after dev_private
1576 * is freed, it's too late.
1577 */
1578 if (dev->irq_enabled)
1579 drm_irq_uninstall(dev);
1580
1581 #if __OS_HAS_AGP
1582 if (dev_priv->flags & RADEON_IS_AGP) {
1583 if (dev_priv->cp_ring != NULL) {
1584 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1585 dev_priv->cp_ring = NULL;
1586 }
1587 if (dev_priv->ring_rptr != NULL) {
1588 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1589 dev_priv->ring_rptr = NULL;
1590 }
1591 if (dev->agp_buffer_map != NULL) {
1592 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1593 dev->agp_buffer_map = NULL;
1594 }
1595 } else
1596 #endif
1597 {
1598
1599 if (dev_priv->gart_info.bus_addr) {
1600 /* Turn off PCI GART */
1601 radeon_set_pcigart(dev_priv, 0);
1602 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1603 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1604 else {
1605 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1606 DRM_ERROR("failed to cleanup PCI GART!\n");
1607 }
1608 }
1609
1610 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1611 {
1612 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1613 dev_priv->gart_info.addr = NULL;
1614 }
1615 }
1616 /* only clear to the start of flags */
1617 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1618
1619 return 0;
1620 }
1621
1622 /* This code will reinit the Radeon CP hardware after a resume from disc.
1623 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1624 * here we make sure that all Radeon hardware initialisation is re-done without
1625 * affecting running applications.
1626 *
1627 * Charl P. Botha <http://cpbotha.net>
1628 */
1629 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1630 {
1631 drm_radeon_private_t *dev_priv = dev->dev_private;
1632
1633 if (!dev_priv) {
1634 DRM_ERROR("Called with no initialization\n");
1635 return -EINVAL;
1636 }
1637
1638 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1639
1640 #if __OS_HAS_AGP
1641 if (dev_priv->flags & RADEON_IS_AGP) {
1642 /* Turn off PCI GART */
1643 radeon_set_pcigart(dev_priv, 0);
1644 } else
1645 #endif
1646 {
1647 /* Turn on PCI GART */
1648 radeon_set_pcigart(dev_priv, 1);
1649 }
1650
1651 radeon_cp_load_microcode(dev_priv);
1652 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1653
1654 dev_priv->have_z_offset = 0;
1655 radeon_do_engine_reset(dev);
1656 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1657
1658 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1659
1660 return 0;
1661 }
1662
1663 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1664 {
1665 drm_radeon_private_t *dev_priv = dev->dev_private;
1666 drm_radeon_init_t *init = data;
1667
1668 LOCK_TEST_WITH_RETURN(dev, file_priv);
1669
1670 if (init->func == RADEON_INIT_R300_CP)
1671 r300_init_reg_flags(dev);
1672
1673 switch (init->func) {
1674 case RADEON_INIT_CP:
1675 case RADEON_INIT_R200_CP:
1676 case RADEON_INIT_R300_CP:
1677 return radeon_do_init_cp(dev, init, file_priv);
1678 case RADEON_INIT_R600_CP:
1679 return r600_do_init_cp(dev, init, file_priv);
1680 case RADEON_CLEANUP_CP:
1681 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1682 return r600_do_cleanup_cp(dev);
1683 else
1684 return radeon_do_cleanup_cp(dev);
1685 }
1686
1687 return -EINVAL;
1688 }
1689
1690 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1691 {
1692 drm_radeon_private_t *dev_priv = dev->dev_private;
1693 DRM_DEBUG("\n");
1694
1695 LOCK_TEST_WITH_RETURN(dev, file_priv);
1696
1697 if (dev_priv->cp_running) {
1698 DRM_DEBUG("while CP running\n");
1699 return 0;
1700 }
1701 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1702 DRM_DEBUG("called with bogus CP mode (%d)\n",
1703 dev_priv->cp_mode);
1704 return 0;
1705 }
1706
1707 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1708 r600_do_cp_start(dev_priv);
1709 else
1710 radeon_do_cp_start(dev_priv);
1711
1712 return 0;
1713 }
1714
1715 /* Stop the CP. The engine must have been idled before calling this
1716 * routine.
1717 */
1718 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1719 {
1720 drm_radeon_private_t *dev_priv = dev->dev_private;
1721 drm_radeon_cp_stop_t *stop = data;
1722 int ret;
1723 DRM_DEBUG("\n");
1724
1725 LOCK_TEST_WITH_RETURN(dev, file_priv);
1726
1727 if (!dev_priv->cp_running)
1728 return 0;
1729
1730 /* Flush any pending CP commands. This ensures any outstanding
1731 * commands are exectuted by the engine before we turn it off.
1732 */
1733 if (stop->flush) {
1734 radeon_do_cp_flush(dev_priv);
1735 }
1736
1737 /* If we fail to make the engine go idle, we return an error
1738 * code so that the DRM ioctl wrapper can try again.
1739 */
1740 if (stop->idle) {
1741 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1742 ret = r600_do_cp_idle(dev_priv);
1743 else
1744 ret = radeon_do_cp_idle(dev_priv);
1745 if (ret)
1746 return ret;
1747 }
1748
1749 /* Finally, we can turn off the CP. If the engine isn't idle,
1750 * we will get some dropped triangles as they won't be fully
1751 * rendered before the CP is shut down.
1752 */
1753 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1754 r600_do_cp_stop(dev_priv);
1755 else
1756 radeon_do_cp_stop(dev_priv);
1757
1758 /* Reset the engine */
1759 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1760 r600_do_engine_reset(dev);
1761 else
1762 radeon_do_engine_reset(dev);
1763
1764 return 0;
1765 }
1766
1767 void radeon_do_release(struct drm_device * dev)
1768 {
1769 drm_radeon_private_t *dev_priv = dev->dev_private;
1770 int i, ret;
1771
1772 if (dev_priv) {
1773 if (dev_priv->cp_running) {
1774 /* Stop the cp */
1775 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1776 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1777 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1778 #ifdef __linux__
1779 schedule();
1780 #else
1781 tsleep(&ret, PZERO, "rdnrel", 1);
1782 #endif
1783 }
1784 } else {
1785 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1786 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1787 #ifdef __linux__
1788 schedule();
1789 #else
1790 tsleep(&ret, PZERO, "rdnrel", 1);
1791 #endif
1792 }
1793 }
1794 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1795 r600_do_cp_stop(dev_priv);
1796 r600_do_engine_reset(dev);
1797 } else {
1798 radeon_do_cp_stop(dev_priv);
1799 radeon_do_engine_reset(dev);
1800 }
1801 }
1802
1803 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1804 /* Disable *all* interrupts */
1805 if (dev_priv->mmio) /* remove this after permanent addmaps */
1806 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1807
1808 if (dev_priv->mmio) { /* remove all surfaces */
1809 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1810 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1811 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1812 16 * i, 0);
1813 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1814 16 * i, 0);
1815 }
1816 }
1817 }
1818
1819 /* Free memory heap structures */
1820 radeon_mem_takedown(&(dev_priv->gart_heap));
1821 radeon_mem_takedown(&(dev_priv->fb_heap));
1822
1823 /* deallocate kernel resources */
1824 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1825 r600_do_cleanup_cp(dev);
1826 else
1827 radeon_do_cleanup_cp(dev);
1828 if (dev_priv->me_fw) {
1829 release_firmware(dev_priv->me_fw);
1830 dev_priv->me_fw = NULL;
1831 }
1832 if (dev_priv->pfp_fw) {
1833 release_firmware(dev_priv->pfp_fw);
1834 dev_priv->pfp_fw = NULL;
1835 }
1836 }
1837 }
1838
1839 /* Just reset the CP ring. Called as part of an X Server engine reset.
1840 */
1841 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1842 {
1843 drm_radeon_private_t *dev_priv = dev->dev_private;
1844 DRM_DEBUG("\n");
1845
1846 LOCK_TEST_WITH_RETURN(dev, file_priv);
1847
1848 if (!dev_priv) {
1849 DRM_DEBUG("called before init done\n");
1850 return -EINVAL;
1851 }
1852
1853 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1854 r600_do_cp_reset(dev_priv);
1855 else
1856 radeon_do_cp_reset(dev_priv);
1857
1858 /* The CP is no longer running after an engine reset */
1859 dev_priv->cp_running = 0;
1860
1861 return 0;
1862 }
1863
1864 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1865 {
1866 drm_radeon_private_t *dev_priv = dev->dev_private;
1867 DRM_DEBUG("\n");
1868
1869 LOCK_TEST_WITH_RETURN(dev, file_priv);
1870
1871 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1872 return r600_do_cp_idle(dev_priv);
1873 else
1874 return radeon_do_cp_idle(dev_priv);
1875 }
1876
1877 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1878 */
1879 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1880 {
1881 drm_radeon_private_t *dev_priv = dev->dev_private;
1882 DRM_DEBUG("\n");
1883
1884 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1885 return r600_do_resume_cp(dev, file_priv);
1886 else
1887 return radeon_do_resume_cp(dev, file_priv);
1888 }
1889
1890 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1891 {
1892 drm_radeon_private_t *dev_priv = dev->dev_private;
1893 DRM_DEBUG("\n");
1894
1895 LOCK_TEST_WITH_RETURN(dev, file_priv);
1896
1897 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1898 return r600_do_engine_reset(dev);
1899 else
1900 return radeon_do_engine_reset(dev);
1901 }
1902
1903 /* ================================================================
1904 * Fullscreen mode
1905 */
1906
1907 /* KW: Deprecated to say the least:
1908 */
1909 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1910 {
1911 return 0;
1912 }
1913
1914 /* ================================================================
1915 * Freelist management
1916 */
1917
1918 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1919 * bufs until freelist code is used. Note this hides a problem with
1920 * the scratch register * (used to keep track of last buffer
1921 * completed) being written to before * the last buffer has actually
1922 * completed rendering.
1923 *
1924 * KW: It's also a good way to find free buffers quickly.
1925 *
1926 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1927 * sleep. However, bugs in older versions of radeon_accel.c mean that
1928 * we essentially have to do this, else old clients will break.
1929 *
1930 * However, it does leave open a potential deadlock where all the
1931 * buffers are held by other clients, which can't release them because
1932 * they can't get the lock.
1933 */
1934
1935 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1936 {
1937 struct drm_device_dma *dma = dev->dma;
1938 drm_radeon_private_t *dev_priv = dev->dev_private;
1939 drm_radeon_buf_priv_t *buf_priv;
1940 struct drm_buf *buf;
1941 int i, t;
1942 int start;
1943
1944 if (++dev_priv->last_buf >= dma->buf_count)
1945 dev_priv->last_buf = 0;
1946
1947 start = dev_priv->last_buf;
1948
1949 for (t = 0; t < dev_priv->usec_timeout; t++) {
1950 u32 done_age = GET_SCRATCH(dev_priv, 1);
1951 DRM_DEBUG("done_age = %d\n", done_age);
1952 for (i = 0; i < dma->buf_count; i++) {
1953 buf = dma->buflist[start];
1954 buf_priv = buf->dev_private;
1955 if (buf->file_priv == NULL || (buf->pending &&
1956 buf_priv->age <=
1957 done_age)) {
1958 dev_priv->stats.requested_bufs++;
1959 buf->pending = 0;
1960 return buf;
1961 }
1962 if (++start >= dma->buf_count)
1963 start = 0;
1964 }
1965
1966 if (t) {
1967 DRM_UDELAY(1);
1968 dev_priv->stats.freelist_loops++;
1969 }
1970 }
1971
1972 return NULL;
1973 }
1974
1975 void radeon_freelist_reset(struct drm_device * dev)
1976 {
1977 struct drm_device_dma *dma = dev->dma;
1978 drm_radeon_private_t *dev_priv = dev->dev_private;
1979 int i;
1980
1981 dev_priv->last_buf = 0;
1982 for (i = 0; i < dma->buf_count; i++) {
1983 struct drm_buf *buf = dma->buflist[i];
1984 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1985 buf_priv->age = 0;
1986 }
1987 }
1988
1989 /* ================================================================
1990 * CP command submission
1991 */
1992
1993 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1994 {
1995 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1996 int i;
1997 u32 last_head = GET_RING_HEAD(dev_priv);
1998
1999 for (i = 0; i < dev_priv->usec_timeout; i++) {
2000 u32 head = GET_RING_HEAD(dev_priv);
2001
2002 ring->space = (head - ring->tail) * sizeof(u32);
2003 if (ring->space <= 0)
2004 ring->space += ring->size;
2005 if (ring->space > n)
2006 return 0;
2007
2008 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2009
2010 if (head != last_head)
2011 i = 0;
2012 last_head = head;
2013
2014 DRM_UDELAY(1);
2015 }
2016
2017 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2018 #if RADEON_FIFO_DEBUG
2019 radeon_status(dev_priv);
2020 DRM_ERROR("failed!\n");
2021 #endif
2022 return -EBUSY;
2023 }
2024
2025 static int radeon_cp_get_buffers(struct drm_device *dev,
2026 struct drm_file *file_priv,
2027 struct drm_dma * d)
2028 {
2029 int i;
2030 struct drm_buf *buf;
2031
2032 for (i = d->granted_count; i < d->request_count; i++) {
2033 buf = radeon_freelist_get(dev);
2034 if (!buf)
2035 return -EBUSY; /* NOTE: broken client */
2036
2037 buf->file_priv = file_priv;
2038
2039 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2040 sizeof(buf->idx)))
2041 return -EFAULT;
2042 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2043 sizeof(buf->total)))
2044 return -EFAULT;
2045
2046 d->granted_count++;
2047 }
2048 return 0;
2049 }
2050
2051 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2052 {
2053 struct drm_device_dma *dma = dev->dma;
2054 int ret = 0;
2055 struct drm_dma *d = data;
2056
2057 LOCK_TEST_WITH_RETURN(dev, file_priv);
2058
2059 /* Please don't send us buffers.
2060 */
2061 if (d->send_count != 0) {
2062 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2063 DRM_CURRENTPID, d->send_count);
2064 return -EINVAL;
2065 }
2066
2067 /* We'll send you buffers.
2068 */
2069 if (d->request_count < 0 || d->request_count > dma->buf_count) {
2070 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2071 DRM_CURRENTPID, d->request_count, dma->buf_count);
2072 return -EINVAL;
2073 }
2074
2075 d->granted_count = 0;
2076
2077 if (d->request_count) {
2078 ret = radeon_cp_get_buffers(dev, file_priv, d);
2079 }
2080
2081 return ret;
2082 }
2083
2084 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2085 {
2086 drm_radeon_private_t *dev_priv;
2087 int ret = 0;
2088
2089 dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
2090 if (dev_priv == NULL)
2091 return -ENOMEM;
2092
2093 dev->dev_private = (void *)dev_priv;
2094 dev_priv->flags = flags;
2095
2096 switch (flags & RADEON_FAMILY_MASK) {
2097 case CHIP_R100:
2098 case CHIP_RV200:
2099 case CHIP_R200:
2100 case CHIP_R300:
2101 case CHIP_R350:
2102 case CHIP_R420:
2103 case CHIP_R423:
2104 case CHIP_RV410:
2105 case CHIP_RV515:
2106 case CHIP_R520:
2107 case CHIP_RV570:
2108 case CHIP_R580:
2109 dev_priv->flags |= RADEON_HAS_HIERZ;
2110 break;
2111 default:
2112 /* all other chips have no hierarchical z buffer */
2113 break;
2114 }
2115
2116 if (drm_pci_device_is_agp(dev))
2117 dev_priv->flags |= RADEON_IS_AGP;
2118 else if (pci_is_pcie(dev->pdev))
2119 dev_priv->flags |= RADEON_IS_PCIE;
2120 else
2121 dev_priv->flags |= RADEON_IS_PCI;
2122
2123 ret = drm_addmap(dev, pci_resource_start(dev->pdev, 2),
2124 pci_resource_len(dev->pdev, 2), _DRM_REGISTERS,
2125 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2126 if (ret != 0)
2127 return ret;
2128
2129 ret = drm_vblank_init(dev, 2);
2130 if (ret) {
2131 radeon_driver_unload(dev);
2132 return ret;
2133 }
2134
2135 DRM_DEBUG("%s card detected\n",
2136 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2137 return ret;
2138 }
2139
2140 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2141 {
2142 struct drm_radeon_master_private *master_priv;
2143 unsigned long sareapage;
2144 int ret;
2145
2146 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
2147 if (!master_priv)
2148 return -ENOMEM;
2149
2150 /* prebuild the SAREA */
2151 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2152 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2153 &master_priv->sarea);
2154 if (ret) {
2155 DRM_ERROR("SAREA setup failed\n");
2156 kfree(master_priv);
2157 return ret;
2158 }
2159 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2160 master_priv->sarea_priv->pfCurrentPage = 0;
2161
2162 master->driver_priv = master_priv;
2163 return 0;
2164 }
2165
2166 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2167 {
2168 struct drm_radeon_master_private *master_priv = master->driver_priv;
2169
2170 if (!master_priv)
2171 return;
2172
2173 if (master_priv->sarea_priv &&
2174 master_priv->sarea_priv->pfCurrentPage != 0)
2175 radeon_cp_dispatch_flip(dev, master);
2176
2177 master_priv->sarea_priv = NULL;
2178 if (master_priv->sarea)
2179 drm_rmmap_locked(dev, master_priv->sarea);
2180
2181 kfree(master_priv);
2182
2183 master->driver_priv = NULL;
2184 }
2185
2186 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2187 * have to find them.
2188 */
2189 int radeon_driver_firstopen(struct drm_device *dev)
2190 {
2191 int ret;
2192 drm_local_map_t *map;
2193 drm_radeon_private_t *dev_priv = dev->dev_private;
2194
2195 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2196
2197 dev_priv->fb_aper_offset = pci_resource_start(dev->pdev, 0);
2198 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2199 pci_resource_len(dev->pdev, 0), _DRM_FRAME_BUFFER,
2200 _DRM_WRITE_COMBINING, &map);
2201 if (ret != 0)
2202 return ret;
2203
2204 return 0;
2205 }
2206
2207 int radeon_driver_unload(struct drm_device *dev)
2208 {
2209 drm_radeon_private_t *dev_priv = dev->dev_private;
2210
2211 DRM_DEBUG("\n");
2212
2213 drm_rmmap(dev, dev_priv->mmio);
2214
2215 kfree(dev_priv);
2216
2217 dev->dev_private = NULL;
2218 return 0;
2219 }
2220
2221 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2222 {
2223 int i;
2224 u32 *ring;
2225 int tail_aligned;
2226
2227 /* check if the ring is padded out to 16-dword alignment */
2228
2229 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2230 if (tail_aligned) {
2231 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2232
2233 ring = dev_priv->ring.start;
2234 /* pad with some CP_PACKET2 */
2235 for (i = 0; i < num_p2; i++)
2236 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2237
2238 dev_priv->ring.tail += i;
2239
2240 dev_priv->ring.space -= num_p2 * sizeof(u32);
2241 }
2242
2243 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2244
2245 DRM_MEMORYBARRIER();
2246 GET_RING_HEAD( dev_priv );
2247
2248 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2249 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2250 /* read from PCI bus to ensure correct posting */
2251 RADEON_READ(R600_CP_RB_RPTR);
2252 } else {
2253 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2254 /* read from PCI bus to ensure correct posting */
2255 RADEON_READ(RADEON_CP_RB_RPTR);
2256 }
2257 }
Linux with added FPC-III support