drm/radeon/kms: set DMA mask properly on newer PCI asics
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / rv250d.h
blobe5a70b06fe1fdcc6d3671dbdc765f1595fc7e75b
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
28 #ifndef __RV250D_H__
29 #define __RV250D_H__
31 #define R_00000D_SCLK_CNTL_M6 0x00000D
32 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0)
33 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7)
34 #define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8
35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3)
36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1)
37 #define C_00000D_CP_MAX_DYN_STOP_LAT 0xFFFFFFF7
38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4)
39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1)
40 #define C_00000D_HDP_MAX_DYN_STOP_LAT 0xFFFFFFEF
41 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5)
42 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1)
43 #define C_00000D_TV_MAX_DYN_STOP_LAT 0xFFFFFFDF
44 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6)
45 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1)
46 #define C_00000D_E2_MAX_DYN_STOP_LAT 0xFFFFFFBF
47 #define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7)
48 #define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1)
49 #define C_00000D_SE_MAX_DYN_STOP_LAT 0xFFFFFF7F
50 #define S_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 8)
51 #define G_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 8) & 0x1)
52 #define C_00000D_IDCT_MAX_DYN_STOP_LAT 0xFFFFFEFF
53 #define S_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 9)
54 #define G_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) >> 9) & 0x1)
55 #define C_00000D_VIP_MAX_DYN_STOP_LAT 0xFFFFFDFF
56 #define S_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 10)
57 #define G_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) >> 10) & 0x1)
58 #define C_00000D_RE_MAX_DYN_STOP_LAT 0xFFFFFBFF
59 #define S_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 11)
60 #define G_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) >> 11) & 0x1)
61 #define C_00000D_PB_MAX_DYN_STOP_LAT 0xFFFFF7FF
62 #define S_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 12)
63 #define G_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) >> 12) & 0x1)
64 #define C_00000D_TAM_MAX_DYN_STOP_LAT 0xFFFFEFFF
65 #define S_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 13)
66 #define G_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) >> 13) & 0x1)
67 #define C_00000D_TDM_MAX_DYN_STOP_LAT 0xFFFFDFFF
68 #define S_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 14)
69 #define G_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) >> 14) & 0x1)
70 #define C_00000D_RB_MAX_DYN_STOP_LAT 0xFFFFBFFF
71 #define S_00000D_FORCE_DISP2(x) (((x) & 0x1) << 15)
72 #define G_00000D_FORCE_DISP2(x) (((x) >> 15) & 0x1)
73 #define C_00000D_FORCE_DISP2 0xFFFF7FFF
74 #define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16)
75 #define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1)
76 #define C_00000D_FORCE_CP 0xFFFEFFFF
77 #define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17)
78 #define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1)
79 #define C_00000D_FORCE_HDP 0xFFFDFFFF
80 #define S_00000D_FORCE_DISP1(x) (((x) & 0x1) << 18)
81 #define G_00000D_FORCE_DISP1(x) (((x) >> 18) & 0x1)
82 #define C_00000D_FORCE_DISP1 0xFFFBFFFF
83 #define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19)
84 #define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1)
85 #define C_00000D_FORCE_TOP 0xFFF7FFFF
86 #define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20)
87 #define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1)
88 #define C_00000D_FORCE_E2 0xFFEFFFFF
89 #define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21)
90 #define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1)
91 #define C_00000D_FORCE_SE 0xFFDFFFFF
92 #define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22)
93 #define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1)
94 #define C_00000D_FORCE_IDCT 0xFFBFFFFF
95 #define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23)
96 #define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1)
97 #define C_00000D_FORCE_VIP 0xFF7FFFFF
98 #define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24)
99 #define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1)
100 #define C_00000D_FORCE_RE 0xFEFFFFFF
101 #define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25)
102 #define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1)
103 #define C_00000D_FORCE_PB 0xFDFFFFFF
104 #define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26)
105 #define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1)
106 #define C_00000D_FORCE_TAM 0xFBFFFFFF
107 #define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27)
108 #define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1)
109 #define C_00000D_FORCE_TDM 0xF7FFFFFF
110 #define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28)
111 #define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1)
112 #define C_00000D_FORCE_RB 0xEFFFFFFF
113 #define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29)
114 #define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1)
115 #define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF
116 #define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30)
117 #define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1)
118 #define C_00000D_FORCE_SUBPIC 0xBFFFFFFF
119 #define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31)
120 #define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1)
121 #define C_00000D_FORCE_OV0 0x7FFFFFFF
123 #endif