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drm/radeon/kms: set DMA mask properly on newer PCI asics
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / rv515.c
blob6613ee9ecca331dbcf9db9295667ca70c0817082
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "rv515d.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "atom.h"
35 #include "rv515_reg_safe.h"
36
37 /* This files gather functions specifics to: rv515 */
38 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
39 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
40 void rv515_gpu_init(struct radeon_device *rdev);
41 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
42
43 void rv515_debugfs(struct radeon_device *rdev)
44 {
45 if (r100_debugfs_rbbm_init(rdev)) {
46 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
47 }
48 if (rv515_debugfs_pipes_info_init(rdev)) {
49 DRM_ERROR("Failed to register debugfs file for pipes !\n");
50 }
51 if (rv515_debugfs_ga_info_init(rdev)) {
52 DRM_ERROR("Failed to register debugfs file for pipes !\n");
53 }
54 }
55
56 void rv515_ring_start(struct radeon_device *rdev)
57 {
58 int r;
59
60 r = radeon_ring_lock(rdev, 64);
61 if (r) {
62 return;
63 }
64 radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
65 radeon_ring_write(rdev,
66 ISYNC_ANY2D_IDLE3D |
67 ISYNC_ANY3D_IDLE2D |
68 ISYNC_WAIT_IDLEGUI |
69 ISYNC_CPSCRATCH_IDLEGUI);
70 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
71 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
72 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
73 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
74 radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
75 radeon_ring_write(rdev, 0);
76 radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
77 radeon_ring_write(rdev, 0);
78 radeon_ring_write(rdev, PACKET0(R500_SU_REG_DEST, 0));
79 radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
80 radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
81 radeon_ring_write(rdev, 0);
82 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
83 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
84 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
85 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
86 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
87 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
88 radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
89 radeon_ring_write(rdev, 0);
90 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
91 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
92 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
93 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
94 radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
95 radeon_ring_write(rdev,
96 ((6 << MS_X0_SHIFT) |
97 (6 << MS_Y0_SHIFT) |
98 (6 << MS_X1_SHIFT) |
99 (6 << MS_Y1_SHIFT) |
100 (6 << MS_X2_SHIFT) |
101 (6 << MS_Y2_SHIFT) |
102 (6 << MSBD0_Y_SHIFT) |
103 (6 << MSBD0_X_SHIFT)));
104 radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
105 radeon_ring_write(rdev,
106 ((6 << MS_X3_SHIFT) |
107 (6 << MS_Y3_SHIFT) |
108 (6 << MS_X4_SHIFT) |
109 (6 << MS_Y4_SHIFT) |
110 (6 << MS_X5_SHIFT) |
111 (6 << MS_Y5_SHIFT) |
112 (6 << MSBD1_SHIFT)));
113 radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
114 radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
115 radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
116 radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
117 radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
118 radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
119 radeon_ring_write(rdev, PACKET0(0x20C8, 0));
120 radeon_ring_write(rdev, 0);
121 radeon_ring_unlock_commit(rdev);
122 }
123
124 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
125 {
126 unsigned i;
127 uint32_t tmp;
128
129 for (i = 0; i < rdev->usec_timeout; i++) {
130 /* read MC_STATUS */
131 tmp = RREG32_MC(MC_STATUS);
132 if (tmp & MC_STATUS_IDLE) {
133 return 0;
134 }
135 DRM_UDELAY(1);
136 }
137 return -1;
138 }
139
140 void rv515_vga_render_disable(struct radeon_device *rdev)
141 {
142 WREG32(R_000300_VGA_RENDER_CONTROL,
143 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
144 }
145
146 void rv515_gpu_init(struct radeon_device *rdev)
147 {
148 unsigned pipe_select_current, gb_pipe_select, tmp;
149
150 if (r100_gui_wait_for_idle(rdev)) {
151 printk(KERN_WARNING "Failed to wait GUI idle while "
152 "reseting GPU. Bad things might happen.\n");
153 }
154 rv515_vga_render_disable(rdev);
155 r420_pipes_init(rdev);
156 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
157 tmp = RREG32(R300_DST_PIPE_CONFIG);
158 pipe_select_current = (tmp >> 2) & 3;
159 tmp = (1 << pipe_select_current) |
160 (((gb_pipe_select >> 8) & 0xF) << 4);
161 WREG32_PLL(0x000D, tmp);
162 if (r100_gui_wait_for_idle(rdev)) {
163 printk(KERN_WARNING "Failed to wait GUI idle while "
164 "reseting GPU. Bad things might happen.\n");
165 }
166 if (rv515_mc_wait_for_idle(rdev)) {
167 printk(KERN_WARNING "Failed to wait MC idle while "
168 "programming pipes. Bad things might happen.\n");
169 }
170 }
171
172 static void rv515_vram_get_type(struct radeon_device *rdev)
173 {
174 uint32_t tmp;
175
176 rdev->mc.vram_width = 128;
177 rdev->mc.vram_is_ddr = true;
178 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
179 switch (tmp) {
180 case 0:
181 rdev->mc.vram_width = 64;
182 break;
183 case 1:
184 rdev->mc.vram_width = 128;
185 break;
186 default:
187 rdev->mc.vram_width = 128;
188 break;
189 }
190 }
191
192 void rv515_mc_init(struct radeon_device *rdev)
193 {
194
195 rv515_vram_get_type(rdev);
196 r100_vram_init_sizes(rdev);
197 radeon_vram_location(rdev, &rdev->mc, 0);
198 rdev->mc.gtt_base_align = 0;
199 if (!(rdev->flags & RADEON_IS_AGP))
200 radeon_gtt_location(rdev, &rdev->mc);
201 radeon_update_bandwidth_info(rdev);
202 }
203
204 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
205 {
206 uint32_t r;
207
208 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
209 r = RREG32(MC_IND_DATA);
210 WREG32(MC_IND_INDEX, 0);
211 return r;
212 }
213
214 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
215 {
216 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
217 WREG32(MC_IND_DATA, (v));
218 WREG32(MC_IND_INDEX, 0);
219 }
220
221 #if defined(CONFIG_DEBUG_FS)
222 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
223 {
224 struct drm_info_node *node = (struct drm_info_node *) m->private;
225 struct drm_device *dev = node->minor->dev;
226 struct radeon_device *rdev = dev->dev_private;
227 uint32_t tmp;
228
229 tmp = RREG32(GB_PIPE_SELECT);
230 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
231 tmp = RREG32(SU_REG_DEST);
232 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
233 tmp = RREG32(GB_TILE_CONFIG);
234 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
235 tmp = RREG32(DST_PIPE_CONFIG);
236 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
237 return 0;
238 }
239
240 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
241 {
242 struct drm_info_node *node = (struct drm_info_node *) m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct radeon_device *rdev = dev->dev_private;
245 uint32_t tmp;
246
247 tmp = RREG32(0x2140);
248 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
249 radeon_asic_reset(rdev);
250 tmp = RREG32(0x425C);
251 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
252 return 0;
253 }
254
255 static struct drm_info_list rv515_pipes_info_list[] = {
256 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
257 };
258
259 static struct drm_info_list rv515_ga_info_list[] = {
260 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
261 };
262 #endif
263
264 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
265 {
266 #if defined(CONFIG_DEBUG_FS)
267 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
268 #else
269 return 0;
270 #endif
271 }
272
273 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
274 {
275 #if defined(CONFIG_DEBUG_FS)
276 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
277 #else
278 return 0;
279 #endif
280 }
281
282 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
283 {
284 save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
285 save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
286 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
287 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
288 save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
289 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
290
291 /* Stop all video */
292 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
293 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
294 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
295 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
296 WREG32(R_006080_D1CRTC_CONTROL, 0);
297 WREG32(R_006880_D2CRTC_CONTROL, 0);
298 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
299 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
300 WREG32(R_000330_D1VGA_CONTROL, 0);
301 WREG32(R_000338_D2VGA_CONTROL, 0);
302 }
303
304 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
305 {
306 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
307 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
308 WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
309 WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
310 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
311 /* Unlock host access */
312 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
313 mdelay(1);
314 /* Restore video state */
315 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
316 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
317 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
318 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
319 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
320 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
321 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
322 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
323 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
324 }
325
326 void rv515_mc_program(struct radeon_device *rdev)
327 {
328 struct rv515_mc_save save;
329
330 /* Stops all mc clients */
331 rv515_mc_stop(rdev, &save);
332
333 /* Wait for mc idle */
334 if (rv515_mc_wait_for_idle(rdev))
335 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
336 /* Write VRAM size in case we are limiting it */
337 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
338 /* Program MC, should be a 32bits limited address space */
339 WREG32_MC(R_000001_MC_FB_LOCATION,
340 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
341 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
342 WREG32(R_000134_HDP_FB_LOCATION,
343 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
344 if (rdev->flags & RADEON_IS_AGP) {
345 WREG32_MC(R_000002_MC_AGP_LOCATION,
346 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
347 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
348 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
349 WREG32_MC(R_000004_MC_AGP_BASE_2,
350 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
351 } else {
352 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
353 WREG32_MC(R_000003_MC_AGP_BASE, 0);
354 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
355 }
356
357 rv515_mc_resume(rdev, &save);
358 }
359
360 void rv515_clock_startup(struct radeon_device *rdev)
361 {
362 if (radeon_dynclks != -1 && radeon_dynclks)
363 radeon_atom_set_clock_gating(rdev, 1);
364 /* We need to force on some of the block */
365 WREG32_PLL(R_00000F_CP_DYN_CNTL,
366 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
367 WREG32_PLL(R_000011_E2_DYN_CNTL,
368 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
369 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
370 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
371 }
372
373 static int rv515_startup(struct radeon_device *rdev)
374 {
375 int r;
376
377 rv515_mc_program(rdev);
378 /* Resume clock */
379 rv515_clock_startup(rdev);
380 /* Initialize GPU configuration (# pipes, ...) */
381 rv515_gpu_init(rdev);
382 /* Initialize GART (initialize after TTM so we can allocate
383 * memory through TTM but finalize after TTM) */
384 if (rdev->flags & RADEON_IS_PCIE) {
385 r = rv370_pcie_gart_enable(rdev);
386 if (r)
387 return r;
388 }
389
390 /* allocate wb buffer */
391 r = radeon_wb_init(rdev);
392 if (r)
393 return r;
394
395 /* Enable IRQ */
396 rs600_irq_set(rdev);
397 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
398 /* 1M ring buffer */
399 r = r100_cp_init(rdev, 1024 * 1024);
400 if (r) {
401 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
402 return r;
403 }
404 r = r100_ib_init(rdev);
405 if (r) {
406 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
407 return r;
408 }
409 return 0;
410 }
411
412 int rv515_resume(struct radeon_device *rdev)
413 {
414 /* Make sur GART are not working */
415 if (rdev->flags & RADEON_IS_PCIE)
416 rv370_pcie_gart_disable(rdev);
417 /* Resume clock before doing reset */
418 rv515_clock_startup(rdev);
419 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
420 if (radeon_asic_reset(rdev)) {
421 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
422 RREG32(R_000E40_RBBM_STATUS),
423 RREG32(R_0007C0_CP_STAT));
424 }
425 /* post */
426 atom_asic_init(rdev->mode_info.atom_context);
427 /* Resume clock after posting */
428 rv515_clock_startup(rdev);
429 /* Initialize surface registers */
430 radeon_surface_init(rdev);
431 return rv515_startup(rdev);
432 }
433
434 int rv515_suspend(struct radeon_device *rdev)
435 {
436 r100_cp_disable(rdev);
437 radeon_wb_disable(rdev);
438 rs600_irq_disable(rdev);
439 if (rdev->flags & RADEON_IS_PCIE)
440 rv370_pcie_gart_disable(rdev);
441 return 0;
442 }
443
444 void rv515_set_safe_registers(struct radeon_device *rdev)
445 {
446 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
447 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
448 }
449
450 void rv515_fini(struct radeon_device *rdev)
451 {
452 r100_cp_fini(rdev);
453 radeon_wb_fini(rdev);
454 r100_ib_fini(rdev);
455 radeon_gem_fini(rdev);
456 rv370_pcie_gart_fini(rdev);
457 radeon_agp_fini(rdev);
458 radeon_irq_kms_fini(rdev);
459 radeon_fence_driver_fini(rdev);
460 radeon_bo_fini(rdev);
461 radeon_atombios_fini(rdev);
462 kfree(rdev->bios);
463 rdev->bios = NULL;
464 }
465
466 int rv515_init(struct radeon_device *rdev)
467 {
468 int r;
469
470 /* Initialize scratch registers */
471 radeon_scratch_init(rdev);
472 /* Initialize surface registers */
473 radeon_surface_init(rdev);
474 /* TODO: disable VGA need to use VGA request */
475 /* restore some register to sane defaults */
476 r100_restore_sanity(rdev);
477 /* BIOS*/
478 if (!radeon_get_bios(rdev)) {
479 if (ASIC_IS_AVIVO(rdev))
480 return -EINVAL;
481 }
482 if (rdev->is_atom_bios) {
483 r = radeon_atombios_init(rdev);
484 if (r)
485 return r;
486 } else {
487 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
488 return -EINVAL;
489 }
490 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
491 if (radeon_asic_reset(rdev)) {
492 dev_warn(rdev->dev,
493 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
494 RREG32(R_000E40_RBBM_STATUS),
495 RREG32(R_0007C0_CP_STAT));
496 }
497 /* check if cards are posted or not */
498 if (radeon_boot_test_post_card(rdev) == false)
499 return -EINVAL;
500 /* Initialize clocks */
501 radeon_get_clock_info(rdev->ddev);
502 /* initialize AGP */
503 if (rdev->flags & RADEON_IS_AGP) {
504 r = radeon_agp_init(rdev);
505 if (r) {
506 radeon_agp_disable(rdev);
507 }
508 }
509 /* initialize memory controller */
510 rv515_mc_init(rdev);
511 rv515_debugfs(rdev);
512 /* Fence driver */
513 r = radeon_fence_driver_init(rdev);
514 if (r)
515 return r;
516 r = radeon_irq_kms_init(rdev);
517 if (r)
518 return r;
519 /* Memory manager */
520 r = radeon_bo_init(rdev);
521 if (r)
522 return r;
523 r = rv370_pcie_gart_init(rdev);
524 if (r)
525 return r;
526 rv515_set_safe_registers(rdev);
527 rdev->accel_working = true;
528 r = rv515_startup(rdev);
529 if (r) {
530 /* Somethings want wront with the accel init stop accel */
531 dev_err(rdev->dev, "Disabling GPU acceleration\n");
532 r100_cp_fini(rdev);
533 radeon_wb_fini(rdev);
534 r100_ib_fini(rdev);
535 radeon_irq_kms_fini(rdev);
536 rv370_pcie_gart_fini(rdev);
537 radeon_agp_fini(rdev);
538 rdev->accel_working = false;
539 }
540 return 0;
541 }
542
543 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
544 {
545 int index_reg = 0x6578 + crtc->crtc_offset;
546 int data_reg = 0x657c + crtc->crtc_offset;
547
548 WREG32(0x659C + crtc->crtc_offset, 0x0);
549 WREG32(0x6594 + crtc->crtc_offset, 0x705);
550 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
551 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
552 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
553 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
554 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
555 WREG32(index_reg, 0x0);
556 WREG32(data_reg, 0x841880A8);
557 WREG32(index_reg, 0x1);
558 WREG32(data_reg, 0x84208680);
559 WREG32(index_reg, 0x2);
560 WREG32(data_reg, 0xBFF880B0);
561 WREG32(index_reg, 0x100);
562 WREG32(data_reg, 0x83D88088);
563 WREG32(index_reg, 0x101);
564 WREG32(data_reg, 0x84608680);
565 WREG32(index_reg, 0x102);
566 WREG32(data_reg, 0xBFF080D0);
567 WREG32(index_reg, 0x200);
568 WREG32(data_reg, 0x83988068);
569 WREG32(index_reg, 0x201);
570 WREG32(data_reg, 0x84A08680);
571 WREG32(index_reg, 0x202);
572 WREG32(data_reg, 0xBFF080F8);
573 WREG32(index_reg, 0x300);
574 WREG32(data_reg, 0x83588058);
575 WREG32(index_reg, 0x301);
576 WREG32(data_reg, 0x84E08660);
577 WREG32(index_reg, 0x302);
578 WREG32(data_reg, 0xBFF88120);
579 WREG32(index_reg, 0x400);
580 WREG32(data_reg, 0x83188040);
581 WREG32(index_reg, 0x401);
582 WREG32(data_reg, 0x85008660);
583 WREG32(index_reg, 0x402);
584 WREG32(data_reg, 0xBFF88150);
585 WREG32(index_reg, 0x500);
586 WREG32(data_reg, 0x82D88030);
587 WREG32(index_reg, 0x501);
588 WREG32(data_reg, 0x85408640);
589 WREG32(index_reg, 0x502);
590 WREG32(data_reg, 0xBFF88180);
591 WREG32(index_reg, 0x600);
592 WREG32(data_reg, 0x82A08018);
593 WREG32(index_reg, 0x601);
594 WREG32(data_reg, 0x85808620);
595 WREG32(index_reg, 0x602);
596 WREG32(data_reg, 0xBFF081B8);
597 WREG32(index_reg, 0x700);
598 WREG32(data_reg, 0x82608010);
599 WREG32(index_reg, 0x701);
600 WREG32(data_reg, 0x85A08600);
601 WREG32(index_reg, 0x702);
602 WREG32(data_reg, 0x800081F0);
603 WREG32(index_reg, 0x800);
604 WREG32(data_reg, 0x8228BFF8);
605 WREG32(index_reg, 0x801);
606 WREG32(data_reg, 0x85E085E0);
607 WREG32(index_reg, 0x802);
608 WREG32(data_reg, 0xBFF88228);
609 WREG32(index_reg, 0x10000);
610 WREG32(data_reg, 0x82A8BF00);
611 WREG32(index_reg, 0x10001);
612 WREG32(data_reg, 0x82A08CC0);
613 WREG32(index_reg, 0x10002);
614 WREG32(data_reg, 0x8008BEF8);
615 WREG32(index_reg, 0x10100);
616 WREG32(data_reg, 0x81F0BF28);
617 WREG32(index_reg, 0x10101);
618 WREG32(data_reg, 0x83608CA0);
619 WREG32(index_reg, 0x10102);
620 WREG32(data_reg, 0x8018BED0);
621 WREG32(index_reg, 0x10200);
622 WREG32(data_reg, 0x8148BF38);
623 WREG32(index_reg, 0x10201);
624 WREG32(data_reg, 0x84408C80);
625 WREG32(index_reg, 0x10202);
626 WREG32(data_reg, 0x8008BEB8);
627 WREG32(index_reg, 0x10300);
628 WREG32(data_reg, 0x80B0BF78);
629 WREG32(index_reg, 0x10301);
630 WREG32(data_reg, 0x85008C20);
631 WREG32(index_reg, 0x10302);
632 WREG32(data_reg, 0x8020BEA0);
633 WREG32(index_reg, 0x10400);
634 WREG32(data_reg, 0x8028BF90);
635 WREG32(index_reg, 0x10401);
636 WREG32(data_reg, 0x85E08BC0);
637 WREG32(index_reg, 0x10402);
638 WREG32(data_reg, 0x8018BE90);
639 WREG32(index_reg, 0x10500);
640 WREG32(data_reg, 0xBFB8BFB0);
641 WREG32(index_reg, 0x10501);
642 WREG32(data_reg, 0x86C08B40);
643 WREG32(index_reg, 0x10502);
644 WREG32(data_reg, 0x8010BE90);
645 WREG32(index_reg, 0x10600);
646 WREG32(data_reg, 0xBF58BFC8);
647 WREG32(index_reg, 0x10601);
648 WREG32(data_reg, 0x87A08AA0);
649 WREG32(index_reg, 0x10602);
650 WREG32(data_reg, 0x8010BE98);
651 WREG32(index_reg, 0x10700);
652 WREG32(data_reg, 0xBF10BFF0);
653 WREG32(index_reg, 0x10701);
654 WREG32(data_reg, 0x886089E0);
655 WREG32(index_reg, 0x10702);
656 WREG32(data_reg, 0x8018BEB0);
657 WREG32(index_reg, 0x10800);
658 WREG32(data_reg, 0xBED8BFE8);
659 WREG32(index_reg, 0x10801);
660 WREG32(data_reg, 0x89408940);
661 WREG32(index_reg, 0x10802);
662 WREG32(data_reg, 0xBFE8BED8);
663 WREG32(index_reg, 0x20000);
664 WREG32(data_reg, 0x80008000);
665 WREG32(index_reg, 0x20001);
666 WREG32(data_reg, 0x90008000);
667 WREG32(index_reg, 0x20002);
668 WREG32(data_reg, 0x80008000);
669 WREG32(index_reg, 0x20003);
670 WREG32(data_reg, 0x80008000);
671 WREG32(index_reg, 0x20100);
672 WREG32(data_reg, 0x80108000);
673 WREG32(index_reg, 0x20101);
674 WREG32(data_reg, 0x8FE0BF70);
675 WREG32(index_reg, 0x20102);
676 WREG32(data_reg, 0xBFE880C0);
677 WREG32(index_reg, 0x20103);
678 WREG32(data_reg, 0x80008000);
679 WREG32(index_reg, 0x20200);
680 WREG32(data_reg, 0x8018BFF8);
681 WREG32(index_reg, 0x20201);
682 WREG32(data_reg, 0x8F80BF08);
683 WREG32(index_reg, 0x20202);
684 WREG32(data_reg, 0xBFD081A0);
685 WREG32(index_reg, 0x20203);
686 WREG32(data_reg, 0xBFF88000);
687 WREG32(index_reg, 0x20300);
688 WREG32(data_reg, 0x80188000);
689 WREG32(index_reg, 0x20301);
690 WREG32(data_reg, 0x8EE0BEC0);
691 WREG32(index_reg, 0x20302);
692 WREG32(data_reg, 0xBFB082A0);
693 WREG32(index_reg, 0x20303);
694 WREG32(data_reg, 0x80008000);
695 WREG32(index_reg, 0x20400);
696 WREG32(data_reg, 0x80188000);
697 WREG32(index_reg, 0x20401);
698 WREG32(data_reg, 0x8E00BEA0);
699 WREG32(index_reg, 0x20402);
700 WREG32(data_reg, 0xBF8883C0);
701 WREG32(index_reg, 0x20403);
702 WREG32(data_reg, 0x80008000);
703 WREG32(index_reg, 0x20500);
704 WREG32(data_reg, 0x80188000);
705 WREG32(index_reg, 0x20501);
706 WREG32(data_reg, 0x8D00BE90);
707 WREG32(index_reg, 0x20502);
708 WREG32(data_reg, 0xBF588500);
709 WREG32(index_reg, 0x20503);
710 WREG32(data_reg, 0x80008008);
711 WREG32(index_reg, 0x20600);
712 WREG32(data_reg, 0x80188000);
713 WREG32(index_reg, 0x20601);
714 WREG32(data_reg, 0x8BC0BE98);
715 WREG32(index_reg, 0x20602);
716 WREG32(data_reg, 0xBF308660);
717 WREG32(index_reg, 0x20603);
718 WREG32(data_reg, 0x80008008);
719 WREG32(index_reg, 0x20700);
720 WREG32(data_reg, 0x80108000);
721 WREG32(index_reg, 0x20701);
722 WREG32(data_reg, 0x8A80BEB0);
723 WREG32(index_reg, 0x20702);
724 WREG32(data_reg, 0xBF0087C0);
725 WREG32(index_reg, 0x20703);
726 WREG32(data_reg, 0x80008008);
727 WREG32(index_reg, 0x20800);
728 WREG32(data_reg, 0x80108000);
729 WREG32(index_reg, 0x20801);
730 WREG32(data_reg, 0x8920BED0);
731 WREG32(index_reg, 0x20802);
732 WREG32(data_reg, 0xBED08920);
733 WREG32(index_reg, 0x20803);
734 WREG32(data_reg, 0x80008010);
735 WREG32(index_reg, 0x30000);
736 WREG32(data_reg, 0x90008000);
737 WREG32(index_reg, 0x30001);
738 WREG32(data_reg, 0x80008000);
739 WREG32(index_reg, 0x30100);
740 WREG32(data_reg, 0x8FE0BF90);
741 WREG32(index_reg, 0x30101);
742 WREG32(data_reg, 0xBFF880A0);
743 WREG32(index_reg, 0x30200);
744 WREG32(data_reg, 0x8F60BF40);
745 WREG32(index_reg, 0x30201);
746 WREG32(data_reg, 0xBFE88180);
747 WREG32(index_reg, 0x30300);
748 WREG32(data_reg, 0x8EC0BF00);
749 WREG32(index_reg, 0x30301);
750 WREG32(data_reg, 0xBFC88280);
751 WREG32(index_reg, 0x30400);
752 WREG32(data_reg, 0x8DE0BEE0);
753 WREG32(index_reg, 0x30401);
754 WREG32(data_reg, 0xBFA083A0);
755 WREG32(index_reg, 0x30500);
756 WREG32(data_reg, 0x8CE0BED0);
757 WREG32(index_reg, 0x30501);
758 WREG32(data_reg, 0xBF7884E0);
759 WREG32(index_reg, 0x30600);
760 WREG32(data_reg, 0x8BA0BED8);
761 WREG32(index_reg, 0x30601);
762 WREG32(data_reg, 0xBF508640);
763 WREG32(index_reg, 0x30700);
764 WREG32(data_reg, 0x8A60BEE8);
765 WREG32(index_reg, 0x30701);
766 WREG32(data_reg, 0xBF2087A0);
767 WREG32(index_reg, 0x30800);
768 WREG32(data_reg, 0x8900BF00);
769 WREG32(index_reg, 0x30801);
770 WREG32(data_reg, 0xBF008900);
771 }
772
773 struct rv515_watermark {
774 u32 lb_request_fifo_depth;
775 fixed20_12 num_line_pair;
776 fixed20_12 estimated_width;
777 fixed20_12 worst_case_latency;
778 fixed20_12 consumption_rate;
779 fixed20_12 active_time;
780 fixed20_12 dbpp;
781 fixed20_12 priority_mark_max;
782 fixed20_12 priority_mark;
783 fixed20_12 sclk;
784 };
785
786 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
787 struct radeon_crtc *crtc,
788 struct rv515_watermark *wm)
789 {
790 struct drm_display_mode *mode = &crtc->base.mode;
791 fixed20_12 a, b, c;
792 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
793 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
794
795 if (!crtc->base.enabled) {
796 /* FIXME: wouldn't it better to set priority mark to maximum */
797 wm->lb_request_fifo_depth = 4;
798 return;
799 }
800
801 if (crtc->vsc.full > dfixed_const(2))
802 wm->num_line_pair.full = dfixed_const(2);
803 else
804 wm->num_line_pair.full = dfixed_const(1);
805
806 b.full = dfixed_const(mode->crtc_hdisplay);
807 c.full = dfixed_const(256);
808 a.full = dfixed_div(b, c);
809 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
810 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
811 if (a.full < dfixed_const(4)) {
812 wm->lb_request_fifo_depth = 4;
813 } else {
814 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
815 }
816
817 /* Determine consumption rate
818 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
819 * vtaps = number of vertical taps,
820 * vsc = vertical scaling ratio, defined as source/destination
821 * hsc = horizontal scaling ration, defined as source/destination
822 */
823 a.full = dfixed_const(mode->clock);
824 b.full = dfixed_const(1000);
825 a.full = dfixed_div(a, b);
826 pclk.full = dfixed_div(b, a);
827 if (crtc->rmx_type != RMX_OFF) {
828 b.full = dfixed_const(2);
829 if (crtc->vsc.full > b.full)
830 b.full = crtc->vsc.full;
831 b.full = dfixed_mul(b, crtc->hsc);
832 c.full = dfixed_const(2);
833 b.full = dfixed_div(b, c);
834 consumption_time.full = dfixed_div(pclk, b);
835 } else {
836 consumption_time.full = pclk.full;
837 }
838 a.full = dfixed_const(1);
839 wm->consumption_rate.full = dfixed_div(a, consumption_time);
840
841
842 /* Determine line time
843 * LineTime = total time for one line of displayhtotal
844 * LineTime = total number of horizontal pixels
845 * pclk = pixel clock period(ns)
846 */
847 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
848 line_time.full = dfixed_mul(a, pclk);
849
850 /* Determine active time
851 * ActiveTime = time of active region of display within one line,
852 * hactive = total number of horizontal active pixels
853 * htotal = total number of horizontal pixels
854 */
855 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
856 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
857 wm->active_time.full = dfixed_mul(line_time, b);
858 wm->active_time.full = dfixed_div(wm->active_time, a);
859
860 /* Determine chunk time
861 * ChunkTime = the time it takes the DCP to send one chunk of data
862 * to the LB which consists of pipeline delay and inter chunk gap
863 * sclk = system clock(Mhz)
864 */
865 a.full = dfixed_const(600 * 1000);
866 chunk_time.full = dfixed_div(a, rdev->pm.sclk);
867 read_delay_latency.full = dfixed_const(1000);
868
869 /* Determine the worst case latency
870 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
871 * WorstCaseLatency = worst case time from urgent to when the MC starts
872 * to return data
873 * READ_DELAY_IDLE_MAX = constant of 1us
874 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
875 * which consists of pipeline delay and inter chunk gap
876 */
877 if (dfixed_trunc(wm->num_line_pair) > 1) {
878 a.full = dfixed_const(3);
879 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
880 wm->worst_case_latency.full += read_delay_latency.full;
881 } else {
882 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
883 }
884
885 /* Determine the tolerable latency
886 * TolerableLatency = Any given request has only 1 line time
887 * for the data to be returned
888 * LBRequestFifoDepth = Number of chunk requests the LB can
889 * put into the request FIFO for a display
890 * LineTime = total time for one line of display
891 * ChunkTime = the time it takes the DCP to send one chunk
892 * of data to the LB which consists of
893 * pipeline delay and inter chunk gap
894 */
895 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
896 tolerable_latency.full = line_time.full;
897 } else {
898 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
899 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
900 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
901 tolerable_latency.full = line_time.full - tolerable_latency.full;
902 }
903 /* We assume worst case 32bits (4 bytes) */
904 wm->dbpp.full = dfixed_const(2 * 16);
905
906 /* Determine the maximum priority mark
907 * width = viewport width in pixels
908 */
909 a.full = dfixed_const(16);
910 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
911 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
912 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
913
914 /* Determine estimated width */
915 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
916 estimated_width.full = dfixed_div(estimated_width, consumption_time);
917 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
918 wm->priority_mark.full = wm->priority_mark_max.full;
919 } else {
920 a.full = dfixed_const(16);
921 wm->priority_mark.full = dfixed_div(estimated_width, a);
922 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
923 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
924 }
925 }
926
927 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
928 {
929 struct drm_display_mode *mode0 = NULL;
930 struct drm_display_mode *mode1 = NULL;
931 struct rv515_watermark wm0;
932 struct rv515_watermark wm1;
933 u32 tmp;
934 u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
935 u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
936 fixed20_12 priority_mark02, priority_mark12, fill_rate;
937 fixed20_12 a, b;
938
939 if (rdev->mode_info.crtcs[0]->base.enabled)
940 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
941 if (rdev->mode_info.crtcs[1]->base.enabled)
942 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
943 rs690_line_buffer_adjust(rdev, mode0, mode1);
944
945 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
946 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
947
948 tmp = wm0.lb_request_fifo_depth;
949 tmp |= wm1.lb_request_fifo_depth << 16;
950 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
951
952 if (mode0 && mode1) {
953 if (dfixed_trunc(wm0.dbpp) > 64)
954 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
955 else
956 a.full = wm0.num_line_pair.full;
957 if (dfixed_trunc(wm1.dbpp) > 64)
958 b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
959 else
960 b.full = wm1.num_line_pair.full;
961 a.full += b.full;
962 fill_rate.full = dfixed_div(wm0.sclk, a);
963 if (wm0.consumption_rate.full > fill_rate.full) {
964 b.full = wm0.consumption_rate.full - fill_rate.full;
965 b.full = dfixed_mul(b, wm0.active_time);
966 a.full = dfixed_const(16);
967 b.full = dfixed_div(b, a);
968 a.full = dfixed_mul(wm0.worst_case_latency,
969 wm0.consumption_rate);
970 priority_mark02.full = a.full + b.full;
971 } else {
972 a.full = dfixed_mul(wm0.worst_case_latency,
973 wm0.consumption_rate);
974 b.full = dfixed_const(16 * 1000);
975 priority_mark02.full = dfixed_div(a, b);
976 }
977 if (wm1.consumption_rate.full > fill_rate.full) {
978 b.full = wm1.consumption_rate.full - fill_rate.full;
979 b.full = dfixed_mul(b, wm1.active_time);
980 a.full = dfixed_const(16);
981 b.full = dfixed_div(b, a);
982 a.full = dfixed_mul(wm1.worst_case_latency,
983 wm1.consumption_rate);
984 priority_mark12.full = a.full + b.full;
985 } else {
986 a.full = dfixed_mul(wm1.worst_case_latency,
987 wm1.consumption_rate);
988 b.full = dfixed_const(16 * 1000);
989 priority_mark12.full = dfixed_div(a, b);
990 }
991 if (wm0.priority_mark.full > priority_mark02.full)
992 priority_mark02.full = wm0.priority_mark.full;
993 if (dfixed_trunc(priority_mark02) < 0)
994 priority_mark02.full = 0;
995 if (wm0.priority_mark_max.full > priority_mark02.full)
996 priority_mark02.full = wm0.priority_mark_max.full;
997 if (wm1.priority_mark.full > priority_mark12.full)
998 priority_mark12.full = wm1.priority_mark.full;
999 if (dfixed_trunc(priority_mark12) < 0)
1000 priority_mark12.full = 0;
1001 if (wm1.priority_mark_max.full > priority_mark12.full)
1002 priority_mark12.full = wm1.priority_mark_max.full;
1003 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1004 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1005 if (rdev->disp_priority == 2) {
1006 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1007 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1008 }
1009 } else if (mode0) {
1010 if (dfixed_trunc(wm0.dbpp) > 64)
1011 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
1012 else
1013 a.full = wm0.num_line_pair.full;
1014 fill_rate.full = dfixed_div(wm0.sclk, a);
1015 if (wm0.consumption_rate.full > fill_rate.full) {
1016 b.full = wm0.consumption_rate.full - fill_rate.full;
1017 b.full = dfixed_mul(b, wm0.active_time);
1018 a.full = dfixed_const(16);
1019 b.full = dfixed_div(b, a);
1020 a.full = dfixed_mul(wm0.worst_case_latency,
1021 wm0.consumption_rate);
1022 priority_mark02.full = a.full + b.full;
1023 } else {
1024 a.full = dfixed_mul(wm0.worst_case_latency,
1025 wm0.consumption_rate);
1026 b.full = dfixed_const(16);
1027 priority_mark02.full = dfixed_div(a, b);
1028 }
1029 if (wm0.priority_mark.full > priority_mark02.full)
1030 priority_mark02.full = wm0.priority_mark.full;
1031 if (dfixed_trunc(priority_mark02) < 0)
1032 priority_mark02.full = 0;
1033 if (wm0.priority_mark_max.full > priority_mark02.full)
1034 priority_mark02.full = wm0.priority_mark_max.full;
1035 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1036 if (rdev->disp_priority == 2)
1037 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1038 } else if (mode1) {
1039 if (dfixed_trunc(wm1.dbpp) > 64)
1040 a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
1041 else
1042 a.full = wm1.num_line_pair.full;
1043 fill_rate.full = dfixed_div(wm1.sclk, a);
1044 if (wm1.consumption_rate.full > fill_rate.full) {
1045 b.full = wm1.consumption_rate.full - fill_rate.full;
1046 b.full = dfixed_mul(b, wm1.active_time);
1047 a.full = dfixed_const(16);
1048 b.full = dfixed_div(b, a);
1049 a.full = dfixed_mul(wm1.worst_case_latency,
1050 wm1.consumption_rate);
1051 priority_mark12.full = a.full + b.full;
1052 } else {
1053 a.full = dfixed_mul(wm1.worst_case_latency,
1054 wm1.consumption_rate);
1055 b.full = dfixed_const(16 * 1000);
1056 priority_mark12.full = dfixed_div(a, b);
1057 }
1058 if (wm1.priority_mark.full > priority_mark12.full)
1059 priority_mark12.full = wm1.priority_mark.full;
1060 if (dfixed_trunc(priority_mark12) < 0)
1061 priority_mark12.full = 0;
1062 if (wm1.priority_mark_max.full > priority_mark12.full)
1063 priority_mark12.full = wm1.priority_mark_max.full;
1064 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1065 if (rdev->disp_priority == 2)
1066 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1067 }
1068
1069 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1070 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1071 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1072 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1073 }
1074
1075 void rv515_bandwidth_update(struct radeon_device *rdev)
1076 {
1077 uint32_t tmp;
1078 struct drm_display_mode *mode0 = NULL;
1079 struct drm_display_mode *mode1 = NULL;
1080
1081 radeon_update_display_priority(rdev);
1082
1083 if (rdev->mode_info.crtcs[0]->base.enabled)
1084 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1085 if (rdev->mode_info.crtcs[1]->base.enabled)
1086 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1087 /*
1088 * Set display0/1 priority up in the memory controller for
1089 * modes if the user specifies HIGH for displaypriority
1090 * option.
1091 */
1092 if ((rdev->disp_priority == 2) &&
1093 (rdev->family == CHIP_RV515)) {
1094 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1095 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1096 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1097 if (mode1)
1098 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1099 if (mode0)
1100 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1101 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1102 }
1103 rv515_bandwidth_avivo_update(rdev);
1104 }
Linux with added FPC-III support