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drm/radeon/kms: set DMA mask properly on newer PCI asics
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / rv770.c
blob80928f9ff80f7bd2a6b7545c70d79773d57aaef8
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/firmware.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
31 #include "drmP.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "radeon_drm.h"
35 #include "rv770d.h"
36 #include "atom.h"
37 #include "avivod.h"
38
39 #define R700_PFP_UCODE_SIZE 848
40 #define R700_PM4_UCODE_SIZE 1360
41
42 static void rv770_gpu_init(struct radeon_device *rdev);
43 void rv770_fini(struct radeon_device *rdev);
44 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
45
46 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
47 {
48 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
49 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
50
51 /* Lock the graphics update lock */
52 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
53 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
54
55 /* update the scanout addresses */
56 if (radeon_crtc->crtc_id) {
57 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
58 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
59 } else {
60 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
61 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
62 }
63 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
64 (u32)crtc_base);
65 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
66 (u32)crtc_base);
67
68 /* Wait for update_pending to go high. */
69 while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING));
70 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
71
72 /* Unlock the lock, so double-buffering can take place inside vblank */
73 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
74 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
75
76 /* Return current update_pending status: */
77 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
78 }
79
80 /* get temperature in millidegrees */
81 int rv770_get_temp(struct radeon_device *rdev)
82 {
83 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
84 ASIC_T_SHIFT;
85 int actual_temp;
86
87 if (temp & 0x400)
88 actual_temp = -256;
89 else if (temp & 0x200)
90 actual_temp = 255;
91 else if (temp & 0x100) {
92 actual_temp = temp & 0x1ff;
93 actual_temp |= ~0x1ff;
94 } else
95 actual_temp = temp & 0xff;
96
97 return (actual_temp * 1000) / 2;
98 }
99
100 void rv770_pm_misc(struct radeon_device *rdev)
101 {
102 int req_ps_idx = rdev->pm.requested_power_state_index;
103 int req_cm_idx = rdev->pm.requested_clock_mode_index;
104 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
105 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
106
107 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
108 /* 0xff01 is a flag rather then an actual voltage */
109 if (voltage->voltage == 0xff01)
110 return;
111 if (voltage->voltage != rdev->pm.current_vddc) {
112 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
113 rdev->pm.current_vddc = voltage->voltage;
114 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
115 }
116 }
117 }
118
119 /*
120 * GART
121 */
122 int rv770_pcie_gart_enable(struct radeon_device *rdev)
123 {
124 u32 tmp;
125 int r, i;
126
127 if (rdev->gart.table.vram.robj == NULL) {
128 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
129 return -EINVAL;
130 }
131 r = radeon_gart_table_vram_pin(rdev);
132 if (r)
133 return r;
134 radeon_gart_restore(rdev);
135 /* Setup L2 cache */
136 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
137 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
138 EFFECTIVE_L2_QUEUE_SIZE(7));
139 WREG32(VM_L2_CNTL2, 0);
140 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
141 /* Setup TLB control */
142 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
143 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
144 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
145 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
146 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
147 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
148 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
149 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
150 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
151 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
152 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
153 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
154 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
155 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
156 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
157 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
158 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
159 (u32)(rdev->dummy_page.addr >> 12));
160 for (i = 1; i < 7; i++)
161 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
162
163 r600_pcie_gart_tlb_flush(rdev);
164 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
165 (unsigned)(rdev->mc.gtt_size >> 20),
166 (unsigned long long)rdev->gart.table_addr);
167 rdev->gart.ready = true;
168 return 0;
169 }
170
171 void rv770_pcie_gart_disable(struct radeon_device *rdev)
172 {
173 u32 tmp;
174 int i, r;
175
176 /* Disable all tables */
177 for (i = 0; i < 7; i++)
178 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
179
180 /* Setup L2 cache */
181 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
182 EFFECTIVE_L2_QUEUE_SIZE(7));
183 WREG32(VM_L2_CNTL2, 0);
184 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
185 /* Setup TLB control */
186 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
187 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
188 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
189 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
190 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
191 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
192 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
193 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
194 if (rdev->gart.table.vram.robj) {
195 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
196 if (likely(r == 0)) {
197 radeon_bo_kunmap(rdev->gart.table.vram.robj);
198 radeon_bo_unpin(rdev->gart.table.vram.robj);
199 radeon_bo_unreserve(rdev->gart.table.vram.robj);
200 }
201 }
202 }
203
204 void rv770_pcie_gart_fini(struct radeon_device *rdev)
205 {
206 radeon_gart_fini(rdev);
207 rv770_pcie_gart_disable(rdev);
208 radeon_gart_table_vram_free(rdev);
209 }
210
211
212 void rv770_agp_enable(struct radeon_device *rdev)
213 {
214 u32 tmp;
215 int i;
216
217 /* Setup L2 cache */
218 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
219 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
220 EFFECTIVE_L2_QUEUE_SIZE(7));
221 WREG32(VM_L2_CNTL2, 0);
222 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
223 /* Setup TLB control */
224 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
225 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
226 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
227 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
228 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
229 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
230 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
231 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
232 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
233 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
234 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
235 for (i = 0; i < 7; i++)
236 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
237 }
238
239 static void rv770_mc_program(struct radeon_device *rdev)
240 {
241 struct rv515_mc_save save;
242 u32 tmp;
243 int i, j;
244
245 /* Initialize HDP */
246 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
247 WREG32((0x2c14 + j), 0x00000000);
248 WREG32((0x2c18 + j), 0x00000000);
249 WREG32((0x2c1c + j), 0x00000000);
250 WREG32((0x2c20 + j), 0x00000000);
251 WREG32((0x2c24 + j), 0x00000000);
252 }
253 /* r7xx hw bug. Read from HDP_DEBUG1 rather
254 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
255 */
256 tmp = RREG32(HDP_DEBUG1);
257
258 rv515_mc_stop(rdev, &save);
259 if (r600_mc_wait_for_idle(rdev)) {
260 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
261 }
262 /* Lockout access through VGA aperture*/
263 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
264 /* Update configuration */
265 if (rdev->flags & RADEON_IS_AGP) {
266 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
267 /* VRAM before AGP */
268 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
269 rdev->mc.vram_start >> 12);
270 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
271 rdev->mc.gtt_end >> 12);
272 } else {
273 /* VRAM after AGP */
274 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
275 rdev->mc.gtt_start >> 12);
276 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
277 rdev->mc.vram_end >> 12);
278 }
279 } else {
280 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
281 rdev->mc.vram_start >> 12);
282 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
283 rdev->mc.vram_end >> 12);
284 }
285 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
286 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
287 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
288 WREG32(MC_VM_FB_LOCATION, tmp);
289 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
290 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
291 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
292 if (rdev->flags & RADEON_IS_AGP) {
293 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
294 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
295 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
296 } else {
297 WREG32(MC_VM_AGP_BASE, 0);
298 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
299 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
300 }
301 if (r600_mc_wait_for_idle(rdev)) {
302 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
303 }
304 rv515_mc_resume(rdev, &save);
305 /* we need to own VRAM, so turn off the VGA renderer here
306 * to stop it overwriting our objects */
307 rv515_vga_render_disable(rdev);
308 }
309
310
311 /*
312 * CP.
313 */
314 void r700_cp_stop(struct radeon_device *rdev)
315 {
316 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
317 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
318 WREG32(SCRATCH_UMSK, 0);
319 }
320
321 static int rv770_cp_load_microcode(struct radeon_device *rdev)
322 {
323 const __be32 *fw_data;
324 int i;
325
326 if (!rdev->me_fw || !rdev->pfp_fw)
327 return -EINVAL;
328
329 r700_cp_stop(rdev);
330 WREG32(CP_RB_CNTL,
331 #ifdef __BIG_ENDIAN
332 BUF_SWAP_32BIT |
333 #endif
334 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
335
336 /* Reset cp */
337 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
338 RREG32(GRBM_SOFT_RESET);
339 mdelay(15);
340 WREG32(GRBM_SOFT_RESET, 0);
341
342 fw_data = (const __be32 *)rdev->pfp_fw->data;
343 WREG32(CP_PFP_UCODE_ADDR, 0);
344 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
345 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
346 WREG32(CP_PFP_UCODE_ADDR, 0);
347
348 fw_data = (const __be32 *)rdev->me_fw->data;
349 WREG32(CP_ME_RAM_WADDR, 0);
350 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
351 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
352
353 WREG32(CP_PFP_UCODE_ADDR, 0);
354 WREG32(CP_ME_RAM_WADDR, 0);
355 WREG32(CP_ME_RAM_RADDR, 0);
356 return 0;
357 }
358
359 void r700_cp_fini(struct radeon_device *rdev)
360 {
361 r700_cp_stop(rdev);
362 radeon_ring_fini(rdev);
363 }
364
365 /*
366 * Core functions
367 */
368 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
369 u32 num_tile_pipes,
370 u32 num_backends,
371 u32 backend_disable_mask)
372 {
373 u32 backend_map = 0;
374 u32 enabled_backends_mask;
375 u32 enabled_backends_count;
376 u32 cur_pipe;
377 u32 swizzle_pipe[R7XX_MAX_PIPES];
378 u32 cur_backend;
379 u32 i;
380 bool force_no_swizzle;
381
382 if (num_tile_pipes > R7XX_MAX_PIPES)
383 num_tile_pipes = R7XX_MAX_PIPES;
384 if (num_tile_pipes < 1)
385 num_tile_pipes = 1;
386 if (num_backends > R7XX_MAX_BACKENDS)
387 num_backends = R7XX_MAX_BACKENDS;
388 if (num_backends < 1)
389 num_backends = 1;
390
391 enabled_backends_mask = 0;
392 enabled_backends_count = 0;
393 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
394 if (((backend_disable_mask >> i) & 1) == 0) {
395 enabled_backends_mask |= (1 << i);
396 ++enabled_backends_count;
397 }
398 if (enabled_backends_count == num_backends)
399 break;
400 }
401
402 if (enabled_backends_count == 0) {
403 enabled_backends_mask = 1;
404 enabled_backends_count = 1;
405 }
406
407 if (enabled_backends_count != num_backends)
408 num_backends = enabled_backends_count;
409
410 switch (rdev->family) {
411 case CHIP_RV770:
412 case CHIP_RV730:
413 force_no_swizzle = false;
414 break;
415 case CHIP_RV710:
416 case CHIP_RV740:
417 default:
418 force_no_swizzle = true;
419 break;
420 }
421
422 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
423 switch (num_tile_pipes) {
424 case 1:
425 swizzle_pipe[0] = 0;
426 break;
427 case 2:
428 swizzle_pipe[0] = 0;
429 swizzle_pipe[1] = 1;
430 break;
431 case 3:
432 if (force_no_swizzle) {
433 swizzle_pipe[0] = 0;
434 swizzle_pipe[1] = 1;
435 swizzle_pipe[2] = 2;
436 } else {
437 swizzle_pipe[0] = 0;
438 swizzle_pipe[1] = 2;
439 swizzle_pipe[2] = 1;
440 }
441 break;
442 case 4:
443 if (force_no_swizzle) {
444 swizzle_pipe[0] = 0;
445 swizzle_pipe[1] = 1;
446 swizzle_pipe[2] = 2;
447 swizzle_pipe[3] = 3;
448 } else {
449 swizzle_pipe[0] = 0;
450 swizzle_pipe[1] = 2;
451 swizzle_pipe[2] = 3;
452 swizzle_pipe[3] = 1;
453 }
454 break;
455 case 5:
456 if (force_no_swizzle) {
457 swizzle_pipe[0] = 0;
458 swizzle_pipe[1] = 1;
459 swizzle_pipe[2] = 2;
460 swizzle_pipe[3] = 3;
461 swizzle_pipe[4] = 4;
462 } else {
463 swizzle_pipe[0] = 0;
464 swizzle_pipe[1] = 2;
465 swizzle_pipe[2] = 4;
466 swizzle_pipe[3] = 1;
467 swizzle_pipe[4] = 3;
468 }
469 break;
470 case 6:
471 if (force_no_swizzle) {
472 swizzle_pipe[0] = 0;
473 swizzle_pipe[1] = 1;
474 swizzle_pipe[2] = 2;
475 swizzle_pipe[3] = 3;
476 swizzle_pipe[4] = 4;
477 swizzle_pipe[5] = 5;
478 } else {
479 swizzle_pipe[0] = 0;
480 swizzle_pipe[1] = 2;
481 swizzle_pipe[2] = 4;
482 swizzle_pipe[3] = 5;
483 swizzle_pipe[4] = 3;
484 swizzle_pipe[5] = 1;
485 }
486 break;
487 case 7:
488 if (force_no_swizzle) {
489 swizzle_pipe[0] = 0;
490 swizzle_pipe[1] = 1;
491 swizzle_pipe[2] = 2;
492 swizzle_pipe[3] = 3;
493 swizzle_pipe[4] = 4;
494 swizzle_pipe[5] = 5;
495 swizzle_pipe[6] = 6;
496 } else {
497 swizzle_pipe[0] = 0;
498 swizzle_pipe[1] = 2;
499 swizzle_pipe[2] = 4;
500 swizzle_pipe[3] = 6;
501 swizzle_pipe[4] = 3;
502 swizzle_pipe[5] = 1;
503 swizzle_pipe[6] = 5;
504 }
505 break;
506 case 8:
507 if (force_no_swizzle) {
508 swizzle_pipe[0] = 0;
509 swizzle_pipe[1] = 1;
510 swizzle_pipe[2] = 2;
511 swizzle_pipe[3] = 3;
512 swizzle_pipe[4] = 4;
513 swizzle_pipe[5] = 5;
514 swizzle_pipe[6] = 6;
515 swizzle_pipe[7] = 7;
516 } else {
517 swizzle_pipe[0] = 0;
518 swizzle_pipe[1] = 2;
519 swizzle_pipe[2] = 4;
520 swizzle_pipe[3] = 6;
521 swizzle_pipe[4] = 3;
522 swizzle_pipe[5] = 1;
523 swizzle_pipe[6] = 7;
524 swizzle_pipe[7] = 5;
525 }
526 break;
527 }
528
529 cur_backend = 0;
530 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
531 while (((1 << cur_backend) & enabled_backends_mask) == 0)
532 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
533
534 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
535
536 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
537 }
538
539 return backend_map;
540 }
541
542 static void rv770_program_channel_remap(struct radeon_device *rdev)
543 {
544 u32 tcp_chan_steer, mc_shared_chremap, tmp;
545 bool force_no_swizzle;
546
547 switch (rdev->family) {
548 case CHIP_RV770:
549 case CHIP_RV730:
550 force_no_swizzle = false;
551 break;
552 case CHIP_RV710:
553 case CHIP_RV740:
554 default:
555 force_no_swizzle = true;
556 break;
557 }
558
559 tmp = RREG32(MC_SHARED_CHMAP);
560 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
561 case 0:
562 case 1:
563 default:
564 /* default mapping */
565 mc_shared_chremap = 0x00fac688;
566 break;
567 case 2:
568 case 3:
569 if (force_no_swizzle)
570 mc_shared_chremap = 0x00fac688;
571 else
572 mc_shared_chremap = 0x00bbc298;
573 break;
574 }
575
576 if (rdev->family == CHIP_RV740)
577 tcp_chan_steer = 0x00ef2a60;
578 else
579 tcp_chan_steer = 0x00fac688;
580
581 /* RV770 CE has special chremap setup */
582 if (rdev->pdev->device == 0x944e) {
583 tcp_chan_steer = 0x00b08b08;
584 mc_shared_chremap = 0x00b08b08;
585 }
586
587 WREG32(TCP_CHAN_STEER, tcp_chan_steer);
588 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
589 }
590
591 static void rv770_gpu_init(struct radeon_device *rdev)
592 {
593 int i, j, num_qd_pipes;
594 u32 ta_aux_cntl;
595 u32 sx_debug_1;
596 u32 smx_dc_ctl0;
597 u32 db_debug3;
598 u32 num_gs_verts_per_thread;
599 u32 vgt_gs_per_es;
600 u32 gs_prim_buffer_depth = 0;
601 u32 sq_ms_fifo_sizes;
602 u32 sq_config;
603 u32 sq_thread_resource_mgmt;
604 u32 hdp_host_path_cntl;
605 u32 sq_dyn_gpr_size_simd_ab_0;
606 u32 backend_map;
607 u32 gb_tiling_config = 0;
608 u32 cc_rb_backend_disable = 0;
609 u32 cc_gc_shader_pipe_config = 0;
610 u32 mc_arb_ramcfg;
611 u32 db_debug4;
612
613 /* setup chip specs */
614 switch (rdev->family) {
615 case CHIP_RV770:
616 rdev->config.rv770.max_pipes = 4;
617 rdev->config.rv770.max_tile_pipes = 8;
618 rdev->config.rv770.max_simds = 10;
619 rdev->config.rv770.max_backends = 4;
620 rdev->config.rv770.max_gprs = 256;
621 rdev->config.rv770.max_threads = 248;
622 rdev->config.rv770.max_stack_entries = 512;
623 rdev->config.rv770.max_hw_contexts = 8;
624 rdev->config.rv770.max_gs_threads = 16 * 2;
625 rdev->config.rv770.sx_max_export_size = 128;
626 rdev->config.rv770.sx_max_export_pos_size = 16;
627 rdev->config.rv770.sx_max_export_smx_size = 112;
628 rdev->config.rv770.sq_num_cf_insts = 2;
629
630 rdev->config.rv770.sx_num_of_sets = 7;
631 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
632 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
633 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
634 break;
635 case CHIP_RV730:
636 rdev->config.rv770.max_pipes = 2;
637 rdev->config.rv770.max_tile_pipes = 4;
638 rdev->config.rv770.max_simds = 8;
639 rdev->config.rv770.max_backends = 2;
640 rdev->config.rv770.max_gprs = 128;
641 rdev->config.rv770.max_threads = 248;
642 rdev->config.rv770.max_stack_entries = 256;
643 rdev->config.rv770.max_hw_contexts = 8;
644 rdev->config.rv770.max_gs_threads = 16 * 2;
645 rdev->config.rv770.sx_max_export_size = 256;
646 rdev->config.rv770.sx_max_export_pos_size = 32;
647 rdev->config.rv770.sx_max_export_smx_size = 224;
648 rdev->config.rv770.sq_num_cf_insts = 2;
649
650 rdev->config.rv770.sx_num_of_sets = 7;
651 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
652 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
653 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
654 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
655 rdev->config.rv770.sx_max_export_pos_size -= 16;
656 rdev->config.rv770.sx_max_export_smx_size += 16;
657 }
658 break;
659 case CHIP_RV710:
660 rdev->config.rv770.max_pipes = 2;
661 rdev->config.rv770.max_tile_pipes = 2;
662 rdev->config.rv770.max_simds = 2;
663 rdev->config.rv770.max_backends = 1;
664 rdev->config.rv770.max_gprs = 256;
665 rdev->config.rv770.max_threads = 192;
666 rdev->config.rv770.max_stack_entries = 256;
667 rdev->config.rv770.max_hw_contexts = 4;
668 rdev->config.rv770.max_gs_threads = 8 * 2;
669 rdev->config.rv770.sx_max_export_size = 128;
670 rdev->config.rv770.sx_max_export_pos_size = 16;
671 rdev->config.rv770.sx_max_export_smx_size = 112;
672 rdev->config.rv770.sq_num_cf_insts = 1;
673
674 rdev->config.rv770.sx_num_of_sets = 7;
675 rdev->config.rv770.sc_prim_fifo_size = 0x40;
676 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
677 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
678 break;
679 case CHIP_RV740:
680 rdev->config.rv770.max_pipes = 4;
681 rdev->config.rv770.max_tile_pipes = 4;
682 rdev->config.rv770.max_simds = 8;
683 rdev->config.rv770.max_backends = 4;
684 rdev->config.rv770.max_gprs = 256;
685 rdev->config.rv770.max_threads = 248;
686 rdev->config.rv770.max_stack_entries = 512;
687 rdev->config.rv770.max_hw_contexts = 8;
688 rdev->config.rv770.max_gs_threads = 16 * 2;
689 rdev->config.rv770.sx_max_export_size = 256;
690 rdev->config.rv770.sx_max_export_pos_size = 32;
691 rdev->config.rv770.sx_max_export_smx_size = 224;
692 rdev->config.rv770.sq_num_cf_insts = 2;
693
694 rdev->config.rv770.sx_num_of_sets = 7;
695 rdev->config.rv770.sc_prim_fifo_size = 0x100;
696 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
697 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
698
699 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
700 rdev->config.rv770.sx_max_export_pos_size -= 16;
701 rdev->config.rv770.sx_max_export_smx_size += 16;
702 }
703 break;
704 default:
705 break;
706 }
707
708 /* Initialize HDP */
709 j = 0;
710 for (i = 0; i < 32; i++) {
711 WREG32((0x2c14 + j), 0x00000000);
712 WREG32((0x2c18 + j), 0x00000000);
713 WREG32((0x2c1c + j), 0x00000000);
714 WREG32((0x2c20 + j), 0x00000000);
715 WREG32((0x2c24 + j), 0x00000000);
716 j += 0x18;
717 }
718
719 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
720
721 /* setup tiling, simd, pipe config */
722 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
723
724 switch (rdev->config.rv770.max_tile_pipes) {
725 case 1:
726 default:
727 gb_tiling_config |= PIPE_TILING(0);
728 break;
729 case 2:
730 gb_tiling_config |= PIPE_TILING(1);
731 break;
732 case 4:
733 gb_tiling_config |= PIPE_TILING(2);
734 break;
735 case 8:
736 gb_tiling_config |= PIPE_TILING(3);
737 break;
738 }
739 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
740
741 if (rdev->family == CHIP_RV770)
742 gb_tiling_config |= BANK_TILING(1);
743 else
744 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
745 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
746 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
747 if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
748 rdev->config.rv770.tiling_group_size = 512;
749 else
750 rdev->config.rv770.tiling_group_size = 256;
751 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
752 gb_tiling_config |= ROW_TILING(3);
753 gb_tiling_config |= SAMPLE_SPLIT(3);
754 } else {
755 gb_tiling_config |=
756 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
757 gb_tiling_config |=
758 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
759 }
760
761 gb_tiling_config |= BANK_SWAPS(1);
762
763 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
764 cc_rb_backend_disable |=
765 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
766
767 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
768 cc_gc_shader_pipe_config |=
769 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
770 cc_gc_shader_pipe_config |=
771 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
772
773 if (rdev->family == CHIP_RV740)
774 backend_map = 0x28;
775 else
776 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
777 rdev->config.rv770.max_tile_pipes,
778 (R7XX_MAX_BACKENDS -
779 r600_count_pipe_bits((cc_rb_backend_disable &
780 R7XX_MAX_BACKENDS_MASK) >> 16)),
781 (cc_rb_backend_disable >> 16));
782
783 rdev->config.rv770.tile_config = gb_tiling_config;
784 rdev->config.rv770.backend_map = backend_map;
785 gb_tiling_config |= BACKEND_MAP(backend_map);
786
787 WREG32(GB_TILING_CONFIG, gb_tiling_config);
788 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
789 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
790
791 rv770_program_channel_remap(rdev);
792
793 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
794 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
795 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
796 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
797
798 WREG32(CGTS_SYS_TCC_DISABLE, 0);
799 WREG32(CGTS_TCC_DISABLE, 0);
800 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
801 WREG32(CGTS_USER_TCC_DISABLE, 0);
802
803 num_qd_pipes =
804 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
805 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
806 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
807
808 /* set HW defaults for 3D engine */
809 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
810 ROQ_IB2_START(0x2b)));
811
812 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
813
814 ta_aux_cntl = RREG32(TA_CNTL_AUX);
815 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
816
817 sx_debug_1 = RREG32(SX_DEBUG_1);
818 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
819 WREG32(SX_DEBUG_1, sx_debug_1);
820
821 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
822 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
823 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
824 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
825
826 if (rdev->family != CHIP_RV740)
827 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
828 GS_FLUSH_CTL(4) |
829 ACK_FLUSH_CTL(3) |
830 SYNC_FLUSH_CTL));
831
832 db_debug3 = RREG32(DB_DEBUG3);
833 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
834 switch (rdev->family) {
835 case CHIP_RV770:
836 case CHIP_RV740:
837 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
838 break;
839 case CHIP_RV710:
840 case CHIP_RV730:
841 default:
842 db_debug3 |= DB_CLK_OFF_DELAY(2);
843 break;
844 }
845 WREG32(DB_DEBUG3, db_debug3);
846
847 if (rdev->family != CHIP_RV770) {
848 db_debug4 = RREG32(DB_DEBUG4);
849 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
850 WREG32(DB_DEBUG4, db_debug4);
851 }
852
853 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
854 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
855 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
856
857 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
858 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
859 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
860
861 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
862
863 WREG32(VGT_NUM_INSTANCES, 1);
864
865 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
866
867 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
868
869 WREG32(CP_PERFMON_CNTL, 0);
870
871 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
872 DONE_FIFO_HIWATER(0xe0) |
873 ALU_UPDATE_FIFO_HIWATER(0x8));
874 switch (rdev->family) {
875 case CHIP_RV770:
876 case CHIP_RV730:
877 case CHIP_RV710:
878 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
879 break;
880 case CHIP_RV740:
881 default:
882 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
883 break;
884 }
885 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
886
887 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
888 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
889 */
890 sq_config = RREG32(SQ_CONFIG);
891 sq_config &= ~(PS_PRIO(3) |
892 VS_PRIO(3) |
893 GS_PRIO(3) |
894 ES_PRIO(3));
895 sq_config |= (DX9_CONSTS |
896 VC_ENABLE |
897 EXPORT_SRC_C |
898 PS_PRIO(0) |
899 VS_PRIO(1) |
900 GS_PRIO(2) |
901 ES_PRIO(3));
902 if (rdev->family == CHIP_RV710)
903 /* no vertex cache */
904 sq_config &= ~VC_ENABLE;
905
906 WREG32(SQ_CONFIG, sq_config);
907
908 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
909 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
910 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
911
912 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
913 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
914
915 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
916 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
917 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
918 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
919 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
920 else
921 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
922 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
923
924 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
925 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
926
927 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
928 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
929
930 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
931 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
932 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
933 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
934
935 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
936 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
937 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
938 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
939 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
940 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
941 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
942 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
943
944 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
945 FORCE_EOV_MAX_REZ_CNT(255)));
946
947 if (rdev->family == CHIP_RV710)
948 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
949 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
950 else
951 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
952 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
953
954 switch (rdev->family) {
955 case CHIP_RV770:
956 case CHIP_RV730:
957 case CHIP_RV740:
958 gs_prim_buffer_depth = 384;
959 break;
960 case CHIP_RV710:
961 gs_prim_buffer_depth = 128;
962 break;
963 default:
964 break;
965 }
966
967 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
968 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
969 /* Max value for this is 256 */
970 if (vgt_gs_per_es > 256)
971 vgt_gs_per_es = 256;
972
973 WREG32(VGT_ES_PER_GS, 128);
974 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
975 WREG32(VGT_GS_PER_VS, 2);
976
977 /* more default values. 2D/3D driver should adjust as needed */
978 WREG32(VGT_GS_VERTEX_REUSE, 16);
979 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
980 WREG32(VGT_STRMOUT_EN, 0);
981 WREG32(SX_MISC, 0);
982 WREG32(PA_SC_MODE_CNTL, 0);
983 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
984 WREG32(PA_SC_AA_CONFIG, 0);
985 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
986 WREG32(PA_SC_LINE_STIPPLE, 0);
987 WREG32(SPI_INPUT_Z, 0);
988 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
989 WREG32(CB_COLOR7_FRAG, 0);
990
991 /* clear render buffer base addresses */
992 WREG32(CB_COLOR0_BASE, 0);
993 WREG32(CB_COLOR1_BASE, 0);
994 WREG32(CB_COLOR2_BASE, 0);
995 WREG32(CB_COLOR3_BASE, 0);
996 WREG32(CB_COLOR4_BASE, 0);
997 WREG32(CB_COLOR5_BASE, 0);
998 WREG32(CB_COLOR6_BASE, 0);
999 WREG32(CB_COLOR7_BASE, 0);
1000
1001 WREG32(TCP_CNTL, 0);
1002
1003 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1004 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1005
1006 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1007
1008 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1009 NUM_CLIP_SEQ(3)));
1010
1011 }
1012
1013 static int rv770_vram_scratch_init(struct radeon_device *rdev)
1014 {
1015 int r;
1016 u64 gpu_addr;
1017
1018 if (rdev->vram_scratch.robj == NULL) {
1019 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1020 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1021 &rdev->vram_scratch.robj);
1022 if (r) {
1023 return r;
1024 }
1025 }
1026
1027 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1028 if (unlikely(r != 0))
1029 return r;
1030 r = radeon_bo_pin(rdev->vram_scratch.robj,
1031 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
1032 if (r) {
1033 radeon_bo_unreserve(rdev->vram_scratch.robj);
1034 return r;
1035 }
1036 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1037 (void **)&rdev->vram_scratch.ptr);
1038 if (r)
1039 radeon_bo_unpin(rdev->vram_scratch.robj);
1040 radeon_bo_unreserve(rdev->vram_scratch.robj);
1041
1042 return r;
1043 }
1044
1045 static void rv770_vram_scratch_fini(struct radeon_device *rdev)
1046 {
1047 int r;
1048
1049 if (rdev->vram_scratch.robj == NULL) {
1050 return;
1051 }
1052 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1053 if (likely(r == 0)) {
1054 radeon_bo_kunmap(rdev->vram_scratch.robj);
1055 radeon_bo_unpin(rdev->vram_scratch.robj);
1056 radeon_bo_unreserve(rdev->vram_scratch.robj);
1057 }
1058 radeon_bo_unref(&rdev->vram_scratch.robj);
1059 }
1060
1061 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1062 {
1063 u64 size_bf, size_af;
1064
1065 if (mc->mc_vram_size > 0xE0000000) {
1066 /* leave room for at least 512M GTT */
1067 dev_warn(rdev->dev, "limiting VRAM\n");
1068 mc->real_vram_size = 0xE0000000;
1069 mc->mc_vram_size = 0xE0000000;
1070 }
1071 if (rdev->flags & RADEON_IS_AGP) {
1072 size_bf = mc->gtt_start;
1073 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1074 if (size_bf > size_af) {
1075 if (mc->mc_vram_size > size_bf) {
1076 dev_warn(rdev->dev, "limiting VRAM\n");
1077 mc->real_vram_size = size_bf;
1078 mc->mc_vram_size = size_bf;
1079 }
1080 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1081 } else {
1082 if (mc->mc_vram_size > size_af) {
1083 dev_warn(rdev->dev, "limiting VRAM\n");
1084 mc->real_vram_size = size_af;
1085 mc->mc_vram_size = size_af;
1086 }
1087 mc->vram_start = mc->gtt_end;
1088 }
1089 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1090 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1091 mc->mc_vram_size >> 20, mc->vram_start,
1092 mc->vram_end, mc->real_vram_size >> 20);
1093 } else {
1094 radeon_vram_location(rdev, &rdev->mc, 0);
1095 rdev->mc.gtt_base_align = 0;
1096 radeon_gtt_location(rdev, mc);
1097 }
1098 }
1099
1100 int rv770_mc_init(struct radeon_device *rdev)
1101 {
1102 u32 tmp;
1103 int chansize, numchan;
1104
1105 /* Get VRAM informations */
1106 rdev->mc.vram_is_ddr = true;
1107 tmp = RREG32(MC_ARB_RAMCFG);
1108 if (tmp & CHANSIZE_OVERRIDE) {
1109 chansize = 16;
1110 } else if (tmp & CHANSIZE_MASK) {
1111 chansize = 64;
1112 } else {
1113 chansize = 32;
1114 }
1115 tmp = RREG32(MC_SHARED_CHMAP);
1116 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1117 case 0:
1118 default:
1119 numchan = 1;
1120 break;
1121 case 1:
1122 numchan = 2;
1123 break;
1124 case 2:
1125 numchan = 4;
1126 break;
1127 case 3:
1128 numchan = 8;
1129 break;
1130 }
1131 rdev->mc.vram_width = numchan * chansize;
1132 /* Could aper size report 0 ? */
1133 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1134 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1135 /* Setup GPU memory space */
1136 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1137 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1138 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1139 r700_vram_gtt_location(rdev, &rdev->mc);
1140 radeon_update_bandwidth_info(rdev);
1141
1142 return 0;
1143 }
1144
1145 static int rv770_startup(struct radeon_device *rdev)
1146 {
1147 int r;
1148
1149 /* enable pcie gen2 link */
1150 rv770_pcie_gen2_enable(rdev);
1151
1152 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1153 r = r600_init_microcode(rdev);
1154 if (r) {
1155 DRM_ERROR("Failed to load firmware!\n");
1156 return r;
1157 }
1158 }
1159
1160 rv770_mc_program(rdev);
1161 if (rdev->flags & RADEON_IS_AGP) {
1162 rv770_agp_enable(rdev);
1163 } else {
1164 r = rv770_pcie_gart_enable(rdev);
1165 if (r)
1166 return r;
1167 }
1168 r = rv770_vram_scratch_init(rdev);
1169 if (r)
1170 return r;
1171 rv770_gpu_init(rdev);
1172 r = r600_blit_init(rdev);
1173 if (r) {
1174 r600_blit_fini(rdev);
1175 rdev->asic->copy = NULL;
1176 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1177 }
1178
1179 /* allocate wb buffer */
1180 r = radeon_wb_init(rdev);
1181 if (r)
1182 return r;
1183
1184 /* Enable IRQ */
1185 r = r600_irq_init(rdev);
1186 if (r) {
1187 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1188 radeon_irq_kms_fini(rdev);
1189 return r;
1190 }
1191 r600_irq_set(rdev);
1192
1193 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1194 if (r)
1195 return r;
1196 r = rv770_cp_load_microcode(rdev);
1197 if (r)
1198 return r;
1199 r = r600_cp_resume(rdev);
1200 if (r)
1201 return r;
1202
1203 return 0;
1204 }
1205
1206 int rv770_resume(struct radeon_device *rdev)
1207 {
1208 int r;
1209
1210 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1211 * posting will perform necessary task to bring back GPU into good
1212 * shape.
1213 */
1214 /* post card */
1215 atom_asic_init(rdev->mode_info.atom_context);
1216
1217 r = rv770_startup(rdev);
1218 if (r) {
1219 DRM_ERROR("r600 startup failed on resume\n");
1220 return r;
1221 }
1222
1223 r = r600_ib_test(rdev);
1224 if (r) {
1225 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1226 return r;
1227 }
1228
1229 r = r600_audio_init(rdev);
1230 if (r) {
1231 dev_err(rdev->dev, "radeon: audio init failed\n");
1232 return r;
1233 }
1234
1235 return r;
1236
1237 }
1238
1239 int rv770_suspend(struct radeon_device *rdev)
1240 {
1241 int r;
1242
1243 r600_audio_fini(rdev);
1244 /* FIXME: we should wait for ring to be empty */
1245 r700_cp_stop(rdev);
1246 rdev->cp.ready = false;
1247 r600_irq_suspend(rdev);
1248 radeon_wb_disable(rdev);
1249 rv770_pcie_gart_disable(rdev);
1250 /* unpin shaders bo */
1251 if (rdev->r600_blit.shader_obj) {
1252 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1253 if (likely(r == 0)) {
1254 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1255 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1256 }
1257 }
1258 return 0;
1259 }
1260
1261 /* Plan is to move initialization in that function and use
1262 * helper function so that radeon_device_init pretty much
1263 * do nothing more than calling asic specific function. This
1264 * should also allow to remove a bunch of callback function
1265 * like vram_info.
1266 */
1267 int rv770_init(struct radeon_device *rdev)
1268 {
1269 int r;
1270
1271 /* This don't do much */
1272 r = radeon_gem_init(rdev);
1273 if (r)
1274 return r;
1275 /* Read BIOS */
1276 if (!radeon_get_bios(rdev)) {
1277 if (ASIC_IS_AVIVO(rdev))
1278 return -EINVAL;
1279 }
1280 /* Must be an ATOMBIOS */
1281 if (!rdev->is_atom_bios) {
1282 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1283 return -EINVAL;
1284 }
1285 r = radeon_atombios_init(rdev);
1286 if (r)
1287 return r;
1288 /* Post card if necessary */
1289 if (!radeon_card_posted(rdev)) {
1290 if (!rdev->bios) {
1291 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1292 return -EINVAL;
1293 }
1294 DRM_INFO("GPU not posted. posting now...\n");
1295 atom_asic_init(rdev->mode_info.atom_context);
1296 }
1297 /* Initialize scratch registers */
1298 r600_scratch_init(rdev);
1299 /* Initialize surface registers */
1300 radeon_surface_init(rdev);
1301 /* Initialize clocks */
1302 radeon_get_clock_info(rdev->ddev);
1303 /* Fence driver */
1304 r = radeon_fence_driver_init(rdev);
1305 if (r)
1306 return r;
1307 /* initialize AGP */
1308 if (rdev->flags & RADEON_IS_AGP) {
1309 r = radeon_agp_init(rdev);
1310 if (r)
1311 radeon_agp_disable(rdev);
1312 }
1313 r = rv770_mc_init(rdev);
1314 if (r)
1315 return r;
1316 /* Memory manager */
1317 r = radeon_bo_init(rdev);
1318 if (r)
1319 return r;
1320
1321 r = radeon_irq_kms_init(rdev);
1322 if (r)
1323 return r;
1324
1325 rdev->cp.ring_obj = NULL;
1326 r600_ring_init(rdev, 1024 * 1024);
1327
1328 rdev->ih.ring_obj = NULL;
1329 r600_ih_ring_init(rdev, 64 * 1024);
1330
1331 r = r600_pcie_gart_init(rdev);
1332 if (r)
1333 return r;
1334
1335 rdev->accel_working = true;
1336 r = rv770_startup(rdev);
1337 if (r) {
1338 dev_err(rdev->dev, "disabling GPU acceleration\n");
1339 r700_cp_fini(rdev);
1340 r600_irq_fini(rdev);
1341 radeon_wb_fini(rdev);
1342 radeon_irq_kms_fini(rdev);
1343 rv770_pcie_gart_fini(rdev);
1344 rdev->accel_working = false;
1345 }
1346 if (rdev->accel_working) {
1347 r = radeon_ib_pool_init(rdev);
1348 if (r) {
1349 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1350 rdev->accel_working = false;
1351 } else {
1352 r = r600_ib_test(rdev);
1353 if (r) {
1354 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1355 rdev->accel_working = false;
1356 }
1357 }
1358 }
1359
1360 r = r600_audio_init(rdev);
1361 if (r) {
1362 dev_err(rdev->dev, "radeon: audio init failed\n");
1363 return r;
1364 }
1365
1366 return 0;
1367 }
1368
1369 void rv770_fini(struct radeon_device *rdev)
1370 {
1371 r600_blit_fini(rdev);
1372 r700_cp_fini(rdev);
1373 r600_irq_fini(rdev);
1374 radeon_wb_fini(rdev);
1375 radeon_ib_pool_fini(rdev);
1376 radeon_irq_kms_fini(rdev);
1377 rv770_pcie_gart_fini(rdev);
1378 rv770_vram_scratch_fini(rdev);
1379 radeon_gem_fini(rdev);
1380 radeon_fence_driver_fini(rdev);
1381 radeon_agp_fini(rdev);
1382 radeon_bo_fini(rdev);
1383 radeon_atombios_fini(rdev);
1384 kfree(rdev->bios);
1385 rdev->bios = NULL;
1386 }
1387
1388 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1389 {
1390 u32 link_width_cntl, lanes, speed_cntl, tmp;
1391 u16 link_cntl2;
1392
1393 if (radeon_pcie_gen2 == 0)
1394 return;
1395
1396 if (rdev->flags & RADEON_IS_IGP)
1397 return;
1398
1399 if (!(rdev->flags & RADEON_IS_PCIE))
1400 return;
1401
1402 /* x2 cards have a special sequence */
1403 if (ASIC_IS_X2(rdev))
1404 return;
1405
1406 /* advertise upconfig capability */
1407 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1408 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1409 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1410 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1411 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1412 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1413 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1414 LC_RECONFIG_ARC_MISSING_ESCAPE);
1415 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1416 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1417 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1418 } else {
1419 link_width_cntl |= LC_UPCONFIGURE_DIS;
1420 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1421 }
1422
1423 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1424 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1425 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1426
1427 tmp = RREG32(0x541c);
1428 WREG32(0x541c, tmp | 0x8);
1429 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1430 link_cntl2 = RREG16(0x4088);
1431 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1432 link_cntl2 |= 0x2;
1433 WREG16(0x4088, link_cntl2);
1434 WREG32(MM_CFGREGS_CNTL, 0);
1435
1436 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1437 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1438 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1439
1440 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1441 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1442 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1443
1444 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1445 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1446 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1447
1448 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1449 speed_cntl |= LC_GEN2_EN_STRAP;
1450 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1451
1452 } else {
1453 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1454 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1455 if (1)
1456 link_width_cntl |= LC_UPCONFIGURE_DIS;
1457 else
1458 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1459 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1460 }
1461 }
Linux with added FPC-III support