Linux 4.9.151
[linux/fpc-iii.git] / arch / arc / kernel / setup.c
blob0385df77a69738f06a45d45553b1c0d6e0980e30
1 /*
2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 #include <linux/seq_file.h>
10 #include <linux/fs.h>
11 #include <linux/delay.h>
12 #include <linux/root_dev.h>
13 #include <linux/console.h>
14 #include <linux/module.h>
15 #include <linux/cpu.h>
16 #include <linux/of_fdt.h>
17 #include <linux/of.h>
18 #include <linux/cache.h>
19 #include <asm/sections.h>
20 #include <asm/arcregs.h>
21 #include <asm/tlb.h>
22 #include <asm/setup.h>
23 #include <asm/page.h>
24 #include <asm/irq.h>
25 #include <asm/unwind.h>
26 #include <asm/mach_desc.h>
27 #include <asm/smp.h>
29 #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x))
31 unsigned int intr_to_DE_cnt;
33 /* Part of U-boot ABI: see head.S */
34 int __initdata uboot_tag;
35 char __initdata *uboot_arg;
37 const struct machine_desc *machine_desc;
39 struct task_struct *_current_task[NR_CPUS]; /* For stack switching */
41 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
43 static const struct id_to_str arc_cpu_rel[] = {
44 #ifdef CONFIG_ISA_ARCOMPACT
45 { 0x34, "R4.10"},
46 { 0x35, "R4.11"},
47 #else
48 { 0x51, "R2.0" },
49 { 0x52, "R2.1" },
50 { 0x53, "R3.0" },
51 #endif
52 { 0x00, NULL }
55 static const struct id_to_str arc_cpu_nm[] = {
56 #ifdef CONFIG_ISA_ARCOMPACT
57 { 0x20, "ARC 600" },
58 { 0x30, "ARC 770" }, /* 750 identified seperately */
59 #else
60 { 0x40, "ARC EM" },
61 { 0x50, "ARC HS38" },
62 #endif
63 { 0x00, "Unknown" }
66 static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
68 if (is_isa_arcompact()) {
69 struct bcr_iccm_arcompact iccm;
70 struct bcr_dccm_arcompact dccm;
72 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
73 if (iccm.ver) {
74 cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */
75 cpu->iccm.base_addr = iccm.base << 16;
78 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
79 if (dccm.ver) {
80 unsigned long base;
81 cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */
83 base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD);
84 cpu->dccm.base_addr = base & ~0xF;
86 } else {
87 struct bcr_iccm_arcv2 iccm;
88 struct bcr_dccm_arcv2 dccm;
89 unsigned long region;
91 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
92 if (iccm.ver) {
93 cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */
94 if (iccm.sz00 == 0xF && iccm.sz01 > 0)
95 cpu->iccm.sz <<= iccm.sz01;
97 region = read_aux_reg(ARC_REG_AUX_ICCM);
98 cpu->iccm.base_addr = region & 0xF0000000;
101 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
102 if (dccm.ver) {
103 cpu->dccm.sz = 256 << dccm.sz0;
104 if (dccm.sz0 == 0xF && dccm.sz1 > 0)
105 cpu->dccm.sz <<= dccm.sz1;
107 region = read_aux_reg(ARC_REG_AUX_DCCM);
108 cpu->dccm.base_addr = region & 0xF0000000;
113 static void read_arc_build_cfg_regs(void)
115 struct bcr_timer timer;
116 struct bcr_generic bcr;
117 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
118 const struct id_to_str *tbl;
120 FIX_PTR(cpu);
122 READ_BCR(AUX_IDENTITY, cpu->core);
123 READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
125 for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) {
126 if (cpu->core.family == tbl->id) {
127 cpu->details = tbl->str;
128 break;
132 for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) {
133 if ((cpu->core.family & 0xF0) == tbl->id)
134 break;
136 cpu->name = tbl->str;
138 READ_BCR(ARC_REG_TIMERS_BCR, timer);
139 cpu->extn.timer0 = timer.t0;
140 cpu->extn.timer1 = timer.t1;
141 cpu->extn.rtc = timer.rtc;
143 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
145 READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
147 cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */
148 cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */
149 cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */
150 cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0;
151 cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */
152 cpu->extn.swape = (cpu->core.family >= 0x34) ? 1 :
153 IS_ENABLED(CONFIG_ARC_HAS_SWAPE);
155 READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);
157 /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
158 read_decode_ccm_bcr(cpu);
160 read_decode_mmu_bcr();
161 read_decode_cache_bcr();
163 if (is_isa_arcompact()) {
164 struct bcr_fp_arcompact sp, dp;
165 struct bcr_bpu_arcompact bpu;
167 READ_BCR(ARC_REG_FP_BCR, sp);
168 READ_BCR(ARC_REG_DPFP_BCR, dp);
169 cpu->extn.fpu_sp = sp.ver ? 1 : 0;
170 cpu->extn.fpu_dp = dp.ver ? 1 : 0;
172 READ_BCR(ARC_REG_BPU_BCR, bpu);
173 cpu->bpu.ver = bpu.ver;
174 cpu->bpu.full = bpu.fam ? 1 : 0;
175 if (bpu.ent) {
176 cpu->bpu.num_cache = 256 << (bpu.ent - 1);
177 cpu->bpu.num_pred = 256 << (bpu.ent - 1);
179 } else {
180 struct bcr_fp_arcv2 spdp;
181 struct bcr_bpu_arcv2 bpu;
183 READ_BCR(ARC_REG_FP_V2_BCR, spdp);
184 cpu->extn.fpu_sp = spdp.sp ? 1 : 0;
185 cpu->extn.fpu_dp = spdp.dp ? 1 : 0;
187 READ_BCR(ARC_REG_BPU_BCR, bpu);
188 cpu->bpu.ver = bpu.ver;
189 cpu->bpu.full = bpu.ft;
190 cpu->bpu.num_cache = 256 << bpu.bce;
191 cpu->bpu.num_pred = 2048 << bpu.pte;
194 READ_BCR(ARC_REG_AP_BCR, bcr);
195 cpu->extn.ap = bcr.ver ? 1 : 0;
197 READ_BCR(ARC_REG_SMART_BCR, bcr);
198 cpu->extn.smart = bcr.ver ? 1 : 0;
200 READ_BCR(ARC_REG_RTT_BCR, bcr);
201 cpu->extn.rtt = bcr.ver ? 1 : 0;
203 cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;
205 /* some hacks for lack of feature BCR info in old ARC700 cores */
206 if (is_isa_arcompact()) {
207 if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */
208 cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
209 else
210 cpu->isa.atomic = cpu->isa.atomic1;
212 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
214 /* there's no direct way to distinguish 750 vs. 770 */
215 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
216 cpu->name = "ARC750";
220 static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
222 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
223 struct bcr_identity *core = &cpu->core;
224 int i, n = 0;
226 FIX_PTR(cpu);
228 n += scnprintf(buf + n, len - n,
229 "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
230 core->family, core->cpu_id, core->chip_id);
232 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s\n",
233 cpu_id, cpu->name, cpu->details,
234 is_isa_arcompact() ? "ARCompact" : "ARCv2",
235 IS_AVAIL1(cpu->isa.be, "[Big-Endian]"));
237 n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
238 IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
239 IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
240 IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ",
241 CONFIG_ARC_HAS_RTC));
243 n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s",
244 IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
245 IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
246 IS_AVAIL1(cpu->isa.unalign, "unalign (not used)"));
248 if (i)
249 n += scnprintf(buf + n, len - n, "\n\t\t: ");
251 if (cpu->extn_mpy.ver) {
252 if (cpu->extn_mpy.ver <= 0x2) { /* ARCompact */
253 n += scnprintf(buf + n, len - n, "mpy ");
254 } else {
255 int opt = 2; /* stock MPY/MPYH */
257 if (cpu->extn_mpy.dsp) /* OPT 7-9 */
258 opt = cpu->extn_mpy.dsp + 6;
260 n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt);
264 n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
265 IS_AVAIL1(cpu->isa.div_rem, "div_rem "),
266 IS_AVAIL1(cpu->extn.norm, "norm "),
267 IS_AVAIL1(cpu->extn.barrel, "barrel-shift "),
268 IS_AVAIL1(cpu->extn.swap, "swap "),
269 IS_AVAIL1(cpu->extn.minmax, "minmax "),
270 IS_AVAIL1(cpu->extn.crc, "crc "),
271 IS_AVAIL2(cpu->extn.swape, "swape", CONFIG_ARC_HAS_SWAPE));
273 if (cpu->bpu.ver)
274 n += scnprintf(buf + n, len - n,
275 "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n",
276 IS_AVAIL1(cpu->bpu.full, "full"),
277 IS_AVAIL1(!cpu->bpu.full, "partial"),
278 cpu->bpu.num_cache, cpu->bpu.num_pred);
280 return buf;
283 static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
285 int n = 0;
286 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
288 FIX_PTR(cpu);
290 n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base);
292 if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
293 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
294 IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
295 IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
297 if (cpu->extn.debug)
298 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n",
299 IS_AVAIL1(cpu->extn.ap, "ActionPoint "),
300 IS_AVAIL1(cpu->extn.smart, "smaRT "),
301 IS_AVAIL1(cpu->extn.rtt, "RTT "));
303 if (cpu->dccm.sz || cpu->iccm.sz)
304 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
305 cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
306 cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
308 n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n",
309 EF_ARC_OSABI_CURRENT >> 8,
310 EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ?
311 "no-legacy-syscalls" : "64-bit data any register aligned");
313 return buf;
316 static void arc_chk_core_config(void)
318 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
319 int fpu_enabled;
321 if (!cpu->extn.timer0)
322 panic("Timer0 is not present!\n");
324 if (!cpu->extn.timer1)
325 panic("Timer1 is not present!\n");
327 #ifdef CONFIG_ARC_HAS_DCCM
329 * DCCM can be arbit placed in hardware.
330 * Make sure it's placement/sz matches what Linux is built with
332 if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
333 panic("Linux built with incorrect DCCM Base address\n");
335 if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz)
336 panic("Linux built with incorrect DCCM Size\n");
337 #endif
339 #ifdef CONFIG_ARC_HAS_ICCM
340 if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz)
341 panic("Linux built with incorrect ICCM Size\n");
342 #endif
345 * FP hardware/software config sanity
346 * -If hardware contains DPFP, kernel needs to save/restore FPU state
347 * -If not, it will crash trying to save/restore the non-existant regs
349 * (only DPDP checked since SP has no arch visible regs)
351 fpu_enabled = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);
353 if (cpu->extn.fpu_dp && !fpu_enabled)
354 pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n");
355 else if (!cpu->extn.fpu_dp && fpu_enabled)
356 panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n");
360 * Initialize and setup the processor core
361 * This is called by all the CPUs thus should not do special case stuff
362 * such as only for boot CPU etc
365 void setup_processor(void)
367 char str[512];
368 int cpu_id = smp_processor_id();
370 read_arc_build_cfg_regs();
371 arc_init_IRQ();
373 printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
375 arc_mmu_init();
376 arc_cache_init();
378 printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
379 printk(arc_platform_smp_cpuinfo());
381 arc_chk_core_config();
384 static inline int is_kernel(unsigned long addr)
386 if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end)
387 return 1;
388 return 0;
391 void __init setup_arch(char **cmdline_p)
393 #ifdef CONFIG_ARC_UBOOT_SUPPORT
394 /* make sure that uboot passed pointer to cmdline/dtb is valid */
395 if (uboot_tag && is_kernel((unsigned long)uboot_arg))
396 panic("Invalid uboot arg\n");
398 /* See if u-boot passed an external Device Tree blob */
399 machine_desc = setup_machine_fdt(uboot_arg); /* uboot_tag == 2 */
400 if (!machine_desc)
401 #endif
403 /* No, so try the embedded one */
404 machine_desc = setup_machine_fdt(__dtb_start);
405 if (!machine_desc)
406 panic("Embedded DT invalid\n");
409 * If we are here, it is established that @uboot_arg didn't
410 * point to DT blob. Instead if u-boot says it is cmdline,
411 * append to embedded DT cmdline.
412 * setup_machine_fdt() would have populated @boot_command_line
414 if (uboot_tag == 1) {
415 /* Ensure a whitespace between the 2 cmdlines */
416 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
417 strlcat(boot_command_line, uboot_arg,
418 COMMAND_LINE_SIZE);
422 /* Save unparsed command line copy for /proc/cmdline */
423 *cmdline_p = boot_command_line;
425 /* To force early parsing of things like mem=xxx */
426 parse_early_param();
428 /* Platform/board specific: e.g. early console registration */
429 if (machine_desc->init_early)
430 machine_desc->init_early();
432 smp_init_cpus();
434 setup_processor();
435 setup_arch_memory();
437 /* copy flat DT out of .init and then unflatten it */
438 unflatten_and_copy_device_tree();
440 /* Can be issue if someone passes cmd line arg "ro"
441 * But that is unlikely so keeping it as it is
443 root_mountflags &= ~MS_RDONLY;
445 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
446 conswitchp = &dummy_con;
447 #endif
449 arc_unwind_init();
452 static int __init customize_machine(void)
454 if (machine_desc->init_machine)
455 machine_desc->init_machine();
457 return 0;
459 arch_initcall(customize_machine);
461 static int __init init_late_machine(void)
463 if (machine_desc->init_late)
464 machine_desc->init_late();
466 return 0;
468 late_initcall(init_late_machine);
470 * Get CPU information for use by the procfs.
473 #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c)))
474 #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p))
476 static int show_cpuinfo(struct seq_file *m, void *v)
478 char *str;
479 int cpu_id = ptr_to_cpu(v);
480 struct device_node *core_clk = of_find_node_by_name(NULL, "core_clk");
481 u32 freq = 0;
483 if (!cpu_online(cpu_id)) {
484 seq_printf(m, "processor [%d]\t: Offline\n", cpu_id);
485 goto done;
488 str = (char *)__get_free_page(GFP_TEMPORARY);
489 if (!str)
490 goto done;
492 seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
494 of_property_read_u32(core_clk, "clock-frequency", &freq);
495 if (freq)
496 seq_printf(m, "CPU speed\t: %u.%02u Mhz\n",
497 freq / 1000000, (freq / 10000) % 100);
499 seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
500 loops_per_jiffy / (500000 / HZ),
501 (loops_per_jiffy / (5000 / HZ)) % 100);
503 seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
504 seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
505 seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
506 seq_printf(m, arc_platform_smp_cpuinfo());
508 free_page((unsigned long)str);
509 done:
510 seq_printf(m, "\n");
512 return 0;
515 static void *c_start(struct seq_file *m, loff_t *pos)
518 * Callback returns cpu-id to iterator for show routine, NULL to stop.
519 * However since NULL is also a valid cpu-id (0), we use a round-about
520 * way to pass it w/o having to kmalloc/free a 2 byte string.
521 * Encode cpu-id as 0xFFcccc, which is decoded by show routine.
523 return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
526 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
528 ++*pos;
529 return c_start(m, pos);
532 static void c_stop(struct seq_file *m, void *v)
536 const struct seq_operations cpuinfo_op = {
537 .start = c_start,
538 .next = c_next,
539 .stop = c_stop,
540 .show = show_cpuinfo
543 static DEFINE_PER_CPU(struct cpu, cpu_topology);
545 static int __init topology_init(void)
547 int cpu;
549 for_each_present_cpu(cpu)
550 register_cpu(&per_cpu(cpu_topology, cpu), cpu);
552 return 0;
555 subsys_initcall(topology_init);